core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Collapse)	Author
2018-10-16	(1) Fixed width definitions and cleaned up constants as part of checking ↵HEAD master	Joachim Strömbergson
	that all registers are being reset. (2) Cleaned up tasks and removed timescale directives to silence lint.
2014-10-02	Updating testbenches to match new interfaces and use the api to read and ↵	Joachim Strömbergson
	write data.
2014-09-11	Update after completion of rtl and debug of rtl using the updated testbench. ↵	Joachim Strömbergson
	Now it works.
2014-09-11	Adding initial versions of rtl and tb for the mixer.	Joachim Strömbergson