core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Expand)	Author
2015-07-18	Read out all data in the fifo by looking at the syn flag. The fifo simulates ok.	Joachim Strömbergson
2015-07-18	Writing a new word into the fifo.	Joachim Strömbergson
2015-07-18	Adding task for reading words from the fifo. Reading out more than 16 words. ...	Joachim Strömbergson
2015-07-17	Adding more functionality to observe the fifo during test.	Joachim Strömbergson
2015-07-17	Adding task to dump fifo contents.	Joachim Strömbergson
2015-07-17	Adding more test functionality in the fifo testbench. Now we generates severa...	Joachim Strömbergson
2015-04-02	(1) Added a state in the write fifo machine to actually drop request between ...	Joachim Strömbergson
2015-04-02	Fixed syntax and added init functionality for testing the dut.	Joachim Strömbergson
2015-04-01	Adding initial version of testbench for the csprng fifo.	Joachim Strömbergson