core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Expand)	Author
2014-11-20	Reworked the csprng output fifo to really take advantage of the fact that the...	Joachim Strömbergson
2014-11-20	Updates after linting.	Joachim Strömbergson
2014-11-20	(1) Reducing timepout for entropy sources. Updated interface for sha-512 to m...	Joachim Strömbergson
2014-10-02	Removing wrappers since they are not used.	Joachim Strömbergson
2014-10-02	Updating trng to debugged version.	Joachim Strömbergson
2014-09-27	Adding debug port for mixer and csprng. In the csprng the debug_update will t...	Joachim Strömbergson
2014-09-26	Updating source to the latest and greatest. In this version the entropy sourc...	Joachim Strömbergson
2014-09-18	Updates after synthesis of the complete trng.	Joachim Strömbergson
2014-09-16	Adding a minor readme to explain when to use the entropy wrappers.	Joachim Strömbergson
2014-09-16	Adding initial version of wrapper for the avalance entropy core to be used du...	Joachim Strömbergson
2014-09-16	Fixed incorrect bit index.	Joachim Strömbergson
2014-09-16	More debug fixes. We add one extra wait cycle to allow the mixer to detect th...	Joachim Strömbergson
2014-09-16	Debug fixes found during simulation. Now the trng generates data and provides...	Joachim Strömbergson
2014-09-12	Adding first version of complete trng.	Joachim Strömbergson
2014-09-11	Update after completion of rtl and debug of rtl using the updated testbench. ...	Joachim Strömbergson
2014-09-11	Adding initial versions of rtl and tb for the mixer.	Joachim Strömbergson
2014-09-11	Adding rtl and tb for the csprng part of the trng.	Joachim Strömbergson