core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Collapse)	Author
2015-03-25	streamline(?) api_mux, register data for eim output	Paul Selkirk

2014-11-20	Updates after linting.	Joachim Strömbergson

2014-11-20	(1) Reducing timepout for entropy sources. Updated interface for sha-512 to ↵	Joachim Strömbergson
	match new interface with work factor ports. We are not using the work factor here at the moment.
2014-10-02	Updating trng to debugged version.	Joachim Strömbergson

2014-09-27	Adding debug port for mixer and csprng. In the csprng the debug_update will ↵	Joachim Strömbergson
	trigger fifo extraction and thus force random number generation.
2014-09-26	Updating source to the latest and greatest. In this version the entropy ↵	Joachim Strömbergson
	sources works and all modules have correct intterface.
2014-09-11	Update after completion of rtl and debug of rtl using the updated testbench. ↵	Joachim Strömbergson
	Now it works.
2014-09-11	Adding initial versions of rtl and tb for the mixer.	Joachim Strömbergson