| Age | Commit message (Expand) | Author |
|---|---|---|
| 2014-09-16 | Fixed incorrect bit index. | Joachim StroĢmbergson |
| 2014-09-11 | Adding rtl and tb for the csprng part of the trng. | Joachim StroĢmbergson |
 |
index : core/rng/trng | |
| True Random Number Generator core implemented in Verilog | git repositories |
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