core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Expand)	Author
2015-12-13	whack copyrights	Paul Selkirk
2015-07-18	Fixed replication sizes found during lintint.	Joachim Strömbergson
2015-07-18	Simplified the pointer handling. Fixed size of counter. Now all positions in ...	Joachim Strömbergson
2015-05-22	(1) Added a cipher block statistics counter. (2) Cleaned up the csprng code a...	Joachim Strömbergson
2015-04-02	(1) Added a state in the write fifo machine to actually drop request between ...	Joachim Strömbergson
2015-04-01	Cleanup and fixes of calculations.	Joachim Strömbergson
2015-03-26	Changed to Verilog 2001 part select for word extraction.	Joachim Strömbergson
2015-03-26	More cleanup. Completed parameterization of fifo. Fixed incorrect size of con...	Joachim Strömbergson
2015-03-26	Cleanup from linting. Changing to parameterized fifo pointers. Fixed bug in b...	Joachim Strömbergson
2014-11-20	Reworked the csprng output fifo to really take advantage of the fact that the...	Joachim Strömbergson
2014-09-16	Fixed incorrect bit index.	Joachim Strömbergson
2014-09-11	Adding rtl and tb for the csprng part of the trng.	Joachim Strömbergson