| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2014-11-20 | Reworked the csprng output fifo to really take advantage of the fact that ↵ | Joachim Strömbergson | |
| the csprng delivers blocks of 512 bits. Removed trailing whitespaces and linted code. | |||
| 2014-09-16 | Fixed incorrect bit index. | Joachim Strömbergson | |
| 2014-09-11 | Adding rtl and tb for the csprng part of the trng. | Joachim Strömbergson | |
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index : core/rng/trng | |
| True Random Number Generator core implemented in Verilog | git repositories |
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