core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Expand)	Author
2015-11-17	Harmonize status valid bit with other cores.	Paul Selkirk
2015-11-16	harmonize ctrl and status addresses with other cores	Paul Selkirk
2015-09-07	(1) Debugged the block stat counter. (2) Added missing port type. (3) Removed...	Joachim Strömbergson
2015-09-02	Changed the max number of blocks to force reseed once every 256 TByte. Change...	Joachim Strömbergson
2015-08-20	Adding a stat counter for number of CSPRNG reseeds.	Joachim Strömbergson
2015-05-22	(1) Added a cipher block statistics counter. (2) Cleaned up the csprng code a...	Joachim Strömbergson
2015-04-28	(1) Remove the delayed read for EIM (see core/platform/novena commit 2f58e8f)...	Paul Selkirk
2015-04-27	Adding name and version fields to the csprng.	Joachim Strömbergson
2015-04-01	Cleanup and fixes of calculations.	Joachim Strömbergson
2015-03-26	Minor cleanup: Changed to localparam for internal parameters. Merged reg upda...	Joachim Strömbergson
2015-03-25	streamline(?) api_mux, register data for eim output	Paul Selkirk
2014-11-20	Updates after linting.	Joachim Strömbergson
2014-10-02	Updating trng to debugged version.	Joachim Strömbergson
2014-09-27	Adding debug port for mixer and csprng. In the csprng the debug_update will t...	Joachim Strömbergson
2014-09-26	Updating source to the latest and greatest. In this version the entropy sourc...	Joachim Strömbergson
2014-09-18	Updates after synthesis of the complete trng.	Joachim Strömbergson
2014-09-16	More debug fixes. We add one extra wait cycle to allow the mixer to detect th...	Joachim Strömbergson
2014-09-11	Adding rtl and tb for the csprng part of the trng.	Joachim Strömbergson