core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Collapse)	Author
2018-10-16	(1) Fixed width definitions and cleaned up constants as part of checking ↵HEAD master	Joachim Strömbergson
	that all registers are being reset. (2) Cleaned up tasks and removed timescale directives to silence lint.
2015-12-13	whack copyrights	Paul Selkirk

2015-11-17	Harmonize status valid bit with other cores.	Paul Selkirk

2015-11-16	harmonize ctrl and status addresses with other cores	Paul Selkirk

2015-09-07	(1) Debugged the block stat counter. (2) Added missing port type. (3) ↵	Joachim Strömbergson
	Removed second define for default number of blocks.
2015-09-02	Changed the max number of blocks to force reseed once every 256 TByte. ↵	Joachim Strömbergson
	Changed default number of blocks to do reseed once every 16 GByte.
2015-08-20	Adding a stat counter for number of CSPRNG reseeds.	Joachim Strömbergson

2015-05-22	(1) Added a cipher block statistics counter. (2) Cleaned up the csprng code ↵	Joachim Strömbergson
	and connected discard for fast restart of trng. (3) Added addresses for allowing API to write a known seed to allow test mode. (3) Fixed a number of minor issues during linting. (4) Fixed the csprng testbench to actually generate data as well as displaying the block stat counter.
2015-04-28	(1) Remove the delayed read for EIM (see core/platform/novena commit ↵	Paul Selkirk
	2f58e8f). (2) Add the code to read the csprng name and version registers.
2015-04-27	Adding name and version fields to the csprng.	Joachim Strömbergson

2015-04-01	Cleanup and fixes of calculations.	Joachim Strömbergson

2015-03-26	Minor cleanup: Changed to localparam for internal parameters. Merged reg ↵	Joachim Strömbergson
	update processes to one. Changed name of api read data hold reg and added better update vector name for it.
2015-03-25	streamline(?) api_mux, register data for eim output	Paul Selkirk

2014-11-20	Updates after linting.	Joachim Strömbergson

2014-10-02	Updating trng to debugged version.	Joachim Strömbergson

2014-09-27	Adding debug port for mixer and csprng. In the csprng the debug_update will ↵	Joachim Strömbergson
	trigger fifo extraction and thus force random number generation.
2014-09-26	Updating source to the latest and greatest. In this version the entropy ↵	Joachim Strömbergson
	sources works and all modules have correct intterface.
2014-09-18	Updates after synthesis of the complete trng.	Joachim Strömbergson

2014-09-16	More debug fixes. We add one extra wait cycle to allow the mixer to detect ↵	Joachim Strömbergson
	that we want more seed.
2014-09-11	Adding rtl and tb for the csprng part of the trng.	Joachim Strömbergson