core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Collapse)	Author
2015-04-28	(1) Remove the delayed read for EIM (see core/platform/novena commit ↵	Paul Selkirk
	2f58e8f). (2) Add the code to read the csprng name and version registers.
2015-04-27	Adding name and version fields to the csprng.	Joachim Strömbergson

2015-04-01	Cleanup and fixes of calculations.	Joachim Strömbergson

2015-03-26	Minor cleanup: Changed to localparam for internal parameters. Merged reg ↵	Joachim Strömbergson
	update processes to one. Changed name of api read data hold reg and added better update vector name for it.
2015-03-25	streamline(?) api_mux, register data for eim output	Paul Selkirk

2014-11-20	Updates after linting.	Joachim Strömbergson

2014-10-02	Updating trng to debugged version.	Joachim Strömbergson

2014-09-27	Adding debug port for mixer and csprng. In the csprng the debug_update will ↵	Joachim Strömbergson
	trigger fifo extraction and thus force random number generation.
2014-09-26	Updating source to the latest and greatest. In this version the entropy ↵	Joachim Strömbergson
	sources works and all modules have correct intterface.
2014-09-18	Updates after synthesis of the complete trng.	Joachim Strömbergson

2014-09-16	More debug fixes. We add one extra wait cycle to allow the mixer to detect ↵	Joachim Strömbergson
	that we want more seed.
2014-09-11	Adding rtl and tb for the csprng part of the trng.	Joachim Strömbergson