core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Expand)	Author
2015-10-05	(1) Minor cleanup. Removed unneeded code blocks and comments. (2) Moved debug...	Joachim Strömbergson
2015-10-05	(1) Changed API addresses for ctrl and status registers - HEADSUP: this might...	Joachim Strömbergson
2015-04-28	(1) Remove the delayed read for EIM (see core/platform/novena commit 2f58e8f)...	Paul Selkirk
2015-04-27	Updated the trng version number to sometning that better reflects that it act...	Joachim Strömbergson
2015-03-26	Cleanup: Merged separate clocked processes. Fixed incorrect bit widths. Chang...	Joachim Strömbergson
2015-03-25	streamline(?) api_mux, register data for eim output	Paul Selkirk
2014-11-20	Updates after linting.	Joachim Strömbergson
2014-10-02	Updating trng to debugged version.	Joachim Strömbergson
2014-09-27	Adding debug port for mixer and csprng. In the csprng the debug_update will t...	Joachim Strömbergson
2014-09-26	Updating source to the latest and greatest. In this version the entropy sourc...	Joachim Strömbergson
2014-09-18	Updates after synthesis of the complete trng.	Joachim Strömbergson
2014-09-16	Debug fixes found during simulation. Now the trng generates data and provides...	Joachim Strömbergson
2014-09-12	Adding first version of complete trng.	Joachim Strömbergson