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-rw-r--r--src/rtl/trng_csprng_fifo.v8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/rtl/trng_csprng_fifo.v b/src/rtl/trng_csprng_fifo.v
index e90d23d..e3fe4fb 100644
--- a/src/rtl/trng_csprng_fifo.v
+++ b/src/rtl/trng_csprng_fifo.v
@@ -149,8 +149,8 @@ module trng_csprng_fifo(
fifo_mem[02] <= {16{32'h00000000}};
fifo_mem[03] <= {16{32'h00000000}};
mux_data_ptr_reg <= 4'h0;
- rd_ptr_reg <= {(FIFO_ADDR_BITS - 1){1'b0}};
- wr_ptr_reg <= {(FIFO_ADDR_BITS - 1){1'b0}};
+ rd_ptr_reg <= {(FIFO_ADDR_BITS){1'b0}};
+ wr_ptr_reg <= {(FIFO_ADDR_BITS){1'b0}};
fifo_ctr_reg <= {FIFO_ADDR_BITS{1'b0}};
rnd_data_reg <= 32'h00000000;
rnd_syn_reg <= 0;
@@ -296,7 +296,7 @@ module trng_csprng_fifo(
//----------------------------------------------------------------
always @*
begin : fifo_ctr
- fifo_ctr_new = {FIFO_ADDR_BITS{1'b0}};
+ fifo_ctr_new = {(FIFO_ADDR_BITS + 1){1'b0}};
fifo_ctr_we = 0;
fifo_empty = 0;
fifo_full = 0;
@@ -313,7 +313,7 @@ module trng_csprng_fifo(
if (fifo_ctr_rst)
begin
- fifo_ctr_new = {FIFO_ADDR_BITS{1'b0}};
+ fifo_ctr_new = {(FIFO_ADDR_BITS + 1){1'b0}};
fifo_ctr_we = 1;
end