Adding Quartus project files to build trng for TerasIC DE0 Nano board. This also includes a prebuilt config file.

4 files changed, 160 insertions, 0 deletions

diff --git a/toolruns/quartus/terasic_de0_nano/trng.qpf b/toolruns/quartus/terasic_de0_nano/trng.qpf
new file mode 100644
index 0000000..1902c4f
--- /dev/null
+++ b/toolruns/quartus/terasic_de0_nano/trng.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2014 Altera Corporation

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, Altera MegaCore Function License 

+# Agreement, or other applicable license agreement, including, 

+# without limitation, that your use is for the sole purpose of 

+# programming logic devices manufactured by Altera and sold by 

+# Altera or its authorized distributors.  Please refer to the 

+# applicable agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus II 64-Bit

+# Version 13.1.2 Build 173 01/15/2014 SJ Web Edition

+# Date created = 14:45:00  September 18, 2014

+#

+# -------------------------------------------------------------------------- #

+

+QUARTUS_VERSION = "13.1"

+DATE = "14:45:00  September 18, 2014"

+

+# Revisions

+

+PROJECT_REVISION = "trng"

diff --git a/toolruns/quartus/terasic_de0_nano/trng.qsf b/toolruns/quartus/terasic_de0_nano/trng.qsf
new file mode 100644
index 0000000..f1767e0
--- /dev/null
+++ b/toolruns/quartus/terasic_de0_nano/trng.qsf
@@ -0,0 +1,90 @@
+# -------------------------------------------------------------------------- #

+#

+# Copyright (C) 1991-2014 Altera Corporation

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, Altera MegaCore Function License 

+# Agreement, or other applicable license agreement, including, 

+# without limitation, that your use is for the sole purpose of 

+# programming logic devices manufactured by Altera and sold by 

+# Altera or its authorized distributors.  Please refer to the 

+# applicable agreement for further details.

+#

+# -------------------------------------------------------------------------- #

+#

+# Quartus II 64-Bit

+# Version 13.1.2 Build 173 01/15/2014 SJ Web Edition

+# Date created = 14:45:00  September 18, 2014

+#

+# -------------------------------------------------------------------------- #

+#

+# Notes:

+#

+# 1) The default values for assignments are stored in the file:

+#		trng_assignment_defaults.qdf

+#    If this file doesn't exist, see file:

+#		assignment_defaults.qdf

+#

+# 2) Altera recommends that you do not modify this file. This

+#    file is updated automatically by the Quartus II software

+#    and any changes you make may be lost or overwritten.

+#

+# -------------------------------------------------------------------------- #

+

+

+set_global_assignment -name FAMILY "Cyclone IV E"

+set_global_assignment -name DEVICE EP4CE22F17C6

+set_global_assignment -name TOP_LEVEL_ENTITY trng

+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1

+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:45:00  SEPTEMBER 18, 2014"

+set_global_assignment -name LAST_QUARTUS_VERSION 13.1

+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

+set_instance_assignment -name IO_STANDARD "2.5 V" -to clk

+set_location_assignment PIN_R8 -to clk

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reset_n

+set_location_assignment PIN_J15 -to reset_n

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[0]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[1]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[2]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[3]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[4]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[5]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[6]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[7]

+set_location_assignment PIN_A15 -to debug[0]

+set_location_assignment PIN_A13 -to debug[1]

+set_location_assignment PIN_B13 -to debug[2]

+set_location_assignment PIN_A11 -to debug[3]

+set_location_assignment PIN_D1 -to debug[4]

+set_location_assignment PIN_F3 -to debug[5]

+set_location_assignment PIN_B1 -to debug[6]

+set_location_assignment PIN_L3 -to debug[7]

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug_update

+set_location_assignment PIN_E1 -to debug_update

+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to avalanche_noise

+set_location_assignment PIN_D3 -to avalanche_noise

+set_global_assignment -name VERILOG_FILE ../../../../avalanche_entropy/src/rtl/avalanche_entropy_core.v

+set_global_assignment -name VERILOG_FILE ../../../../avalanche_entropy/src/rtl/avalanche_entropy.v

+set_global_assignment -name VERILOG_FILE ../../../../rosc_entropy/src/rtl/rosc_entropy.v

+set_global_assignment -name VERILOG_FILE ../../../../rosc_entropy/src/rtl/rosc.v

+set_global_assignment -name VERILOG_FILE ../../../../rosc_entropy/src/rtl/rosc_entropy_core.v

+set_global_assignment -name VERILOG_FILE ../../../../sha512/src/rtl/sha512_w_mem.v

+set_global_assignment -name VERILOG_FILE ../../../../sha512/src/rtl/sha512_k_constants.v

+set_global_assignment -name VERILOG_FILE ../../../../sha512/src/rtl/sha512_h_constants.v

+set_global_assignment -name VERILOG_FILE ../../../../sha512/src/rtl/sha512_core.v

+set_global_assignment -name VERILOG_FILE ../../../../chacha/src/rtl/chacha_qr.v

+set_global_assignment -name VERILOG_FILE ../../../../chacha/src/rtl/chacha_core.v

+set_global_assignment -name VERILOG_FILE ../../../src/rtl/trng_mixer.v

+set_global_assignment -name VERILOG_FILE ../../../src/rtl/trng_csprng_fifo.v

+set_global_assignment -name VERILOG_FILE ../../../src/rtl/trng_csprng.v

+set_global_assignment -name VERILOG_FILE ../../../src/rtl/trng.v

+set_global_assignment -name SDC_FILE trng.sdc

+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/toolruns/quartus/terasic_de0_nano/trng.sdc b/toolruns/quartus/terasic_de0_nano/trng.sdc
new file mode 100644
index 0000000..eac8536
--- /dev/null
+++ b/toolruns/quartus/terasic_de0_nano/trng.sdc
@@ -0,0 +1,40 @@
+#************************************************************

+# THIS IS A WIZARD-GENERATED FILE.                           

+#

+# Version 13.1.2 Build 173 01/15/2014 SJ Web Edition

+#

+#************************************************************

+

+# Copyright (C) 1991-2014 Altera Corporation

+# Your use of Altera Corporation's design tools, logic functions 

+# and other software and tools, and its AMPP partner logic 

+# functions, and any output files from any of the foregoing 

+# (including device programming or simulation files), and any 

+# associated documentation or information are expressly subject 

+# to the terms and conditions of the Altera Program License 

+# Subscription Agreement, Altera MegaCore Function License 

+# Agreement, or other applicable license agreement, including, 

+# without limitation, that your use is for the sole purpose of 

+# programming logic devices manufactured by Altera and sold by 

+# Altera or its authorized distributors.  Please refer to the 

+# applicable agreement for further details.

+

+

+

+# Clock constraints

+

+create_clock -name "clk" -period 20.000ns [get_ports {clk}] -waveform {0.000 10.000}

+

+

+# Automatically constrain PLL and other generated clocks

+derive_pll_clocks -create_base_clocks

+

+# Automatically calculate clock uncertainty to jitter and other effects.

+derive_clock_uncertainty

+

+# tsu/th constraints

+

+# tco constraints

+

+# tpd constraints

+

diff --git a/toolruns/quartus/terasic_de0_nano/trng.sof b/toolruns/quartus/terasic_de0_nano/trng.sof
new file mode 100644
index 0000000..b4b39d9
--- /dev/null
+++ b/toolruns/quartus/terasic_de0_nano/trng.sof