Adding more functionality to observe the fifo during test.

1 files changed, 26 insertions, 11 deletions

diff --git a/src/tb/tb_csprng_fifo.v b/src/tb/tb_csprng_fifo.v
index a219dfe..2c4543d 100644
--- a/src/tb/tb_csprng_fifo.v
+++ b/src/tb/tb_csprng_fifo.v
@@ -155,6 +155,7 @@ module tb_csprng_fifo();
       $display("internals:");
       $display("rd_ptr = 0x%02x, wr_ptr = 0x%02x, fifo_ctr = 0x%02x, mux_ptr = 0x%02x",
                dut.rd_ptr_reg, dut.wr_ptr_reg, dut.fifo_ctr_reg, dut.mux_data_ptr_reg);
+      $display("fifo_empty = 0x%01x, fifo_full = 0x%01x", dut.fifo_empty, dut.fifo_full);
       $display("");
     end
   endtask // dump_dut_state
@@ -169,7 +170,6 @@ module tb_csprng_fifo();
     begin
       $display("contents of the fifo");
       $display("--------------------");
-      $display("inputs:");
       $display("fifo_mem[0] = 0x%0128x", dut.fifo_mem[0]);
       $display("fifo_mem[1] = 0x%0128x", dut.fifo_mem[1]);
       $display("fifo_mem[2] = 0x%0128x", dut.fifo_mem[2]);
@@ -265,24 +265,30 @@ module tb_csprng_fifo();
 
 
   //----------------------------------------------------------------
+  // wait_more_data()
+  //
+  // Wait for the DUT to signal that it wants more data.
+  //----------------------------------------------------------------
+  task wait_more_data();
+    begin
+      while (!tb_more_data)
+        #(CLK_PERIOD);
+    end
+  endtask // wait_more_data
+
+
+  //----------------------------------------------------------------
   // write_w512()
   //
   // Writes a 512 bit data word into the fifo.
   //----------------------------------------------------------------
   task write_w512(input [511 : 0] w512);
     begin
-      while (!tb_more_data)
-        begin
-          #(CLK_PERIOD);
-        end
-
       $display("writing to fifo: 0x%0128x", w512);
-      dump_dut_state();
       tb_csprng_data       = w512;
       tb_csprng_data_valid = 1;
       #(CLK_PERIOD);
       tb_csprng_data_valid = 0;
-      dump_dut_state();
     end
   endtask // write_w512
 
@@ -316,12 +322,15 @@ module tb_csprng_fifo();
     reg [31 : 0]  w15;
 
     begin
+      $display("*** Test of FIFO by loading known data and then reading out.");
+
+      dump_dut_state();
       dump_fifo();
 
       i = 8'd0;
 
       // Filling up the memory with data.
-      for (j = 0 ; j < 4 ; j = j + 1)
+      for (j = 0 ; j < 3 ; j = j + 1)
         begin
           w00 = {(i + 8'd15), (i + 8'd15), (i + 8'd15), (i + 8'd15)};
           w01 = {(i + 8'd14), (i + 8'd14), (i + 8'd14), (i + 8'd14)};
@@ -344,11 +353,17 @@ module tb_csprng_fifo();
           w512 = {w00, w01, w02, w03, w04, w05, w06, w07,
                   w08, w09, w10, w11, w12, w13, w14, w15};
 
+          wait_more_data();
+
+          dump_dut_state();
+          dump_fifo();
+
           write_w512(w512);
-          #(CLK_PERIOD);
+          #(2 * CLK_PERIOD);
           i = i + 16;
         end
 
+      dump_dut_state();
       dump_fifo();
 
     end
@@ -372,7 +387,7 @@ module tb_csprng_fifo();
       reset_dut();
       dump_dut_state();
 
-      #(100 * CLK_PERIOD)
+      #(10 * CLK_PERIOD)
 
       fifo_test();