diff options
Diffstat (limited to 'src/rtl/rosc_entropy_core.v')
| -rw-r--r-- | src/rtl/rosc_entropy_core.v | 155 |
1 files changed, 94 insertions, 61 deletions
diff --git a/src/rtl/rosc_entropy_core.v b/src/rtl/rosc_entropy_core.v index 5b4b8c4..98e08e6 100644 --- a/src/rtl/rosc_entropy_core.v +++ b/src/rtl/rosc_entropy_core.v @@ -40,16 +40,17 @@ module rosc_entropy_core( input wire clk, input wire reset_n, - input wire enable, + input wire en, input wire [31 : 0] opa, input wire [31 : 0] opb, - output [31 : 0] entropy, + output wire [31 : 0] raw_entropy, + output wire [31 : 0] rosc_outputs, - output wire [31 : 0] rnd_data, - output wire rnd_valid, - input wire rnd_ack, + output wire [31 : 0] entropy_data, + output wire entropy_valid, + input wire entropy_ack, output wire [7 : 0] debug, input wire debug_update @@ -59,6 +60,7 @@ module rosc_entropy_core( //---------------------------------------------------------------- // Parameters. //---------------------------------------------------------------- + parameter DEBUG_DELAY = 32'h002c4b40; parameter NUM_SHIFT_BITS = 8'h20; parameter SAMPLE_CLK_CYCLES = 8'hff; @@ -68,16 +70,14 @@ module rosc_entropy_core( //---------------------------------------------------------------- reg [31 : 0] ent_shift_reg; reg [31 : 0] ent_shift_new; + reg ent_shift_we; - reg ent_shift_we_reg; - reg ent_shift_we_new; + reg [31 : 0] entropy_reg; + reg entropy_we; - reg [31 : 0] rnd_reg; - reg rnd_we; - - reg rnd_valid_reg; - reg rnd_valid_new; - reg rnd_valid_we; + reg entropy_valid_reg; + reg entropy_valid_new; + reg entropy_valid_we; reg bit_we_reg; reg bit_we_new; @@ -90,7 +90,13 @@ module rosc_entropy_core( reg [7 : 0] sample_ctr_reg; reg [7 : 0] sample_ctr_new; + reg [31 : 0] debug_delay_ctr_reg; + reg [31 : 0] debug_delay_ctr_new; + reg debug_delay_ctr_we; + reg [7 : 0] debug_reg; + reg debug_we; + reg debug_update_reg; @@ -104,10 +110,11 @@ module rosc_entropy_core( //---------------------------------------------------------------- // Concurrent connectivity for ports etc. //---------------------------------------------------------------- - assign entropy = ent_shift_reg; - assign rnd_data = rnd_reg; - assign rnd_valid = rnd_valid_reg; - assign debug = debug_reg; + assign rosc_outputs = rosc_dout; + assign raw_entropy = ent_shift_reg; + assign entropy_data = entropy_reg; + assign entropy_valid = entropy_valid_reg; + assign debug = debug_reg; //---------------------------------------------------------------- @@ -142,22 +149,21 @@ module rosc_entropy_core( begin if (!reset_n) begin - ent_shift_reg <= 32'h00000000; - ent_shift_we_reg <= 0; - rnd_reg <= 32'h00000000; - rnd_valid_reg <= 0; - bit_ctr_reg <= 8'h00; - sample_ctr_reg <= 8'h00; - debug_reg <= 8'h00; - debug_update_reg <= 0; + ent_shift_reg <= 32'h00000000; + entropy_reg <= 32'h00000000; + entropy_valid_reg <= 0; + bit_ctr_reg <= 8'h00; + sample_ctr_reg <= 8'h00; + debug_delay_ctr_reg <= 32'h00000000; + debug_reg <= 8'h00; + debug_update_reg <= 0; end else begin sample_ctr_reg <= sample_ctr_new; - ent_shift_we_reg <= ent_shift_we_new; debug_update_reg <= debug_update; - if (ent_shift_we_reg) + if (ent_shift_we) begin ent_shift_reg <= ent_shift_new; end @@ -167,38 +173,69 @@ module rosc_entropy_core( bit_ctr_reg <= bit_ctr_new; end - if (rnd_we) + if (entropy_we) + begin + entropy_reg <= ent_shift_reg; + end + + if (entropy_valid_we) begin - rnd_reg <= ent_shift_reg; + entropy_valid_reg <= entropy_valid_new; end - if (rnd_valid_we) + if (debug_delay_ctr_we) begin - rnd_valid_reg <= rnd_valid_new; + debug_delay_ctr_reg <= debug_delay_ctr_new; end - if (debug_update_reg) + if (debug_we) begin - debug_reg <= rnd_reg[7 : 0]; + debug_reg <= ent_shift_reg[7 : 0]; end end end // reg_update //---------------------------------------------------------------- - // rnd_out + // debug_out + // + // Logic that updates the debug port. + //---------------------------------------------------------------- + always @* + begin : debug_out + debug_delay_ctr_new = 8'h00000000; + debug_delay_ctr_we = 0; + debug_we = 0; + + if (debug_update_reg) + begin + debug_delay_ctr_new = debug_delay_ctr_reg + 1'b1; + debug_delay_ctr_we = 1; + end + + if (debug_delay_ctr_reg == DEBUG_DELAY) + begin + debug_delay_ctr_new = 8'h00000000; + debug_delay_ctr_we = 1; + debug_we = 1; + end + end + + + //---------------------------------------------------------------- + // entropy_out // // Logic that implements the random output control. If we have - // added more than NUM_SHIFT_BITS we raise the rnd_valid flag. + // added more than NUM_SHIFT_BITS we raise the entropy_valid flag. // When we detect and ACK, the valid flag is dropped. //---------------------------------------------------------------- always @* - begin : rnd_out - bit_ctr_new = 8'h00; - bit_ctr_we = 0; - rnd_we = 0; - rnd_valid_new = 0; - rnd_valid_we = 0; + begin : entropy_out + bit_ctr_new = 8'h00; + bit_ctr_we = 0; + entropy_we = 0; + entropy_valid_new = 0; + entropy_valid_we = 0; if (bit_ctr_inc) begin @@ -210,52 +247,48 @@ module rosc_entropy_core( end else begin - rnd_we = 1; - rnd_valid_new = 1; - rnd_valid_we = 1; + entropy_we = 1; + entropy_valid_new = 1; + entropy_valid_we = 1; end end - if (rnd_ack) + if (entropy_ack) begin - bit_ctr_new = 8'h00; - bit_ctr_we = 1; - rnd_valid_new = 0; - rnd_valid_we = 1; + bit_ctr_new = 8'h00; + bit_ctr_we = 1; + entropy_valid_new = 0; + entropy_valid_we = 1; end end //---------------------------------------------------------------- - // rnd_gen + // entropy_gen // - // Logic that implements the actual random bit value generator + // Logic that implements the actual entropy bit value generator // by XOR mixing the oscillator outputs. These outputs are // sampled once every SAMPLE_CLK_CYCLES. - // - // Note that the update of the shift register is delayed - // one cycle to allow the outputs from the oscillators - // to be updated. //---------------------------------------------------------------- always @* - begin : rnd_gen + begin : entropy_gen reg ent_bit; - bit_ctr_inc = 0; - rosc_we = 0; - ent_shift_we_new = 0; + bit_ctr_inc = 0; + rosc_we = 0; + ent_shift_we = 0; ent_bit = ^rosc_dout; ent_shift_new = {ent_shift_reg[30 : 0], ent_bit}; sample_ctr_new = sample_ctr_reg + 1'b1; - if (enable && (sample_ctr_reg == SAMPLE_CLK_CYCLES)) + if (en && (sample_ctr_reg == SAMPLE_CLK_CYCLES)) begin sample_ctr_new = 8'h00; bit_ctr_inc = 1; rosc_we = 1; - ent_shift_we_new = 1; + ent_shift_we = 1; end end endmodule // rosc_entropy_core |