diff options
Diffstat (limited to 'src/rtl/avalanche_entropy_core.v')
| -rw-r--r-- | src/rtl/avalanche_entropy_core.v | 76 |
1 files changed, 53 insertions, 23 deletions
diff --git a/src/rtl/avalanche_entropy_core.v b/src/rtl/avalanche_entropy_core.v index 582b4b6..115a94d 100644 --- a/src/rtl/avalanche_entropy_core.v +++ b/src/rtl/avalanche_entropy_core.v @@ -72,13 +72,20 @@ module avalanche_entropy_core( //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- - parameter DEBUG_DELAY = 32'h002c4b40; - parameter MIN_ENTROPY_BITS = 6'h20; + // 100000 cycles warmup delay. + localparam WARMUP_CYCLES = 24'h0186a0; + localparam DEBUG_DELAY = 32'h002c4b40; + localparam MIN_ENTROPY_BITS = 6'h20; //---------------------------------------------------------------- // Registers including update variables and write enable. //---------------------------------------------------------------- + reg [23 : 0] warmup_cycle_ctr_reg; + reg [23 : 0] warmup_cycle_ctr_new; + reg warmup_cycle_ctr_we; + reg warmup_done; + reg noise_sample0_reg; reg noise_sample_reg; @@ -118,19 +125,14 @@ module avalanche_entropy_core( //---------------------------------------------------------------- - // Wires. - //---------------------------------------------------------------- - - - //---------------------------------------------------------------- // Concurrent connectivity for ports etc. //---------------------------------------------------------------- - assign entropy_valid = entropy_valid_reg; + assign entropy_valid = entropy_valid_reg & warmup_done; assign entropy_data = entropy_reg; + assign entropy_enabled = enable_reg & warmup_done; assign delta = delta_reg; assign debug = debug_reg; - assign entropy_enabled = enable_reg; //---------------------------------------------------------------- @@ -140,20 +142,21 @@ module avalanche_entropy_core( begin if (!reset_n) begin - noise_sample0_reg <= 1'b0; - noise_sample_reg <= 1'b0; - flank0_reg <= 1'b0; - flank1_reg <= 1'b0; - entropy_valid_reg <= 1'b0; - entropy_reg <= 32'h00000000; - entropy_bit_reg <= 1'b0; - bit_ctr_reg <= 6'h00; - cycle_ctr_reg <= 32'h00000000; - delta_reg <= 32'h00000000; - debug_delay_ctr_reg <= 32'h00000000; - debug_reg <= 8'h00; - debug_update_reg <= 0; - enable_reg <= 0; + noise_sample0_reg <= 1'b0; + noise_sample_reg <= 1'b0; + flank0_reg <= 1'b0; + flank1_reg <= 1'b0; + entropy_valid_reg <= 1'b0; + entropy_reg <= 32'h00000000; + entropy_bit_reg <= 1'b0; + bit_ctr_reg <= 6'h00; + cycle_ctr_reg <= 32'h00000000; + delta_reg <= 32'h00000000; + debug_delay_ctr_reg <= 32'h00000000; + warmup_cycle_ctr_reg <= WARMUP_CYCLES; + debug_reg <= 8'h00; + debug_update_reg <= 0; + enable_reg <= 0; end else begin @@ -171,6 +174,9 @@ module avalanche_entropy_core( enable_reg <= enable; + if (warmup_cycle_ctr_we) + warmup_cycle_ctr_reg <= warmup_cycle_ctr_new; + if (delta_we) begin delta_reg <= cycle_ctr_reg; @@ -226,6 +232,30 @@ module avalanche_entropy_core( //---------------------------------------------------------------- + // warmup_ctr + // + // Logic for the warmup counter. This counter starts + // decreasing when reset lifts and decreases until reaching zero. + // At zero the counter stops and asserts warmup_done. + //---------------------------------------------------------------- + always @* + begin : warmup_ctr + if (warmup_cycle_ctr_reg == 0) + begin + warmup_cycle_ctr_new = 24'h000000; + warmup_cycle_ctr_we = 0; + warmup_done = 1; + end + else + begin + warmup_cycle_ctr_new = warmup_cycle_ctr_reg - 1'b1; + warmup_cycle_ctr_we = 1; + warmup_done = 0; + end + end + + + //---------------------------------------------------------------- // entropy_collect // // We collect entropy by adding the current state of the |