| Age | Commit message (Expand) | Author |
|---|---|---|
| 2014-05-07 | Update of prebuilt FPGA configuration with new coretest. | Joachim Strömbergson |
| 2014-04-01 | Refactored code to allow additions of test cases. Adding dual block message t... | Joachim Strömbergson |
| 2014-03-17 | Adding project, assignment and clock setup files for Quartus and the TerasIC ... | Joachim Strömbergson |
| 2014-03-17 | Adding bitstream file for coretest_hashes on the TerasIC C5G board. | Joachim Strömbergson |
| 2014-03-17 | Adding test program that checks the SHA-1 and SHA-256 cores and do single blo... | Joachim Strömbergson |
| 2014-03-17 | Updating address for uart to 8 bits which should be the default. | Joachim Strömbergson |
| 2014-03-13 | Adding Makefile to build the coretest_hashes subsystem. | Joachim Strömbergson |
| 2014-03-13 | Adding RTL to build the coretest_hashes subsystem with SHA-1 and SHA-256 cores. | Joachim Strömbergson |
| 2014-03-13 | Adding readme and license for the coretest_hashes subsystem. | Joachim Strömbergson |
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index : core/platform/terasic_c5g | |
| Platform-specific files for the TerasIC C5G development board | git repositories |
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