blob: 8b984a2ed4c6cb806faf325b5df1915b7a8807e3 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
|
# Localize all the relative path awfulness in one variable.
CORE_TREE := $(abspath ../../../..)
# Figure out what the native word size is on the build host, because
# the XiLinx tools care for some reason.
WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0)) * 8')
# Parameters to xilinx.mk.
project ?= novena_eim
vendor = xilinx
family = spartan6
part = xc6slx45csg324-3
top_module = novena_top
isedir = /opt/Xilinx/14.7/ISE_DS
xil_env = . $(isedir)/settings$(WORD_SIZE).sh
ucf ?= ../ucf/$(project).ucf
#ucf ?= ../ucf/$(project)-dev_bridge_board.ucf
all: $(project).bit
# Build the default core_selector if it doesn't already exist.
CONFIG = $(CORE_TREE)/platform/common/config
core_selector.v core_vfiles.mk:
$(CONFIG)/config.py -c $(CONFIG)/config.cfg
# Build some different configurations
bare:
$(CONFIG)/config.py -c $(CONFIG)/config.cfg -s bare
$(MAKE) project=$(project)_bare ucf=$(ucf)
trng:
$(CONFIG)/config.py -c $(CONFIG)/config.cfg -s trng
$(MAKE) project=$(project)_trng ucf=$(ucf)
hash:
$(CONFIG)/config.py -c $(CONFIG)/config.cfg -s hash
$(MAKE) project=$(project)_hash ucf=$(ucf)
rsa:
$(CONFIG)/config.py -c $(CONFIG)/config.cfg -s rsa
$(MAKE) project=$(project)_rsa ucf=$(ucf)
# Verilog files that always go with builds on this platform.
vfiles = \
$(CORE_TREE)/platform/novena/eim/rtl/novena_eim.v \
$(CORE_TREE)/platform/novena/common/rtl/novena_regs.v \
$(CORE_TREE)/platform/novena/common/rtl/novena_clkmgr.v \
$(CORE_TREE)/platform/novena/common/rtl/clkmgr_dcm.v \
./core_selector.v \
$(CORE_TREE)/comm/eim/src/rtl/cdc_bus_pulse.v \
$(CORE_TREE)/comm/eim/src/rtl/eim_arbiter_cdc.v \
$(CORE_TREE)/comm/eim/src/rtl/eim_arbiter.v \
$(CORE_TREE)/comm/eim/src/rtl/eim_da_phy.v \
$(CORE_TREE)/comm/eim/src/rtl/eim_indicator.v \
$(CORE_TREE)/comm/eim/src/rtl/eim_regs.v \
$(CORE_TREE)/comm/eim/src/rtl/eim.v
# Verilog files selected by the core configuration script.
-include ./core_vfiles.mk
include xilinx.mk
# 'clean' target collects files by project name, and we just broke that
# by adding configurations
junk += *.bgn *.bit *.bld *.cfi *.drc *.lso *.map *.mcs *.mrp *.ncd *.ngc \
*.ngd *.ngm *.pcf *.post_map.twr *.post_map.twx *.prj *.prm *.psr \
*.scr *.srp *.twr *.twx *_bd.bmm *_bitgen.xwb *_bitgen.xwbt \
*_err.twr *_err.twx *_par.grf *_par.ncd *_par.pad *_par.par \
*_par.ptwx *_par.unroutes *_par.xpi *_par_pad.csv *_par_pad.txt \
*_summary.xml *_usage.xml
distclean: clean
rm core_selector.v core_vfiles.mk
# Fun extras for running verilator as a linter.
VERILATOR_FLAGS = --lint-only --top-module $(top_module) -Wall -Wno-fatal -Wno-DECLFILENAME
lint:
verilator ${VERILATOR_FLAGS} $(vfiles) $(CORE_TREE)/platform/novena/common/rtl/lint-dummy.v
|
