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-rw-r--r--i2c/build/Makefile102
-rw-r--r--i2c/build/xilinx.mk16
-rw-r--r--i2c/rtl/novena_i2c.v14
3 files changed, 53 insertions, 79 deletions
diff --git a/i2c/build/Makefile b/i2c/build/Makefile
index 1859da3..441b67a 100644
--- a/i2c/build/Makefile
+++ b/i2c/build/Makefile
@@ -1,70 +1,44 @@
-project = novena_i2c
-vendor = xilinx
-family = spartan6
-part = xc6slx45csg324-3
-top_module = novena_top
-isedir = /opt/Xilinx/14.7/ISE_DS
-xil_env = . $(isedir)/settings64.sh
-ucf = ../ucf/novena_i2c.ucf
+# Localize all the relative path awfulness in one variable.
+
+CORE_TREE := $(abspath ../../../..)
+
+# Figure out what the native word size is on the build host, because
+# the XiLinx tools care for some reason.
+
+WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0)) * 8')
+
+# Parameters to xilinx.mk.
+
+project = novena_eim
+vendor = xilinx
+family = spartan6
+part = xc6slx45csg324-3
+top_module = novena_top
+isedir = /opt/Xilinx/14.7/ISE_DS
+xil_env = . $(isedir)/settings$(WORD_SIZE).sh
+ucf = ../ucf/$(project).ucf
+
+# Verilog files that always go with builds on this platform.
vfiles = \
- ../rtl/novena_i2c.v \
- ../../common/rtl/novena_regs.v \
- ../../common/rtl/novena_clkmgr.v \
- ../../common/rtl/ipcore/clkmgr_dcm.v \
- ../../../common/core_selector/src/rtl/core_selector.v \
- ../../../common/core_selector/src/rtl/global_selector.v \
- ../../../common/core_selector/src/rtl/hash_selector.v \
- ../../../common/core_selector/src/rtl/rng_selector.v \
- ../../../common/core_selector/src/rtl/cipher_selector.v \
- ../../../common/core_selector/src/rtl/math_selector.v \
- ../../../../comm/i2c/src/rtl/i2c_regs.v \
- ../../../../comm/i2c/src/rtl/i2c_core.v \
- ../../../../comm/coretest/src/rtl/coretest.v \
- ../../../../hash/sha1/src/rtl/sha1.v \
- ../../../../hash/sha1/src/rtl/sha1_core.v \
- ../../../../hash/sha1/src/rtl/sha1_w_mem.v \
- ../../../../hash/sha256/src/rtl/sha256.v \
- ../../../../hash/sha256/src/rtl/sha256_core.v \
- ../../../../hash/sha256/src/rtl/sha256_k_constants.v \
- ../../../../hash/sha256/src/rtl/sha256_w_mem.v \
- ../../../../hash/sha512/src/rtl/sha512.v \
- ../../../../hash/sha512/src/rtl/sha512_core.v \
- ../../../../hash/sha512/src/rtl/sha512_h_constants.v \
- ../../../../hash/sha512/src/rtl/sha512_k_constants.v \
- ../../../../hash/sha512/src/rtl/sha512_w_mem.v \
- ../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy.v \
- ../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v \
- ../../../../rng/rosc_entropy/src/rtl/rosc.v \
- ../../../../rng/rosc_entropy/src/rtl/rosc_entropy.v \
- ../../../../rng/rosc_entropy/src/rtl/rosc_entropy_core.v \
- ../../../../rng/trng/src/rtl/trng.v \
- ../../../../rng/trng/src/rtl/trng_csprng.v \
- ../../../../rng/trng/src/rtl/trng_csprng_fifo.v \
- ../../../../rng/trng/src/rtl/trng_mixer.v \
- ../../../../cipher/aes/src/rtl/aes.v \
- ../../../../cipher/aes/src/rtl/aes_core.v \
- ../../../../cipher/aes/src/rtl/aes_decipher_block.v \
- ../../../../cipher/aes/src/rtl/aes_encipher_block.v \
- ../../../../cipher/aes/src/rtl/aes_inv_sbox.v \
- ../../../../cipher/aes/src/rtl/aes_key_mem.v \
- ../../../../cipher/aes/src/rtl/aes_sbox.v \
- ../../../../cipher/chacha/src/rtl/chacha.v \
- ../../../../cipher/chacha/src/rtl/chacha_core.v \
- ../../../../cipher/chacha/src/rtl/chacha_qr.v \
- ../../../../math/modexp/src/rtl/adder32.v \
- ../../../../math/modexp/src/rtl/blockmem1r1w.v \
- ../../../../math/modexp/src/rtl/blockmem2r1wptr.v \
- ../../../../math/modexp/src/rtl/blockmem2r1w.v \
- ../../../../math/modexp/src/rtl/blockmem2rptr1w.v \
- ../../../../math/modexp/src/rtl/modexp.v \
- ../../../../math/modexp/src/rtl/modexp_core.v \
- ../../../../math/modexp/src/rtl/montprod.v \
- ../../../../math/modexp/src/rtl/residue.v \
- ../../../../math/modexp/src/rtl/shl32.v \
- ../../../../math/modexp/src/rtl/shr32.v
+ $(CORE_TREE)/platform/novena/i2c/rtl/novena_i2c.v \
+ $(CORE_TREE)/platform/novena/common/rtl/novena_regs.v \
+ $(CORE_TREE)/platform/novena/common/rtl/novena_clkmgr.v \
+ $(CORE_TREE)/platform/novena/common/rtl/clkmgr_dcm.v \
+ $(CORE_TREE)/platform/novena/config/core_selector.v \
+ $(CORE_TREE)/comm/i2c/src/rtl/i2c_regs.v \
+ $(CORE_TREE)/comm/i2c/src/rtl/i2c_core.v \
+ $(CORE_TREE)/comm/coretest/src/rtl/coretest.v
+
+# Verilog files selected by the core configuration script.
+
+-include $(CORE_TREE)/platform/novena/config/core_vfiles.mk
include xilinx.mk
+# Fun extras for running verlator as a linter.
+
+VERILATOR_FLAGS = --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME
+
lint:
- verilator --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME $(vfiles) ../../common/rtl/lint-dummy.v
+ verilator ${VERILATOR_FLAGS} $(vfiles) $(CORE_TREE)/platform/novena/common/rtl/lint-dummy.v
diff --git a/i2c/build/xilinx.mk b/i2c/build/xilinx.mk
index f35cc98..cace9c1 100644
--- a/i2c/build/xilinx.mk
+++ b/i2c/build/xilinx.mk
@@ -1,6 +1,6 @@
# The top level module should define the variables below then include
# this file. The files listed should be in the same directory as the
-# Makefile.
+# Makefile.
#
# variable description
# ---------- -------------
@@ -11,7 +11,7 @@
# vfiles all local .v files
# xilinx_cores all local .xco files
# vendor vendor of FPGA (xilinx, altera, etc.)
-# family FPGA device family (spartan3e)
+# family FPGA device family (spartan3e)
# part FPGA part name (xc4vfx12-10-sf363)
# flashsize size of flash for mcs file (16384)
# optfile (optional) xst extra opttions file to put in .scr
@@ -38,7 +38,7 @@ xil_env ?= . $(isedir)/settings32.sh
flashsize ?= 8192
ucf ?= $(project).ucf
-libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs))
+libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs))
mkfiles = $(libmks) xilinx.mk
include $(libmks)
@@ -108,9 +108,9 @@ $(project)_par.ncd: $(project).ncd
:; \
else \
$(MAKE) etwr; \
- fi
-junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad
-junk += $(project)_par_pad.csv $(project)_par_pad.txt
+ fi
+junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad
+junk += $(project)_par_pad.csv $(project)_par_pad.txt
junk += $(project)_par.grf $(project)_par.ptwx
junk += $(project)_par.unroutes $(project)_par.xpi
@@ -124,7 +124,7 @@ $(project).ncd: $(project).ngd
$(xil_env); \
map $(intstyle) $(map_opts) $$smartguide $<
junk += $(project).ncd $(project).pcf $(project).ngm $(project).mrp $(project).map
-junk += smartguide.ncd $(project).psr
+junk += smartguide.ncd $(project).psr
junk += $(project)_summary.xml $(project)_usage.xml
$(project).ngd: $(project).ngc $(ucf)
@@ -133,7 +133,7 @@ junk += $(project).ngd $(project).bld
$(project).ngc: $(vfiles) $(local_corengcs) $(project).scr $(project).prj
$(xil_env); xst $(intstyle) -ifn $(project).scr
-junk += xlnx_auto* $(top_module).lso $(project).srp
+junk += xlnx_auto* $(top_module).lso $(project).srp
junk += netlist.lst xst $(project).ngc
$(project).prj: $(vfiles) $(mkfiles)
diff --git a/i2c/rtl/novena_i2c.v b/i2c/rtl/novena_i2c.v
index 4ea6f82..db2c203 100644
--- a/i2c/rtl/novena_i2c.v
+++ b/i2c/rtl/novena_i2c.v
@@ -53,7 +53,7 @@ module novena_top
// I2C interface
input wire i2c_scl,
inout wire i2c_sda,
-
+
// Novena utility ports
output wire apoptosis_pin, // Hold low to not restart after config.
output wire led_pin // LED on edge close to the FPGA.
@@ -99,7 +99,7 @@ module novena_top
wire sda_pd;
wire sda_int;
-
+
wire clk = sys_clk;
// Coretest connections.
@@ -143,7 +143,7 @@ module novena_top
.rxd_syn(i2c_rxd_syn),
.rxd_data(i2c_rxd_data),
.rxd_ack(i2c_rxd_ack),
-
+
// Internal transmit interface.
.txd_syn(i2c_txd_syn),
.txd_data(i2c_txd_data),
@@ -154,15 +154,15 @@ module novena_top
(
.clk(clk),
.reset_n(sys_rst_n),
-
+
.rx_syn(i2c_rxd_syn),
.rx_data(i2c_rxd_data),
.rx_ack(i2c_rxd_ack),
-
+
.tx_syn(i2c_txd_syn),
.tx_data(i2c_txd_data),
.tx_ack(i2c_txd_ack),
-
+
// Interface to the core being tested.
.core_reset_n(coretest_reset_n),
.core_cs(coretest_cs),
@@ -199,7 +199,7 @@ module novena_top
.noise(ct_noise),
.debug(ct_led)
- );
+ );
//----------------------------------------------------------------
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-18 07:14:07 +0000