diff options
Diffstat (limited to 'i2c/build/Makefile')
| -rw-r--r-- | i2c/build/Makefile | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/i2c/build/Makefile b/i2c/build/Makefile index dc020c8..a890242 100644 --- a/i2c/build/Makefile +++ b/i2c/build/Makefile @@ -23,25 +23,26 @@ all: $(project).bit # Build the default core_selector if it doesn't already exist. CONFIG = $(CORE_TREE)/platform/common/config +CONFIG_GEN = $(CONFIG)/core_config.py -c $(CONFIG)/core.cfg -b novena core_selector.v core_vfiles.mk: - $(CONFIG)/config.py -c $(CONFIG)/config.cfg + $(CONFIG_GEN) -p rsa # Build some different configurations bare: - $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s bare + $(CONFIG_GEN) -p bare $(MAKE) project=$(project)_bare ucf=$(ucf) trng: - $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s trng + $(CONFIG_GEN) -p trng $(MAKE) project=$(project)_trng ucf=$(ucf) hash: - $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s hash + $(CONFIG_GEN) -p hash $(MAKE) project=$(project)_hash ucf=$(ucf) rsa: - $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s rsa + $(CONFIG_GEN) -p rsa $(MAKE) project=$(project)_rsa ucf=$(ucf) # Verilog files that always go with builds on this platform. |