diff options
Diffstat (limited to 'eim/iseconfig/novena_eim.xise')
| -rw-r--r-- | eim/iseconfig/novena_eim.xise | 177 |
1 files changed, 88 insertions, 89 deletions
diff --git a/eim/iseconfig/novena_eim.xise b/eim/iseconfig/novena_eim.xise index b7708eb..e89c042 100644 --- a/eim/iseconfig/novena_eim.xise +++ b/eim/iseconfig/novena_eim.xise @@ -17,87 +17,71 @@ <files> <file xil_pn:name="../rtl/novena_eim.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> - <association xil_pn:name="Implementation" xil_pn:seqID="56"/> + <association xil_pn:name="Implementation" xil_pn:seqID="54"/> </file> <file xil_pn:name="../../common/rtl/novena_regs.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> - <association xil_pn:name="Implementation" xil_pn:seqID="35"/> + <association xil_pn:name="Implementation" xil_pn:seqID="36"/> </file> <file xil_pn:name="../../common/rtl/novena_clkmgr.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> - <association xil_pn:name="Implementation" xil_pn:seqID="53"/> - </file> - <file xil_pn:name="../../common/rtl/ipcore/clkmgr_dcm.xco" xil_pn:type="FILE_COREGEN"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> - <association xil_pn:name="Implementation" xil_pn:seqID="45"/> + <association xil_pn:name="Implementation" xil_pn:seqID="51"/> </file> <file xil_pn:name="../../../common/core_selector/src/rtl/core_selector.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> - <association xil_pn:name="Implementation" xil_pn:seqID="54"/> + <association xil_pn:name="Implementation" xil_pn:seqID="52"/> </file> <file xil_pn:name="../../../common/core_selector/src/rtl/global_selector.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> - <association xil_pn:name="Implementation" xil_pn:seqID="49"/> + <association xil_pn:name="Implementation" xil_pn:seqID="47"/> </file> <file xil_pn:name="../../../common/core_selector/src/rtl/cipher_selector.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> - <association xil_pn:name="Implementation" xil_pn:seqID="50"/> + <association xil_pn:name="Implementation" xil_pn:seqID="48"/> </file> <file xil_pn:name="../../../common/core_selector/src/rtl/hash_selector.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/> - <association xil_pn:name="Implementation" xil_pn:seqID="48"/> + <association xil_pn:name="Implementation" xil_pn:seqID="46"/> </file> <file xil_pn:name="../../../common/core_selector/src/rtl/rng_selector.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/> - <association xil_pn:name="Implementation" xil_pn:seqID="46"/> + <association xil_pn:name="Implementation" xil_pn:seqID="44"/> </file> <file xil_pn:name="../../../../comm/eim/src/rtl/cdc_bus_pulse.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/> - <association xil_pn:name="Implementation" xil_pn:seqID="32"/> + <association xil_pn:name="Implementation" xil_pn:seqID="33"/> </file> <file xil_pn:name="../../../../comm/eim/src/rtl/eim_arbiter_cdc.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/> - <association xil_pn:name="Implementation" xil_pn:seqID="42"/> + <association xil_pn:name="Implementation" xil_pn:seqID="41"/> </file> <file xil_pn:name="../../../../comm/eim/src/rtl/eim_arbiter.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/> - <association xil_pn:name="Implementation" xil_pn:seqID="52"/> + <association xil_pn:name="Implementation" xil_pn:seqID="50"/> </file> <file xil_pn:name="../../../../comm/eim/src/rtl/eim_da_phy.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/> - <association xil_pn:name="Implementation" xil_pn:seqID="41"/> + <association xil_pn:name="Implementation" xil_pn:seqID="40"/> </file> <file xil_pn:name="../../../../comm/eim/src/rtl/eim_indicator.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/> - <association xil_pn:name="Implementation" xil_pn:seqID="51"/> + <association xil_pn:name="Implementation" xil_pn:seqID="49"/> </file> <file xil_pn:name="../../../../comm/eim/src/rtl/eim.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/> - <association xil_pn:name="Implementation" xil_pn:seqID="55"/> - </file> - <file xil_pn:name="../../../../hash/sha1/src/rtl/sha1_core.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/> - <association xil_pn:name="Implementation" xil_pn:seqID="31"/> - </file> - <file xil_pn:name="../../../../hash/sha1/src/rtl/sha1_w_mem.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/> - <association xil_pn:name="Implementation" xil_pn:seqID="17"/> - </file> - <file xil_pn:name="../../../../hash/sha1/src/rtl/sha1.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/> - <association xil_pn:name="Implementation" xil_pn:seqID="39"/> + <association xil_pn:name="Implementation" xil_pn:seqID="53"/> </file> <file xil_pn:name="../../../../hash/sha256/src/rtl/sha256_core.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/> - <association xil_pn:name="Implementation" xil_pn:seqID="30"/> + <association xil_pn:name="Implementation" xil_pn:seqID="32"/> </file> <file xil_pn:name="../../../../hash/sha256/src/rtl/sha256_k_constants.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/> - <association xil_pn:name="Implementation" xil_pn:seqID="16"/> + <association xil_pn:name="Implementation" xil_pn:seqID="21"/> </file> <file xil_pn:name="../../../../hash/sha256/src/rtl/sha256_w_mem.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/> - <association xil_pn:name="Implementation" xil_pn:seqID="15"/> + <association xil_pn:name="Implementation" xil_pn:seqID="20"/> </file> <file xil_pn:name="../../../../hash/sha256/src/rtl/sha256.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/> @@ -105,146 +89,160 @@ </file> <file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_core.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/> - <association xil_pn:name="Implementation" xil_pn:seqID="14"/> + <association xil_pn:name="Implementation" xil_pn:seqID="19"/> </file> <file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_h_constants.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/> - <association xil_pn:name="Implementation" xil_pn:seqID="4"/> + <association xil_pn:name="Implementation" xil_pn:seqID="8"/> </file> <file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_k_constants.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/> - <association xil_pn:name="Implementation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="7"/> </file> <file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_w_mem.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/> - <association xil_pn:name="Implementation" xil_pn:seqID="2"/> - </file> - <file xil_pn:name="../../../../hash/sha512/src/rtl/sha512.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/> - <association xil_pn:name="Implementation" xil_pn:seqID="37"/> + <association xil_pn:name="Implementation" xil_pn:seqID="6"/> </file> <file xil_pn:name="../ucf/novena_eim.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> <file xil_pn:name="../../../../comm/eim/src/rtl/eim_regs.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/> - <association xil_pn:name="Implementation" xil_pn:seqID="40"/> + <association xil_pn:name="Implementation" xil_pn:seqID="39"/> </file> <file xil_pn:name="../../../../rng/trng/src/rtl/trng.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/> - <association xil_pn:name="Implementation" xil_pn:seqID="34"/> + <association xil_pn:name="Implementation" xil_pn:seqID="35"/> </file> <file xil_pn:name="../../../../rng/trng/src/rtl/trng_mixer.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/> - <association xil_pn:name="Implementation" xil_pn:seqID="23"/> + <association xil_pn:name="Implementation" xil_pn:seqID="27"/> </file> <file xil_pn:name="../../../../rng/trng/src/rtl/trng_csprng.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/> - <association xil_pn:name="Implementation" xil_pn:seqID="24"/> + <association xil_pn:name="Implementation" xil_pn:seqID="28"/> </file> <file xil_pn:name="../../../../rng/trng/src/rtl/trng_csprng_fifo.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/> - <association xil_pn:name="Implementation" xil_pn:seqID="7"/> + <association xil_pn:name="Implementation" xil_pn:seqID="11"/> </file> <file xil_pn:name="../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/> - <association xil_pn:name="Implementation" xil_pn:seqID="26"/> + <association xil_pn:name="Implementation" xil_pn:seqID="30"/> </file> <file xil_pn:name="../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/> - <association xil_pn:name="Implementation" xil_pn:seqID="9"/> + <association xil_pn:name="Implementation" xil_pn:seqID="13"/> </file> <file xil_pn:name="../../../../rng/rosc_entropy/src/rtl/rosc_entropy_core.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/> - <association xil_pn:name="Implementation" xil_pn:seqID="8"/> + <association xil_pn:name="Implementation" xil_pn:seqID="12"/> </file> <file xil_pn:name="../../../../rng/rosc_entropy/src/rtl/rosc_entropy.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/> - <association xil_pn:name="Implementation" xil_pn:seqID="25"/> + <association xil_pn:name="Implementation" xil_pn:seqID="29"/> </file> <file xil_pn:name="../../../../rng/rosc_entropy/src/rtl/rosc.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/> - <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + <association xil_pn:name="Implementation" xil_pn:seqID="2"/> </file> <file xil_pn:name="../../../../cipher/chacha/src/rtl/chacha_core.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/> - <association xil_pn:name="Implementation" xil_pn:seqID="18"/> + <association xil_pn:name="Implementation" xil_pn:seqID="22"/> </file> <file xil_pn:name="../../../../cipher/chacha/src/rtl/chacha_qr.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/> - <association xil_pn:name="Implementation" xil_pn:seqID="5"/> + <association xil_pn:name="Implementation" xil_pn:seqID="9"/> </file> <file xil_pn:name="../../../common/core_selector/src/rtl/math_selector.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/> - <association xil_pn:name="Implementation" xil_pn:seqID="47"/> + <association xil_pn:name="Implementation" xil_pn:seqID="45"/> </file> <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_core.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/> - <association xil_pn:name="Implementation" xil_pn:seqID="33"/> + <association xil_pn:name="Implementation" xil_pn:seqID="34"/> </file> <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_decipher_block.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/> - <association xil_pn:name="Implementation" xil_pn:seqID="22"/> + <association xil_pn:name="Implementation" xil_pn:seqID="26"/> </file> <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_encipher_block.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/> - <association xil_pn:name="Implementation" xil_pn:seqID="21"/> + <association xil_pn:name="Implementation" xil_pn:seqID="25"/> </file> <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_inv_sbox.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="100"/> - <association xil_pn:name="Implementation" xil_pn:seqID="6"/> + <association xil_pn:name="Implementation" xil_pn:seqID="10"/> </file> <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_key_mem.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="101"/> - <association xil_pn:name="Implementation" xil_pn:seqID="20"/> + <association xil_pn:name="Implementation" xil_pn:seqID="24"/> </file> <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_sbox.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="102"/> - <association xil_pn:name="Implementation" xil_pn:seqID="19"/> + <association xil_pn:name="Implementation" xil_pn:seqID="23"/> </file> <file xil_pn:name="../../../../cipher/aes/src/rtl/aes.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="103"/> - <association xil_pn:name="Implementation" xil_pn:seqID="44"/> - </file> - <file xil_pn:name="../../../../cipher/chacha/src/rtl/chacha.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="104"/> - <association xil_pn:name="Implementation" xil_pn:seqID="43"/> - </file> - <file xil_pn:name="../../../../math/modexp/src/rtl/adder32.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="105"/> - <association xil_pn:name="Implementation" xil_pn:seqID="13"/> - </file> - <file xil_pn:name="../../../../math/modexp/src/rtl/blockmem1r1w.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/> - <association xil_pn:name="Implementation" xil_pn:seqID="12"/> - </file> - <file xil_pn:name="../../../../math/modexp/src/rtl/blockmem2r1w.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/> - <association xil_pn:name="Implementation" xil_pn:seqID="29"/> + <association xil_pn:name="Implementation" xil_pn:seqID="42"/> </file> - <file xil_pn:name="../../../../math/modexp/src/rtl/modexp.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../math/modexps6/src/rtl/modexps6_adder64_carry32.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="108"/> - <association xil_pn:name="Implementation" xil_pn:seqID="36"/> + <association xil_pn:name="Implementation" xil_pn:seqID="4"/> </file> - <file xil_pn:name="../../../../math/modexp/src/rtl/montprod.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../math/modexps6/src/rtl/modexps6_buffer_core.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="109"/> - <association xil_pn:name="Implementation" xil_pn:seqID="28"/> + <association xil_pn:name="Implementation" xil_pn:seqID="18"/> </file> - <file xil_pn:name="../../../../math/modexp/src/rtl/residue.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../math/modexps6/src/rtl/modexps6_buffer_user.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="110"/> - <association xil_pn:name="Implementation" xil_pn:seqID="27"/> + <association xil_pn:name="Implementation" xil_pn:seqID="17"/> </file> - <file xil_pn:name="../../../../math/modexp/src/rtl/shl32.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../math/modexps6/src/rtl/modexps6_modinv32.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="111"/> - <association xil_pn:name="Implementation" xil_pn:seqID="11"/> + <association xil_pn:name="Implementation" xil_pn:seqID="16"/> </file> - <file xil_pn:name="../../../../math/modexp/src/rtl/shr32.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../math/modexps6/src/rtl/modexps6_montgomery_coeff.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="112"/> - <association xil_pn:name="Implementation" xil_pn:seqID="10"/> + <association xil_pn:name="Implementation" xil_pn:seqID="15"/> </file> - <file xil_pn:name="../../common/rtl/ipcore/clkmgr_dcm.xise" xil_pn:type="FILE_COREGENISE"> + <file xil_pn:name="../../../../math/modexps6/src/rtl/modexps6_montgomery_multiplier.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="113"/> + <association xil_pn:name="Implementation" xil_pn:seqID="14"/> + </file> + <file xil_pn:name="../../../../math/modexps6/src/rtl/modexps6_top.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="114"/> + <association xil_pn:name="Implementation" xil_pn:seqID="31"/> + </file> + <file xil_pn:name="../../../../math/modexps6/src/rtl/modexps6_wrapper.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/> + <association xil_pn:name="Implementation" xil_pn:seqID="37"/> + </file> + <file xil_pn:name="../../../../math/modexps6/src/rtl/ram_1rw_1ro_readfirst.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/> + <association xil_pn:name="Implementation" xil_pn:seqID="3"/> + </file> + <file xil_pn:name="../../../../math/modexps6/src/rtl/ipcore/multiplier_s6.xco" xil_pn:type="FILE_COREGEN"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="111"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="../../../../math/modexps6/src/rtl/ipcore/subtractor_s6.xco" xil_pn:type="FILE_COREGEN"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="118"/> + <association xil_pn:name="Implementation" xil_pn:seqID="5"/> + </file> + <file xil_pn:name="../../common/rtl/ipcore/clkmgr_dcm.xco" xil_pn:type="FILE_COREGEN"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/> + <association xil_pn:name="Implementation" xil_pn:seqID="125"/> + </file> + <file xil_pn:name="../../../../math/modexps6/src/rtl/ipcore/multiplier_s6.xise" xil_pn:type="FILE_COREGENISE"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> + <file xil_pn:name="../../../../math/modexps6/src/rtl/ipcore/subtractor_s6.xise" xil_pn:type="FILE_COREGENISE"> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + </file> + <file xil_pn:name="../../common/rtl/ipcore/clkmgr_dcm.xise" xil_pn:type="FILE_COREGENISE"> + <association xil_pn:name="Implementation" xil_pn:seqID="126"/> + </file> </files> <properties> @@ -272,7 +270,7 @@ <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/> <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> @@ -450,6 +448,7 @@ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/> <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |