diff options
Diffstat (limited to 'eim/build')
| -rw-r--r-- | eim/build/Makefile | 25 | ||||
| -rw-r--r-- | eim/build/xilinx.mk | 4 |
2 files changed, 17 insertions, 12 deletions
diff --git a/eim/build/Makefile b/eim/build/Makefile index d598126..badda45 100644 --- a/eim/build/Makefile +++ b/eim/build/Makefile @@ -51,16 +51,19 @@ vfiles = \ ../../../../cipher/chacha/src/rtl/chacha.v \ ../../../../cipher/chacha/src/rtl/chacha_core.v \ ../../../../cipher/chacha/src/rtl/chacha_qr.v \ - ../../../../math/modexp/src/rtl/adder32.v \ - ../../../../math/modexp/src/rtl/blockmem1r1w.v \ - ../../../../math/modexp/src/rtl/blockmem2r1wptr.v \ - ../../../../math/modexp/src/rtl/blockmem2r1w.v \ - ../../../../math/modexp/src/rtl/blockmem2rptr1w.v \ - ../../../../math/modexp/src/rtl/modexp.v \ - ../../../../math/modexp/src/rtl/modexp_core.v \ - ../../../../math/modexp/src/rtl/montprod.v \ - ../../../../math/modexp/src/rtl/residue.v \ - ../../../../math/modexp/src/rtl/shl32.v \ - ../../../../math/modexp/src/rtl/shr32.v + ../../../../math/modexps6/src/rtl/modexps6_adder64_carry32.v \ + ../../../../math/modexps6/src/rtl/modexps6_buffer_core.v \ + ../../../../math/modexps6/src/rtl/modexps6_buffer_user.v \ + ../../../../math/modexps6/src/rtl/modexps6_modinv32.v \ + ../../../../math/modexps6/src/rtl/modexps6_montgomery_coeff.v \ + ../../../../math/modexps6/src/rtl/modexps6_montgomery_multiplier.v \ + ../../../../math/modexps6/src/rtl/modexps6_top.v \ + ../../../../math/modexps6/src/rtl/modexps6_wrapper.v \ + ../../../../math/modexps6/src/rtl/ram_1rw_1ro_readfirst.v \ + ../../../../math/modexps6/src/rtl/ipcore/multiplier_s6.v \ + ../../../../math/modexps6/src/rtl/ipcore/subtractor_s6.v include xilinx.mk + +lint: + verilator --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME $(vfiles) ../../common/rtl/lint-dummy.v diff --git a/eim/build/xilinx.mk b/eim/build/xilinx.mk index 8065e45..8a81ef9 100644 --- a/eim/build/xilinx.mk +++ b/eim/build/xilinx.mk @@ -31,7 +31,9 @@ # TODO: .xco files are device dependant, should use a template based system coregen_work_dir ?= ./coregen-tmp -map_opts ?= -timing -ol high -detail -pr b -register_duplication -w -xe n +#map_opts ?= -timing -ol high -detail -pr b -register_duplication -w -xe n +# from https://github.com/fpga-logi/logi-hard/blob/master/build_lib/synth/xilinx.mk: +map_opts ?= -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off par_opts ?= -ol high isedir ?= /opt/Xilinx/13.3/ISE_DS xil_env ?= . $(isedir)/settings32.sh |