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-rw-r--r--config/config.cfg5
-rwxr-xr-xconfig/config.py30
-rw-r--r--config/core_selector.v51
-rw-r--r--config/core_vfiles.mk22
4 files changed, 43 insertions, 65 deletions
diff --git a/config/config.cfg b/config/config.cfg
index 7e4571c..f42813e 100644
--- a/config/config.cfg
+++ b/config/config.cfg
@@ -17,8 +17,6 @@
# file, and has no effect at all if an instance of a core named here
# is already included in the build.
#
-# reset_high: boolean indicating whether the core uses active reset.
-#
# error_wire: boolean indicating whether the core wants a error wire.
#
# block_memory: boolean indicating whether the core uses block memory.
@@ -40,7 +38,7 @@ cores = trng
cores = modexp
[rsa]
-cores = sha256 aes trng modexp
+cores = sha256 aes trng modexps6
[multi-test]
cores = sha256 aes aes chacha aes
@@ -97,7 +95,6 @@ vfiles =
[modexps6]
block_memory = yes
-reset_high = yes
error_wire = no
vfiles =
math/modexps6/src/rtl/modexps6_adder64_carry32.v
diff --git a/config/config.py b/config/config.py
index 0f3818f..de28e7b 100755
--- a/config/config.py
+++ b/config/config.py
@@ -36,19 +36,6 @@ Generate core_selector.v and core_vfiles.mk for a set of cores.
# two-level (no segment) scheme and handle modexps6 as a set of four
# contiguous "cores" with a 10-bit composite register selector.
-# At present, TRNG core's internal multiplexer doesn't allocate cores
-# contiguously, there's a gap, and one just has to know what the
-# offsets are. Current theory is that we'll fix the TRNG core to get
-# rid of this problem, but for now the workaround requires this script
-# to know the magic offsets for the high 4 bits of the 12-bit TRNG
-# address:
-#
-# 0x0: trng
-# 0x5: entropy1 (avalanche)
-# 0x6: entropy2 (rosc)
-# 0xa: mixer
-# 0xb: csprng
-
# The modexps6 core drags in a one clock cycle delay to other cores,
# to compensate for the extra clock cycle consumed by the block
# memories used in the modexps6 core. We probably want a general
@@ -106,9 +93,6 @@ def main():
for core in cores:
core_number = core.assign_core_number(core_number)
- cores[0].reset_high = True
- cores[1].reset_high = True
-
for core in cores:
core.configure(cfg)
@@ -183,7 +167,6 @@ class Core(object):
self.name = name
self.core_number = None
self.vfiles = []
- self.reset_high = False
self.error_wire = True
self.block_memory = False
self.instance_number = self._instance_count.get(name, 0)
@@ -203,7 +186,6 @@ class Core(object):
for required in cfg.getvalues(self.name, "requires"):
if required not in self._instance_count:
self.vfiles.extend(cfg.getvalues(required, "vfiles"))
- self.reset_high = cfg.getboolean(self.name, "reset_high", self.reset_high)
self.error_wire = cfg.getboolean(self.name, "error_wire", self.error_wire)
self.block_memory = cfg.getboolean(self.name, "block_memory", self.block_memory)
@@ -220,7 +202,7 @@ class Core(object):
@property
def reset_pin(self):
- return ".rst(sys_rst)" if self.reset_high else ".reset_n(~sys_rst)"
+ return ".reset_n(sys_rst_n)"
@property
def error_port(self):
@@ -277,10 +259,10 @@ class TRNGCore(Core):
"""
# TRNG subcore name -> internal mux number.
- subcore_parameters = dict(avalanche_entropy = 0x5,
- rosc_entropy = 0x6,
- trng_mixer = 0xa,
- trng_csprng = 0xb)
+ subcore_parameters = dict(avalanche_entropy = 0x1,
+ rosc_entropy = 0x2,
+ trng_mixer = 0x3,
+ trng_csprng = 0x4)
def __init__(self, name):
super(TRNGCore, self).__init__(name)
@@ -472,7 +454,7 @@ createModule_template = """\
module core_selector
(
input wire sys_clk,
- input wire sys_rst,
+ input wire sys_rst_n,
input wire [16: 0] sys_eim_addr,
input wire sys_eim_wr,
diff --git a/config/core_selector.v b/config/core_selector.v
index 3c0a31f..298c39e 100644
--- a/config/core_selector.v
+++ b/config/core_selector.v
@@ -3,7 +3,7 @@
module core_selector
(
input wire sys_clk,
- input wire sys_rst,
+ input wire sys_rst_n,
input wire [16: 0] sys_eim_addr,
input wire sys_eim_wr,
@@ -34,11 +34,11 @@ module core_selector
localparam CORE_ADDR_SHA256 = 9'h02;
localparam CORE_ADDR_AES = 9'h03;
localparam CORE_ADDR_TRNG = 9'h04;
- localparam CORE_ADDR_AVALANCHE_ENTROPY = 9'h09;
- localparam CORE_ADDR_ROSC_ENTROPY = 9'h0a;
- localparam CORE_ADDR_TRNG_MIXER = 9'h0e;
- localparam CORE_ADDR_TRNG_CSPRNG = 9'h0f;
- localparam CORE_ADDR_MODEXP = 9'h14;
+ localparam CORE_ADDR_AVALANCHE_ENTROPY = 9'h05;
+ localparam CORE_ADDR_ROSC_ENTROPY = 9'h06;
+ localparam CORE_ADDR_TRNG_MIXER = 9'h07;
+ localparam CORE_ADDR_TRNG_CSPRNG = 9'h08;
+ localparam CORE_ADDR_MODEXPS6 = 9'h14;
//----------------------------------------------------------------
@@ -51,7 +51,7 @@ module core_selector
board_regs board_regs_inst
(
.clk(sys_clk),
- .rst(sys_rst),
+ .reset_n(sys_rst_n),
.cs(enable_board_regs & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
@@ -77,7 +77,7 @@ module core_selector
comm_regs comm_regs_inst
(
.clk(sys_clk),
- .rst(sys_rst),
+ .reset_n(sys_rst_n),
.cs(enable_comm_regs & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
@@ -103,7 +103,7 @@ module core_selector
sha256 sha256_inst
(
.clk(sys_clk),
- .reset_n(~sys_rst),
+ .reset_n(sys_rst_n),
.cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
@@ -129,7 +129,7 @@ module core_selector
aes aes_inst
(
.clk(sys_clk),
- .reset_n(~sys_rst),
+ .reset_n(sys_rst_n),
.cs(enable_aes & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
@@ -156,7 +156,7 @@ module core_selector
trng trng_inst
(
.clk(sys_clk),
- .reset_n(~sys_rst),
+ .reset_n(sys_rst_n),
.cs(enable_trng & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
@@ -176,29 +176,25 @@ module core_selector
//----------------------------------------------------------------
- // MODEXP
+ // MODEXPS6
//----------------------------------------------------------------
- wire enable_modexp = (addr_core_num == CORE_ADDR_MODEXP);
- wire [31: 0] read_data_modexp;
- wire error_modexp;
+ wire enable_modexps6 = (addr_core_num >= CORE_ADDR_MODEXPS6) && (addr_core_num <= CORE_ADDR_MODEXPS6 + 9'h03);
+ wire [31: 0] read_data_modexps6;
+ wire [1:0] modexps6_prefix = addr_core_num[1:0] - CORE_ADDR_MODEXPS6;
- modexp modexp_inst
+ modexps6_wrapper modexps6_inst
(
.clk(sys_clk),
- .reset_n(~sys_rst),
+ .reset_n(sys_rst_n),
- .cs(enable_modexp & (sys_eim_rd | sys_eim_wr)),
+ .cs(enable_modexps6 & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
- .address(addr_core_reg),
+ .address({modexps6_prefix, addr_core_reg}),
.write_data(sys_write_data),
- .read_data(read_data_modexp)
+ .read_data(read_data_modexps6)
);
- reg [31: 0] read_data_modexp_reg;
- always @(posedge sys_clk)
- read_data_modexp_reg <= read_data_modexp;
-
//----------------------------------------------------------------
@@ -257,9 +253,12 @@ module core_selector
sys_read_data_mux = read_data_trng_reg;
sys_error_mux = error_trng;
end
- CORE_ADDR_MODEXP:
+ CORE_ADDR_MODEXPS6 + 0,
+ CORE_ADDR_MODEXPS6 + 1,
+ CORE_ADDR_MODEXPS6 + 2,
+ CORE_ADDR_MODEXPS6 + 3:
begin
- sys_read_data_mux = read_data_modexp_reg;
+ sys_read_data_mux = read_data_modexps6;
sys_error_mux = 0;
end
diff --git a/config/core_vfiles.mk b/config/core_vfiles.mk
index 8def572..4020234 100644
--- a/config/core_vfiles.mk
+++ b/config/core_vfiles.mk
@@ -29,14 +29,14 @@ vfiles += \
$(CORE_TREE)/hash/sha512/src/rtl/sha512_h_constants.v \
$(CORE_TREE)/hash/sha512/src/rtl/sha512_k_constants.v \
$(CORE_TREE)/hash/sha512/src/rtl/sha512_w_mem.v \
- $(CORE_TREE)/math/modexp/src/rtl/adder.v \
- $(CORE_TREE)/math/modexp/src/rtl/blockmem1r1w.v \
- $(CORE_TREE)/math/modexp/src/rtl/blockmem2r1wptr.v \
- $(CORE_TREE)/math/modexp/src/rtl/blockmem2r1w.v \
- $(CORE_TREE)/math/modexp/src/rtl/blockmem2rptr1w.v \
- $(CORE_TREE)/math/modexp/src/rtl/modexp.v \
- $(CORE_TREE)/math/modexp/src/rtl/modexp_core.v \
- $(CORE_TREE)/math/modexp/src/rtl/montprod.v \
- $(CORE_TREE)/math/modexp/src/rtl/residue.v \
- $(CORE_TREE)/math/modexp/src/rtl/shl.v \
- $(CORE_TREE)/math/modexp/src/rtl/shr.v
+ $(CORE_TREE)/math/modexps6/src/rtl/modexps6_adder64_carry32.v \
+ $(CORE_TREE)/math/modexps6/src/rtl/modexps6_buffer_core.v \
+ $(CORE_TREE)/math/modexps6/src/rtl/modexps6_buffer_user.v \
+ $(CORE_TREE)/math/modexps6/src/rtl/modexps6_modinv32.v \
+ $(CORE_TREE)/math/modexps6/src/rtl/modexps6_montgomery_coeff.v \
+ $(CORE_TREE)/math/modexps6/src/rtl/modexps6_montgomery_multiplier.v \
+ $(CORE_TREE)/math/modexps6/src/rtl/modexps6_top.v \
+ $(CORE_TREE)/math/modexps6/src/rtl/modexps6_wrapper.v \
+ $(CORE_TREE)/math/modexps6/src/rtl/ram_1rw_1ro_readfirst.v \
+ $(CORE_TREE)/math/modexps6/src/rtl/ipcore/multiplier_s6.v \
+ $(CORE_TREE)/math/modexps6/src/rtl/ipcore/subtractor_s6.v
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 17:48:47 +0000