diff options
Diffstat (limited to 'config/config.py')
| -rwxr-xr-x | config/config.py | 38 |
1 files changed, 29 insertions, 9 deletions
diff --git a/config/config.py b/config/config.py index 74a9007..6a5e532 100755 --- a/config/config.py +++ b/config/config.py @@ -13,34 +13,41 @@ def main(): from sys import exit parser = ArgumentParser(description = __doc__, formatter_class = ArgumentDefaultsHelpFormatter) - parser.add_argument("-c", "--config", help = "config file", default = "config.cfg", type = FileType("r")) parser.add_argument("-d", "--debug", help = "enable debugging", action = "store_true") - parser.add_argument("-o", "--outfile", help = "output file", default = "core_selector.v", type = FileType("w")) parser.add_argument("-s", "--section", help = "config file section") + parser.add_argument("-c", "--config", help = "configuration file", default = "config.cfg", type = FileType("r")) + parser.add_argument("--verilog", help = "verilog output file", default = "core_selector.v", type = FileType("w")) + parser.add_argument("--makefile", help = "output makefile", default = "core_vfiles.mk", type = FileType("w")) parser.add_argument("core", help = "name(s) of core(s)", nargs = "*") args = parser.parse_args() try: + cfg = RawConfigParser() + cfg.readfp(args.config) + if args.core: cores = args.core else: - cfg = RawConfigParser() - cfg.readfp(args.config) - section = args.section or cfg.get("default", "default") + section = args.section or cfg.get("default", "default-section") cores = cfg.get(section, "cores").split() cores.insert(0, "board_regs") cores.insert(1, "comm_regs") - cores = [Core.new(core) for core in cores] + cores = tuple(Core.new(core) for core in cores) core_number = 0 for core in cores: core_number = core.assign_core_number(core_number) + for core in cores[2:]: + core.add_vfiles(cfg) - args.outfile.write(createModule_template.format( - addrs = "".join(core.createAddr() for core in cores), + args.verilog.write(createModule_template.format( + addrs = "".join(core.createAddr() for core in cores), insts = "".join(core.createInstance() for core in cores), - muxes = "".join(core.createMux() for core in cores))) + muxes = "".join(core.createMux() for core in cores))) + + args.makefile.write(listVfiles_template.format( + vfiles = "".join(core.listVfiles() for core in cores))) except Exception, e: if args.debug: @@ -67,6 +74,7 @@ class Core(object): def __init__(self, name): self.name = name self.core_number = None + self.vfiles = () self.instance_number = self._instance_count.get(name, 0) self._instance_count[name] = self.instance_number + 1 @@ -78,6 +86,10 @@ class Core(object): self.core_number = n return n + 1 + def add_vfiles(self, cfg): + if self.instance_number == 0: + self.vfiles = cfg.get(self.name, "vfiles").split() + @property def instance_name(self): if self._instance_count[self.name] > 1: @@ -98,6 +110,8 @@ class Core(object): def createMux(self): return createMux_template.format(core = self, core0 = self) + def listVfiles(self): + return "".join(" \\\n\t$(core_tree)/" + vfile for vfile in self.vfiles) class SubCore(Core): """" @@ -290,6 +304,12 @@ endmodule //====================================================================== """ +# Template for makefile snippet listing Verilog source files. + +listVfiles_template = """\ +vfiles +={vfiles} +""" + # Run main program. if __name__ == "__main__": |