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-rwxr-xr-xconfig/config.py11
1 files changed, 9 insertions, 2 deletions
diff --git a/config/config.py b/config/config.py
index 1c5e5d0..0f3818f 100755
--- a/config/config.py
+++ b/config/config.py
@@ -112,7 +112,14 @@ def main():
for core in cores:
core.configure(cfg)
- Core.need_one_cycle_delay = any(core.block_memory for core in cores)
+ if False:
+
+ # For some reason, attempting to optimize out the delay
+ # code entirely results in a non-working bitstream. Don't
+ # know why, disabling the optimization works, so just do
+ # that for now.
+
+ Core.need_one_cycle_delay = any(core.block_memory for core in cores)
args.verilog.write(createModule_template.format(
addrs = "".join(core.createAddr() for core in cores),
@@ -170,7 +177,7 @@ class Core(object):
# Class variable recording whether we need a one-cycle delay to
# compensate for block memories.
- need_one_cycle_delay = False
+ need_one_cycle_delay = True
def __init__(self, name):
self.name = name