aboutsummaryrefslogtreecommitdiff
path: root/config/config.cfg
diff options
context:
space:
mode:
Diffstat (limited to 'config/config.cfg')
-rw-r--r--config/config.cfg17
1 files changed, 15 insertions, 2 deletions
diff --git a/config/config.cfg b/config/config.cfg
index a4120b1..7e4571c 100644
--- a/config/config.cfg
+++ b/config/config.cfg
@@ -1,6 +1,6 @@
# Config file for the Cryptech Novena FPGA framework.
#
-# At present, there are four kinds of variables in this file:
+# Variables used in this file:
#
# default-section: Name of the configuration to build if the user
# doesn't specify one. Only meaningful in the default section.
@@ -16,6 +16,16 @@
# this core. This has no effect on the generated core_selector.v
# file, and has no effect at all if an instance of a core named here
# is already included in the build.
+#
+# reset_high: boolean indicating whether the core uses active reset.
+#
+# error_wire: boolean indicating whether the core wants a error wire.
+#
+# block_memory: boolean indicating whether the core uses block memory.
+# Effect of this is a bit strange: setting it triggers generation of
+# a one-cycle timing delay for every core in this build that does
+# *not* use block memory. When no cores in the build use block
+# memory, the delay isn't necessary and is therefore omitted.
[default]
default-section = rsa
@@ -86,7 +96,9 @@ vfiles =
cipher/chacha/src/rtl/chacha_qr.v
[modexps6]
-reset_high = true
+block_memory = yes
+reset_high = yes
+error_wire = no
vfiles =
math/modexps6/src/rtl/modexps6_adder64_carry32.v
math/modexps6/src/rtl/modexps6_buffer_core.v
@@ -101,6 +113,7 @@ vfiles =
math/modexps6/src/rtl/ipcore/subtractor_s6.v
[modexp]
+error_wire = no
vfiles =
math/modexp/src/rtl/adder.v
math/modexp/src/rtl/blockmem1r1w.v