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-rw-r--r--config/config.cfg125
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diff --git a/config/config.cfg b/config/config.cfg
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-# Config file for the Cryptech Novena FPGA framework.
-#
-# Variables used in this file:
-#
-# default-section: Name of the configuration to build if the user
-# doesn't specify one. Only meaningful in the default section.
-#
-# cores: A list of cores to build. Use with the --section option.
-#
-# vfiles: A list of Verilog files to include in the vfiles list when
-# including a particular core. All (optional) cores must have a
-# vfiles option, so that the configuration program knows what to put
-# into core_vfiles.mk.
-#
-# requires: A list of other cores whose vfiles must be loaded to build
-# this core. This has no effect on the generated core_selector.v
-# file, and has no effect at all if an instance of a core named here
-# is already included in the build.
-#
-# error_wire: boolean indicating whether the core wants a error wire.
-#
-# block_memory: boolean indicating whether the core uses block memory.
-# Effect of this is a bit strange: setting it triggers generation of
-# a one-cycle timing delay for every core in this build that does
-# *not* use block memory. When no cores in the build use block
-# memory, the delay isn't necessary and is therefore omitted.
-
-[default]
-default-section = rsa
-
-[hash-only]
-cores = sha1 sha256 sha512
-
-[trng-only]
-cores = trng
-
-[modexp-only]
-cores = modexp
-
-[rsa]
-cores = sha256 aes trng modexps6
-
-[multi-test]
-cores = sha256 aes aes chacha aes
-
-[sha1]
-vfiles =
- hash/sha1/src/rtl/sha1.v
- hash/sha1/src/rtl/sha1_core.v
- hash/sha1/src/rtl/sha1_w_mem.v
-
-[sha256]
-vfiles =
- hash/sha256/src/rtl/sha256.v
- hash/sha256/src/rtl/sha256_core.v
- hash/sha256/src/rtl/sha256_k_constants.v
- hash/sha256/src/rtl/sha256_w_mem.v
-
-[sha512]
-vfiles =
- hash/sha512/src/rtl/sha512.v
- hash/sha512/src/rtl/sha512_core.v
- hash/sha512/src/rtl/sha512_h_constants.v
- hash/sha512/src/rtl/sha512_k_constants.v
- hash/sha512/src/rtl/sha512_w_mem.v
-
-[trng]
-requires = chacha sha512
-vfiles =
- rng/avalanche_entropy/src/rtl/avalanche_entropy.v
- rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v
- rng/rosc_entropy/src/rtl/rosc.v
- rng/rosc_entropy/src/rtl/rosc_entropy.v
- rng/rosc_entropy/src/rtl/rosc_entropy_core.v
- rng/trng/src/rtl/trng.v
- rng/trng/src/rtl/trng_csprng.v
- rng/trng/src/rtl/trng_csprng_fifo.v
- rng/trng/src/rtl/trng_mixer.v
-
-[aes]
-vfiles =
- cipher/aes/src/rtl/aes.v
- cipher/aes/src/rtl/aes_core.v
- cipher/aes/src/rtl/aes_decipher_block.v
- cipher/aes/src/rtl/aes_encipher_block.v
- cipher/aes/src/rtl/aes_inv_sbox.v
- cipher/aes/src/rtl/aes_key_mem.v
- cipher/aes/src/rtl/aes_sbox.v
-
-[chacha]
-vfiles =
- cipher/chacha/src/rtl/chacha.v
- cipher/chacha/src/rtl/chacha_core.v
- cipher/chacha/src/rtl/chacha_qr.v
-
-[modexps6]
-block_memory = yes
-error_wire = no
-vfiles =
- math/modexps6/src/rtl/modexps6_adder64_carry32.v
- math/modexps6/src/rtl/modexps6_buffer_core.v
- math/modexps6/src/rtl/modexps6_buffer_user.v
- math/modexps6/src/rtl/modexps6_modinv32.v
- math/modexps6/src/rtl/modexps6_montgomery_coeff.v
- math/modexps6/src/rtl/modexps6_montgomery_multiplier.v
- math/modexps6/src/rtl/modexps6_top.v
- math/modexps6/src/rtl/modexps6_wrapper.v
- math/modexps6/src/rtl/ram_1rw_1ro_readfirst.v
- math/modexps6/src/rtl/ipcore/multiplier_s6.v
- math/modexps6/src/rtl/ipcore/subtractor_s6.v
-
-[modexp]
-error_wire = no
-vfiles =
- math/modexp/src/rtl/adder.v
- math/modexp/src/rtl/blockmem1r1w.v
- math/modexp/src/rtl/blockmem2r1wptr.v
- math/modexp/src/rtl/blockmem2r1w.v
- math/modexp/src/rtl/blockmem2rptr1w.v
- math/modexp/src/rtl/modexp.v
- math/modexp/src/rtl/modexp_core.v
- math/modexp/src/rtl/montprod.v
- math/modexp/src/rtl/residue.v
- math/modexp/src/rtl/shl.v
- math/modexp/src/rtl/shr.v