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-rw-r--r--common/rtl/ipcore/_xmsgs/cg.xmsgs27
-rw-r--r--common/rtl/ipcore/clkmgr_dcm.asy25
-rw-r--r--common/rtl/ipcore/clkmgr_dcm.gise31
-rw-r--r--common/rtl/ipcore/clkmgr_dcm.ncf60
-rw-r--r--common/rtl/ipcore/clkmgr_dcm.sym24
-rw-r--r--common/rtl/ipcore/clkmgr_dcm.ucf59
-rw-r--r--common/rtl/ipcore/clkmgr_dcm.v148
-rw-r--r--common/rtl/ipcore/clkmgr_dcm.veo79
-rw-r--r--common/rtl/ipcore/clkmgr_dcm.xco269
-rw-r--r--common/rtl/ipcore/clkmgr_dcm.xdc67
-rw-r--r--common/rtl/ipcore/clkmgr_dcm.xise74
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/clk_wiz_v3_6_readme.txt184
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_readme.txt184
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_vinfo.html195
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/doc/pg065_clk_wiz.pdfbin0 -> 42657 bytes
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf60
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v164
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc69
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/implement/implement.bat90
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/implement/implement.sh91
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.bat58
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.sh59
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.tcl78
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.bat58
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.sh57
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl69
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/implement/xst.prj2
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/implement/xst.scr9
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v145
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl8
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat59
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh61
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat61
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do65
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh61
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh62
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh72
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key5
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl18
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.do60
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.sv118
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v149
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file2
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl9
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh62
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat59
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do65
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh61
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh64
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh72
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key5
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl1
-rw-r--r--common/rtl/ipcore/clkmgr_dcm/simulation/timing/wave.do71
-rw-r--r--common/rtl/ipcore/clkmgr_dcm_flist.txt54
-rw-r--r--common/rtl/ipcore/clkmgr_dcm_xmdf.tcl140
-rw-r--r--common/rtl/ipcore/coregen.cgp9
-rw-r--r--common/rtl/ipcore/create_clkmgr_dcm.tcl37
-rw-r--r--common/rtl/ipcore/edit_clkmgr_dcm.tcl37
-rw-r--r--common/rtl/novena_clkmgr.v130
59 files changed, 4112 insertions, 0 deletions
diff --git a/common/rtl/ipcore/_xmsgs/cg.xmsgs b/common/rtl/ipcore/_xmsgs/cg.xmsgs
new file mode 100644
index 0000000..985e6e3
--- /dev/null
+++ b/common/rtl/ipcore/_xmsgs/cg.xmsgs
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="sim" num="172" delta="old" >Generating IP...
+</msg>
+
+<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;clkmgr_dcm&apos; already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+
+<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;clkmgr_dcm&apos; already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+
+<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Component clk_wiz_v3_6 does not have a valid model name for Verilog synthesis</arg>
+</msg>
+
+<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
+</msg>
+
+<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
+</msg>
+
+</messages>
+
diff --git a/common/rtl/ipcore/clkmgr_dcm.asy b/common/rtl/ipcore/clkmgr_dcm.asy
new file mode 100644
index 0000000..016d02a
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm.asy
@@ -0,0 +1,25 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 clkmgr_dcm
+RECTANGLE Normal 32 32 576 1088
+LINE Normal 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName clk_in1
+PINATTR Polarity IN
+LINE Normal 0 432 32 432
+PIN 0 432 LEFT 36
+PINATTR PinName reset
+PINATTR Polarity IN
+LINE Normal 608 80 576 80
+PIN 608 80 RIGHT 36
+PINATTR PinName clk_out1
+PINATTR Polarity OUT
+LINE Normal 608 880 576 880
+PIN 608 880 RIGHT 36
+PINATTR PinName input_clk_stopped
+PINATTR Polarity OUT
+LINE Normal 608 1008 576 1008
+PIN 608 1008 RIGHT 36
+PINATTR PinName clk_valid
+PINATTR Polarity OUT
+
diff --git a/common/rtl/ipcore/clkmgr_dcm.gise b/common/rtl/ipcore/clkmgr_dcm.gise
new file mode 100644
index 0000000..ed6d0f7
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm.gise
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="clkmgr_dcm.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="clkmgr_dcm.asy" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="clkmgr_dcm.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/common/rtl/ipcore/clkmgr_dcm.ncf b/common/rtl/ipcore/clkmgr_dcm.ncf
new file mode 100644
index 0000000..ef4e259
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm.ncf
@@ -0,0 +1,60 @@
+# file: clkmgr_dcm.ucf
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
+
+
+# FALSE PATH constraints
+PIN "RESET" TIG;
+
+
diff --git a/common/rtl/ipcore/clkmgr_dcm.sym b/common/rtl/ipcore/clkmgr_dcm.sym
new file mode 100644
index 0000000..7d178b8
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm.sym
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="clkmgr_dcm">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2015-1-28T21:56:19</timestamp>
+ <pin polarity="Input" x="0" y="80" name="clk_in1" />
+ <pin polarity="Input" x="0" y="432" name="reset" />
+ <pin polarity="Output" x="608" y="80" name="clk_out1" />
+ <pin polarity="Output" x="608" y="880" name="input_clk_stopped" />
+ <pin polarity="Output" x="608" y="1008" name="clk_valid" />
+ <graph>
+ <text style="fontsize:40;fontname:Arial" x="32" y="32">clkmgr_dcm</text>
+ <rect width="544" x="32" y="32" height="1056" />
+ <line x2="32" y1="80" y2="80" x1="0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin clk_in1" />
+ <line x2="32" y1="432" y2="432" x1="0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="432" type="pin reset" />
+ <line x2="576" y1="80" y2="80" x1="608" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="80" type="pin clk_out1" />
+ <line x2="576" y1="880" y2="880" x1="608" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="880" type="pin input_clk_stopped" />
+ <line x2="576" y1="1008" y2="1008" x1="608" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="1008" type="pin clk_valid" />
+ </graph>
+</symbol>
diff --git a/common/rtl/ipcore/clkmgr_dcm.ucf b/common/rtl/ipcore/clkmgr_dcm.ucf
new file mode 100644
index 0000000..658fdb4
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm.ucf
@@ -0,0 +1,59 @@
+# file: clkmgr_dcm.ucf
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
+
+
+# FALSE PATH constraints
+PIN "RESET" TIG;
+
diff --git a/common/rtl/ipcore/clkmgr_dcm.v b/common/rtl/ipcore/clkmgr_dcm.v
new file mode 100644
index 0000000..71477a8
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm.v
@@ -0,0 +1,148 @@
+// file: clkmgr_dcm.v
+//
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// "Output Output Phase Duty Pk-to-Pk Phase"
+// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
+//----------------------------------------------------------------------------
+// CLK_OUT1____50.000______0.000______50.0______200.000____150.000
+//
+//----------------------------------------------------------------------------
+// "Input Clock Freq (MHz) Input Jitter (UI)"
+//----------------------------------------------------------------------------
+// __primary______________50____________0.010
+
+`timescale 1ps/1ps
+
+(* CORE_GENERATION_INFO = "clkmgr_dcm,clk_wiz_v3_6,{component_name=clkmgr_dcm,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=true,use_status=false,use_freeze=false,use_clk_valid=true,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
+module clkmgr_dcm
+ (// Clock in ports
+ input CLK_IN1,
+ // Clock out ports
+ output CLK_OUT1,
+ // Status and control signals
+ input RESET,
+ output INPUT_CLK_STOPPED,
+ output CLK_VALID
+ );
+
+ // Input buffering
+ //------------------------------------
+ assign clkin1 = CLK_IN1;
+
+
+ // Clocking primitive
+ //------------------------------------
+
+ // Instantiation of the DCM primitive
+ // * Unused inputs are tied off
+ // * Unused outputs are labeled unused
+ wire psdone_unused;
+ wire locked_int;
+ wire [7:0] status_int;
+ wire clkfb;
+ wire clk0;
+
+ DCM_SP
+ #(.CLKDV_DIVIDE (2.000),
+ .CLKFX_DIVIDE (1),
+ .CLKFX_MULTIPLY (4),
+ .CLKIN_DIVIDE_BY_2 ("FALSE"),
+ .CLKIN_PERIOD (20.0),
+ .CLKOUT_PHASE_SHIFT ("NONE"),
+ .CLK_FEEDBACK ("1X"),
+ .DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
+ .PHASE_SHIFT (0),
+ .STARTUP_WAIT ("FALSE"))
+ dcm_sp_inst
+ // Input clock
+ (.CLKIN (clkin1),
+ .CLKFB (clkfb),
+ // Output clocks
+ .CLK0 (clk0),
+ .CLK90 (),
+ .CLK180 (),
+ .CLK270 (),
+ .CLK2X (),
+ .CLK2X180 (),
+ .CLKFX (),
+ .CLKFX180 (),
+ .CLKDV (),
+ // Ports for dynamic phase shift
+ .PSCLK (1'b0),
+ .PSEN (1'b0),
+ .PSINCDEC (1'b0),
+ .PSDONE (),
+ // Other control and status signals
+ .LOCKED (locked_int),
+ .STATUS (status_int),
+
+ .RST (RESET),
+ // Unused pin- tie low
+ .DSSEN (1'b0));
+
+ assign INPUT_CLK_STOPPED = status_int[1];
+ assign CLK_VALID = ( ( locked_int == 1'b 1 ) && ( status_int[1] == 1'b 0 ) );
+
+ // Output buffering
+ //-----------------------------------
+ assign clkfb = CLK_OUT1;
+
+ BUFG clkout1_buf
+ (.O (CLK_OUT1),
+ .I (clk0));
+
+
+
+
+endmodule
diff --git a/common/rtl/ipcore/clkmgr_dcm.veo b/common/rtl/ipcore/clkmgr_dcm.veo
new file mode 100644
index 0000000..c4e1d31
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm.veo
@@ -0,0 +1,79 @@
+//
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// "Output Output Phase Duty Pk-to-Pk Phase"
+// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
+//----------------------------------------------------------------------------
+// CLK_OUT1____50.000______0.000______50.0______200.000____150.000
+//
+//----------------------------------------------------------------------------
+// "Input Clock Freq (MHz) Input Jitter (UI)"
+//----------------------------------------------------------------------------
+// __primary______________50____________0.010
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+
+ clkmgr_dcm instance_name
+ (// Clock in ports
+ .CLK_IN1(CLK_IN1), // IN
+ // Clock out ports
+ .CLK_OUT1(CLK_OUT1), // OUT
+ // Status and control signals
+ .RESET(RESET),// IN
+ .INPUT_CLK_STOPPED(INPUT_CLK_STOPPED), // OUT
+ .CLK_VALID(CLK_VALID)); // OUT
+// INST_TAG_END ------ End INSTANTIATION Template ---------
diff --git a/common/rtl/ipcore/clkmgr_dcm.xco b/common/rtl/ipcore/clkmgr_dcm.xco
new file mode 100644
index 0000000..37f1a1d
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm.xco
@@ -0,0 +1,269 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Sun Feb 01 07:49:40 2015
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:clk_wiz:3.6
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
+# END Select
+# BEGIN Parameters
+CSET calc_done=DONE
+CSET clk_in_sel_port=CLK_IN_SEL
+CSET clk_out1_port=CLK_OUT1
+CSET clk_out1_use_fine_ps_gui=false
+CSET clk_out2_port=CLK_OUT2
+CSET clk_out2_use_fine_ps_gui=false
+CSET clk_out3_port=CLK_OUT3
+CSET clk_out3_use_fine_ps_gui=false
+CSET clk_out4_port=CLK_OUT4
+CSET clk_out4_use_fine_ps_gui=false
+CSET clk_out5_port=CLK_OUT5
+CSET clk_out5_use_fine_ps_gui=false
+CSET clk_out6_port=CLK_OUT6
+CSET clk_out6_use_fine_ps_gui=false
+CSET clk_out7_port=CLK_OUT7
+CSET clk_out7_use_fine_ps_gui=false
+CSET clk_valid_port=CLK_VALID
+CSET clkfb_in_n_port=CLKFB_IN_N
+CSET clkfb_in_p_port=CLKFB_IN_P
+CSET clkfb_in_port=CLKFB_IN
+CSET clkfb_in_signaling=SINGLE
+CSET clkfb_out_n_port=CLKFB_OUT_N
+CSET clkfb_out_p_port=CLKFB_OUT_P
+CSET clkfb_out_port=CLKFB_OUT
+CSET clkfb_stopped_port=CLKFB_STOPPED
+CSET clkin1_jitter_ps=200.0
+CSET clkin1_ui_jitter=0.010
+CSET clkin2_jitter_ps=100.0
+CSET clkin2_ui_jitter=0.010
+CSET clkout1_drives=BUFG
+CSET clkout1_requested_duty_cycle=50.0
+CSET clkout1_requested_out_freq=50
+CSET clkout1_requested_phase=0.000
+CSET clkout2_drives=BUFG
+CSET clkout2_requested_duty_cycle=50.0
+CSET clkout2_requested_out_freq=50
+CSET clkout2_requested_phase=0
+CSET clkout2_used=false
+CSET clkout3_drives=BUFG
+CSET clkout3_requested_duty_cycle=50.0
+CSET clkout3_requested_out_freq=100.000
+CSET clkout3_requested_phase=0.000
+CSET clkout3_used=false
+CSET clkout4_drives=BUFG
+CSET clkout4_requested_duty_cycle=50.0
+CSET clkout4_requested_out_freq=100.000
+CSET clkout4_requested_phase=0.000
+CSET clkout4_used=false
+CSET clkout5_drives=BUFG
+CSET clkout5_requested_duty_cycle=50.0
+CSET clkout5_requested_out_freq=100.000
+CSET clkout5_requested_phase=0.000
+CSET clkout5_used=false
+CSET clkout6_drives=BUFG
+CSET clkout6_requested_duty_cycle=50.0
+CSET clkout6_requested_out_freq=100.000
+CSET clkout6_requested_phase=0.000
+CSET clkout6_used=false
+CSET clkout7_drives=BUFG
+CSET clkout7_requested_duty_cycle=50.0
+CSET clkout7_requested_out_freq=100.000
+CSET clkout7_requested_phase=0.000
+CSET clkout7_used=false
+CSET clock_mgr_type=MANUAL
+CSET component_name=clkmgr_dcm
+CSET daddr_port=DADDR
+CSET dclk_port=DCLK
+CSET dcm_clk_feedback=1X
+CSET dcm_clk_out1_port=CLK0
+CSET dcm_clk_out2_port=CLK0
+CSET dcm_clk_out3_port=CLK0
+CSET dcm_clk_out4_port=CLK0
+CSET dcm_clk_out5_port=CLK0
+CSET dcm_clk_out6_port=CLK0
+CSET dcm_clkdv_divide=2.0
+CSET dcm_clkfx_divide=1
+CSET dcm_clkfx_multiply=4
+CSET dcm_clkgen_clk_out1_port=CLKFX
+CSET dcm_clkgen_clk_out2_port=CLKFX
+CSET dcm_clkgen_clk_out3_port=CLKFX
+CSET dcm_clkgen_clkfx_divide=1
+CSET dcm_clkgen_clkfx_md_max=0.000
+CSET dcm_clkgen_clkfx_multiply=4
+CSET dcm_clkgen_clkfxdv_divide=2
+CSET dcm_clkgen_clkin_period=10.000
+CSET dcm_clkgen_notes=None
+CSET dcm_clkgen_spread_spectrum=NONE
+CSET dcm_clkgen_startup_wait=false
+CSET dcm_clkin_divide_by_2=false
+CSET dcm_clkin_period=20.000
+CSET dcm_clkout_phase_shift=NONE
+CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
+CSET dcm_notes=None
+CSET dcm_phase_shift=0
+CSET dcm_pll_cascade=NONE
+CSET dcm_startup_wait=false
+CSET den_port=DEN
+CSET din_port=DIN
+CSET dout_port=DOUT
+CSET drdy_port=DRDY
+CSET dwe_port=DWE
+CSET feedback_source=FDBK_AUTO
+CSET in_freq_units=Units_MHz
+CSET in_jitter_units=Units_UI
+CSET input_clk_stopped_port=INPUT_CLK_STOPPED
+CSET jitter_options=UI
+CSET jitter_sel=No_Jitter
+CSET locked_port=LOCKED
+CSET mmcm_bandwidth=OPTIMIZED
+CSET mmcm_clkfbout_mult_f=4.000
+CSET mmcm_clkfbout_phase=0.000
+CSET mmcm_clkfbout_use_fine_ps=false
+CSET mmcm_clkin1_period=10.000
+CSET mmcm_clkin2_period=10.000
+CSET mmcm_clkout0_divide_f=4.000
+CSET mmcm_clkout0_duty_cycle=0.500
+CSET mmcm_clkout0_phase=0.000
+CSET mmcm_clkout0_use_fine_ps=false
+CSET mmcm_clkout1_divide=1
+CSET mmcm_clkout1_duty_cycle=0.500
+CSET mmcm_clkout1_phase=0.000
+CSET mmcm_clkout1_use_fine_ps=false
+CSET mmcm_clkout2_divide=1
+CSET mmcm_clkout2_duty_cycle=0.500
+CSET mmcm_clkout2_phase=0.000
+CSET mmcm_clkout2_use_fine_ps=false
+CSET mmcm_clkout3_divide=1
+CSET mmcm_clkout3_duty_cycle=0.500
+CSET mmcm_clkout3_phase=0.000
+CSET mmcm_clkout3_use_fine_ps=false
+CSET mmcm_clkout4_cascade=false
+CSET mmcm_clkout4_divide=1
+CSET mmcm_clkout4_duty_cycle=0.500
+CSET mmcm_clkout4_phase=0.000
+CSET mmcm_clkout4_use_fine_ps=false
+CSET mmcm_clkout5_divide=1
+CSET mmcm_clkout5_duty_cycle=0.500
+CSET mmcm_clkout5_phase=0.000
+CSET mmcm_clkout5_use_fine_ps=false
+CSET mmcm_clkout6_divide=1
+CSET mmcm_clkout6_duty_cycle=0.500
+CSET mmcm_clkout6_phase=0.000
+CSET mmcm_clkout6_use_fine_ps=false
+CSET mmcm_clock_hold=false
+CSET mmcm_compensation=ZHOLD
+CSET mmcm_divclk_divide=1
+CSET mmcm_notes=None
+CSET mmcm_ref_jitter1=0.010
+CSET mmcm_ref_jitter2=0.010
+CSET mmcm_startup_wait=false
+CSET num_out_clks=1
+CSET override_dcm=false
+CSET override_dcm_clkgen=false
+CSET override_mmcm=false
+CSET override_pll=false
+CSET platform=nt
+CSET pll_bandwidth=OPTIMIZED
+CSET pll_clk_feedback=CLKFBOUT
+CSET pll_clkfbout_mult=8
+CSET pll_clkfbout_phase=0.000
+CSET pll_clkin_period=20.0
+CSET pll_clkout0_divide=2
+CSET pll_clkout0_duty_cycle=0.500
+CSET pll_clkout0_phase=0.000
+CSET pll_clkout1_divide=10
+CSET pll_clkout1_duty_cycle=0.500
+CSET pll_clkout1_phase=0.000
+CSET pll_clkout2_divide=1
+CSET pll_clkout2_duty_cycle=0.500
+CSET pll_clkout2_phase=0.000
+CSET pll_clkout3_divide=1
+CSET pll_clkout3_duty_cycle=0.500
+CSET pll_clkout3_phase=0.000
+CSET pll_clkout4_divide=1
+CSET pll_clkout4_duty_cycle=0.500
+CSET pll_clkout4_phase=0.000
+CSET pll_clkout5_divide=1
+CSET pll_clkout5_duty_cycle=0.500
+CSET pll_clkout5_phase=0.000
+CSET pll_compensation=SYSTEM_SYNCHRONOUS
+CSET pll_divclk_divide=1
+CSET pll_notes=None
+CSET pll_ref_jitter=0.010
+CSET power_down_port=POWER_DOWN
+CSET prim_in_freq=50
+CSET prim_in_jitter=0.010
+CSET prim_source=No_buffer
+CSET primary_port=CLK_IN1
+CSET primitive=MMCM
+CSET primtype_sel=DCM_SP
+CSET psclk_port=PSCLK
+CSET psdone_port=PSDONE
+CSET psen_port=PSEN
+CSET psincdec_port=PSINCDEC
+CSET relative_inclk=REL_PRIMARY
+CSET reset_port=RESET
+CSET secondary_in_freq=100.000
+CSET secondary_in_jitter=0.010
+CSET secondary_port=CLK_IN2
+CSET secondary_source=Single_ended_clock_capable_pin
+CSET ss_mod_freq=250
+CSET ss_mode=CENTER_HIGH
+CSET status_port=STATUS
+CSET summary_strings=empty
+CSET use_clk_valid=true
+CSET use_clkfb_stopped=false
+CSET use_dyn_phase_shift=false
+CSET use_dyn_reconfig=false
+CSET use_freeze=false
+CSET use_freq_synth=true
+CSET use_inclk_stopped=true
+CSET use_inclk_switchover=false
+CSET use_locked=false
+CSET use_max_i_jitter=false
+CSET use_min_o_jitter=false
+CSET use_min_power=false
+CSET use_phase_alignment=true
+CSET use_power_down=false
+CSET use_reset=true
+CSET use_spread_spectrum=false
+CSET use_spread_spectrum_1=false
+CSET use_status=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-05-10T12:44:55Z
+# END Extra information
+GENERATE
+# CRC: d6857c2d
diff --git a/common/rtl/ipcore/clkmgr_dcm.xdc b/common/rtl/ipcore/clkmgr_dcm.xdc
new file mode 100644
index 0000000..9ecc102
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm.xdc
@@ -0,0 +1,67 @@
+# file: clkmgr_dcm.xdc
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system
+#----------------------------------------------------------------
+create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1]
+set_propagated_clock CLK_IN1
+set_input_jitter CLK_IN1 0.2
+
+set_false_path -from [get_ports "RESET"]
+
+# Derived clock periods. These are commented out because they are
+# automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you
+# can copy them into your module level timing checks
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
diff --git a/common/rtl/ipcore/clkmgr_dcm.xise b/common/rtl/ipcore/clkmgr_dcm.xise
new file mode 100644
index 0000000..7369d3b
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm.xise
@@ -0,0 +1,74 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="clkmgr_dcm.ucf" xil_pn:type="FILE_UCF">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="clkmgr_dcm.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Module|clkmgr_dcm" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="clkmgr_dcm.v" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clkmgr_dcm" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="clkmgr_dcm" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-02-01T08:50:04" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="67BEB73269CA45ADBC7997434CEC13CB" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings>
+ <binding xil_pn:location="/clkmgr_dcm" xil_pn:name="clkmgr_dcm.ucf"/>
+ </bindings>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
diff --git a/common/rtl/ipcore/clkmgr_dcm/clk_wiz_v3_6_readme.txt b/common/rtl/ipcore/clkmgr_dcm/clk_wiz_v3_6_readme.txt
new file mode 100644
index 0000000..91dcdd0
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/clk_wiz_v3_6_readme.txt
@@ -0,0 +1,184 @@
+CHANGE LOG for LogiCORE Clocking Wizard V3.6
+
+ Release Date: June 19, 2013
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION
+2. DEVICE SUPPORT
+3. NEW FEATURE HISTORY
+4. RESOLVED ISSUES
+5. KNOWN ISSUES & LIMITATIONS
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY
+8. LEGAL DISCLAIMER
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+ http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+ http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+ http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+ 2.1 ISE
+
+
+ The following device families are supported by the core for this release.
+
+ All 7 Series devices
+
+
+ Zynq-7000 devices
+ Zynq-7000
+ Defense Grade Zynq-7000Q (XQ)
+
+
+ All Virtex-6 devices
+
+
+ All Spartan-6 devices
+
+
+................................................................................
+
+3. NEW FEATURE HISTORY
+
+
+ 3.1 ISE
+
+ - Spread Spectrum support for 7 series MMCME2
+
+ - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+ 4.1 ISE
+
+ Resolved issue with example design becoming core top in planAhead
+
+ Resolved issue with Virtex6 MMCM instantiation for VHDL project
+ Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+ 5.1 ISE
+
+
+ The most recent information, including known issues, workarounds, and
+ resolutions for this version is provided in the IP Release Notes Guide
+ located at
+
+ www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+
+
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date By Version Description
+================================================================================
+06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
+10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
+07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
+04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
+01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
+06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
+03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
+12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
+09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
+07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
+04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
+12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
+09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
+06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
+04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
+================================================================================
+
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
diff --git a/common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_readme.txt b/common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_readme.txt
new file mode 100644
index 0000000..91dcdd0
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_readme.txt
@@ -0,0 +1,184 @@
+CHANGE LOG for LogiCORE Clocking Wizard V3.6
+
+ Release Date: June 19, 2013
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION
+2. DEVICE SUPPORT
+3. NEW FEATURE HISTORY
+4. RESOLVED ISSUES
+5. KNOWN ISSUES & LIMITATIONS
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY
+8. LEGAL DISCLAIMER
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+ http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+ http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+ http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+ 2.1 ISE
+
+
+ The following device families are supported by the core for this release.
+
+ All 7 Series devices
+
+
+ Zynq-7000 devices
+ Zynq-7000
+ Defense Grade Zynq-7000Q (XQ)
+
+
+ All Virtex-6 devices
+
+
+ All Spartan-6 devices
+
+
+................................................................................
+
+3. NEW FEATURE HISTORY
+
+
+ 3.1 ISE
+
+ - Spread Spectrum support for 7 series MMCME2
+
+ - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+ 4.1 ISE
+
+ Resolved issue with example design becoming core top in planAhead
+
+ Resolved issue with Virtex6 MMCM instantiation for VHDL project
+ Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+ 5.1 ISE
+
+
+ The most recent information, including known issues, workarounds, and
+ resolutions for this version is provided in the IP Release Notes Guide
+ located at
+
+ www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+
+
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date By Version Description
+================================================================================
+06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
+10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
+07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
+04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
+01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
+06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
+03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
+12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
+09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
+07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
+04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
+12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
+09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
+06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
+04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
+================================================================================
+
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
diff --git a/common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_vinfo.html b/common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_vinfo.html
new file mode 100644
index 0000000..d6deba0
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_vinfo.html
@@ -0,0 +1,195 @@
+<HTML>
+<HEAD>
+<TITLE>clk_wiz_v3_6_vinfo</TITLE>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
+</HEAD>
+<BODY>
+<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
+CHANGE LOG for LogiCORE Clocking Wizard V3.6
+
+ Release Date: June 19, 2013
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION
+2. DEVICE SUPPORT
+3. NEW FEATURE HISTORY
+4. RESOLVED ISSUES
+5. KNOWN ISSUES & LIMITATIONS
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY
+8. LEGAL DISCLAIMER
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+ <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
+
+For system requirements:
+
+ <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+ <A HREF="http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/">www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/</A>
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+ 2.1 ISE
+
+
+ The following device families are supported by the core for this release.
+
+ All 7 Series devices
+
+
+ Zynq-7000 devices
+ Zynq-7000
+ Defense Grade Zynq-7000Q (XQ)
+
+
+ All Virtex-6 devices
+
+
+ All Spartan-6 devices
+
+
+................................................................................
+
+3. NEW FEATURE HISTORY
+
+
+ 3.1 ISE
+
+ - Spread Spectrum support for 7 series MMCME2
+
+ - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+ 4.1 ISE
+
+ Resolved issue with example design becoming core top in planAhead
+
+ Resolved issue with Virtex6 MMCM instantiation for VHDL project
+ Please refer to AR 50719 - <A HREF="http://www.xilinx.com/support/answers/50719.htm">www.xilinx.com/support/answers/50719.htm</A>
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+ 5.1 ISE
+
+
+ The most recent information, including known issues, workarounds, and
+ resolutions for this version is provided in the IP Release Notes Guide
+ located at
+
+ <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
+
+
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date By Version Description
+================================================================================
+06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
+10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
+07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
+04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
+01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support
+06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support
+03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support
+12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
+09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
+07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
+04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
+12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
+09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
+06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
+04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support
+================================================================================
+
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
+</FONT>
+</PRE>
+</BODY>
+</HTML>
diff --git a/common/rtl/ipcore/clkmgr_dcm/doc/pg065_clk_wiz.pdf b/common/rtl/ipcore/clkmgr_dcm/doc/pg065_clk_wiz.pdf
new file mode 100644
index 0000000..a7daa60
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/doc/pg065_clk_wiz.pdf
Binary files differ
diff --git a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf b/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf
new file mode 100644
index 0000000..dffb528
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf
@@ -0,0 +1,60 @@
+# file: clkmgr_dcm_exdes.ucf
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
+
+
+# FALSE PATH constraints
+PIN "COUNTER_RESET" TIG;
+PIN "RESET" TIG;
+
diff --git a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v b/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v
new file mode 100644
index 0000000..10627b3
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v
@@ -0,0 +1,164 @@
+// file: clkmgr_dcm_exdes.v
+//
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+
+//----------------------------------------------------------------------------
+// Clocking wizard example design
+//----------------------------------------------------------------------------
+// This example design instantiates the created clocking network, where each
+// output clock drives a counter. The high bit of each counter is ported.
+//----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+module clkmgr_dcm_exdes
+ #(
+ parameter TCQ = 100
+ )
+ (// Clock in ports
+ input CLK_IN1,
+ // Reset that only drives logic in example design
+ input COUNTER_RESET,
+ output [1:1] CLK_OUT,
+ // High bits of counters driven by clocks
+ output COUNT,
+ // Status and control signals
+ input RESET,
+ output INPUT_CLK_STOPPED,
+ output CLK_VALID
+ );
+
+ // Parameters for the counters
+ //-------------------------------
+ // Counter width
+ localparam C_W = 16;
+ // Create reset for the counters
+ wire reset_int = RESET || COUNTER_RESET;
+
+ reg rst_sync;
+ reg rst_sync_int;
+ reg rst_sync_int1;
+ reg rst_sync_int2;
+
+
+
+ // Declare the clocks and counter
+ wire clk_int;
+ wire clk_n;
+ wire clk;
+ reg [C_W-1:0] counter;
+
+ // Insert BUFGs on all input clocks that don't already have them
+ //--------------------------------------------------------------
+ BUFG clkin1_buf
+ (.O (clk_in1_buf),
+ .I (CLK_IN1));
+
+ // Instantiation of the clocking network
+ //--------------------------------------
+ clkmgr_dcm clknetwork
+ (// Clock in ports
+ .CLK_IN1 (clk_in1_buf),
+ // Clock out ports
+ .CLK_OUT1 (clk_int),
+ // Status and control signals
+ .RESET (RESET),
+ .INPUT_CLK_STOPPED (INPUT_CLK_STOPPED),
+ .CLK_VALID (CLK_VALID));
+
+ assign clk_n = ~clk;
+
+ ODDR2 clkout_oddr
+ (.Q (CLK_OUT[1]),
+ .C0 (clk),
+ .C1 (clk_n),
+ .CE (1'b1),
+ .D0 (1'b1),
+ .D1 (1'b0),
+ .R (1'b0),
+ .S (1'b0));
+
+ // Connect the output clocks to the design
+ //-----------------------------------------
+ assign clk = clk_int;
+
+
+ // Reset synchronizer
+ //-----------------------------------
+ always @(posedge reset_int or posedge clk) begin
+ if (reset_int) begin
+ rst_sync <= 1'b1;
+ rst_sync_int <= 1'b1;
+ rst_sync_int1 <= 1'b1;
+ rst_sync_int2 <= 1'b1;
+ end
+ else begin
+ rst_sync <= 1'b0;
+ rst_sync_int <= rst_sync;
+ rst_sync_int1 <= rst_sync_int;
+ rst_sync_int2 <= rst_sync_int1;
+ end
+ end
+
+
+ // Output clock sampling
+ //-----------------------------------
+ always @(posedge clk or posedge rst_sync_int2) begin
+ if (rst_sync_int2) begin
+ counter <= #TCQ { C_W { 1'b 0 } };
+ end else begin
+ counter <= #TCQ counter + 1'b 1;
+ end
+ end
+
+ // alias the high bit to the output
+ assign COUNT = counter[C_W-1];
+
+
+
+endmodule
diff --git a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc b/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc
new file mode 100644
index 0000000..787023d
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc
@@ -0,0 +1,69 @@
+# file: clkmgr_dcm_exdes.xdc
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system
+#----------------------------------------------------------------
+create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1]
+set_propagated_clock CLK_IN1
+set_input_jitter CLK_IN1 0.2
+
+# FALSE PATH constraint added on COUNTER_RESET
+set_false_path -from [get_ports "COUNTER_RESET"]
+set_false_path -from [get_ports "RESET"]
+
+# Derived clock periods. These are commented out because they are
+# automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you
+# can copy them into your module level timing checks
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/implement.bat b/common/rtl/ipcore/clkmgr_dcm/implement/implement.bat
new file mode 100644
index 0000000..3d313d5
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/implement/implement.bat
@@ -0,0 +1,90 @@
+REM file: implement.bat
+REM
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM
+
+REM -----------------------------------------------------------------------------
+REM Script to synthesize and implement the RTL provided for the clocking wizard
+REM -----------------------------------------------------------------------------
+
+REM Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+REM Copy unisim_comp.v file to results directory
+copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\
+
+REM Synthesize the Verilog Wrapper Files
+echo 'Synthesizing Clocking Wizard design with XST'
+xst -ifn xst.scr
+move clkmgr_dcm_exdes.ngc results\
+
+REM Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\clkmgr_dcm_exdes.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -uc clkmgr_dcm_exdes.ucf clkmgr_dcm_exdes
+
+echo 'Running map'
+map -timing -pr b clkmgr_dcm_exdes -o mapped.ncd
+
+echo 'Running par'
+par -w mapped.ncd routed mapped.pcf
+
+echo 'Running trce'
+trce -e 10 routed -o routed mapped.pcf
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level model for the clocking wizard example design'
+netgen -ofmt verilog -sim -sdf_anno false -tm clkmgr_dcm_exdes -w routed.ncd routed.v
+cd ..
+
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/implement.sh b/common/rtl/ipcore/clkmgr_dcm/implement/implement.sh
new file mode 100644
index 0000000..2c64bee
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/implement/implement.sh
@@ -0,0 +1,91 @@
+#!/bin/sh
+# file: implement.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the clocking wizard
+#-----------------------------------------------------------------------------
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+# Copy unisim_comp.v file to results directory
+cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
+
+# Synthesize the Verilog Wrapper Files
+echo 'Synthesizing Clocking Wizard design with XST'
+xst -ifn xst.scr
+mv clkmgr_dcm_exdes.ngc results/
+
+# Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/clkmgr_dcm_exdes.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -uc clkmgr_dcm_exdes.ucf clkmgr_dcm_exdes
+
+echo 'Running map'
+map -timing clkmgr_dcm_exdes -o mapped.ncd
+
+echo 'Running par'
+par -w mapped.ncd routed mapped.pcf
+
+echo 'Running trce'
+trce -e 10 routed -o routed mapped.pcf
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level model for the clocking wizard example design'
+netgen -ofmt verilog -sim -sdf_anno false -tm clkmgr_dcm_exdes -w routed.ncd routed.v
+
+cd ..
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.bat b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.bat
new file mode 100644
index 0000000..9782028
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.bat
@@ -0,0 +1,58 @@
+REM file: planAhead_ise.bat
+REM
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM
+
+REM-----------------------------------------------------------------------------
+REM Script to synthesize and implement the RTL provided for the clocking wizard
+REM-----------------------------------------------------------------------------
+
+del \f results
+mkdir results
+cd results
+
+planAhead -mode batch -source ..\planAhead_ise.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.sh b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.sh
new file mode 100644
index 0000000..7f436b6
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.sh
@@ -0,0 +1,59 @@
+#!/bin/sh
+# file: planAhead_ise.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the clocking wizard
+#-----------------------------------------------------------------------------
+
+rm -rf results
+mkdir results
+cd results
+
+planAhead -mode batch -source ../planAhead_ise.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.tcl b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.tcl
new file mode 100644
index 0000000..ab77638
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.tcl
@@ -0,0 +1,78 @@
+# file: planAhead_ise.tcl
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+set projDir [file dirname [info script]]
+set projName clkmgr_dcm
+set topName clkmgr_dcm_exdes
+set device xc6slx45csg324-3
+
+create_project $projName $projDir/results/$projName -part $device
+
+set_property design_mode RTL [get_filesets sources_1]
+
+## Source files
+#set verilogSources [glob $srcDir/*.v]
+import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/clkmgr_dcm_exdes.v
+import_files -fileset [get_filesets sources_1] -force -norecurse ../../../clkmgr_dcm.v
+
+
+#UCF file
+import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/clkmgr_dcm_exdes.ucf
+
+set_property top $topName [get_property srcset [current_run]]
+
+launch_runs -runs synth_1
+wait_on_run synth_1
+
+set_property add_step Bitgen [get_runs impl_1]
+launch_runs -runs impl_1
+wait_on_run impl_1
+
+
+
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.bat b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.bat
new file mode 100644
index 0000000..3e1e03b
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.bat
@@ -0,0 +1,58 @@
+REM file: planAhead_rdn.sh
+REM
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM
+
+REM-----------------------------------------------------------------------------
+REM Script to synthesize and implement the RTL provided for the XADC wizard
+REM-----------------------------------------------------------------------------
+
+del \f results
+mkdir results
+cd results
+
+planAhead -mode batch -source ..\planAhead_rdn.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.sh b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.sh
new file mode 100644
index 0000000..a5adee8
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.sh
@@ -0,0 +1,57 @@
+#!/bin/sh
+# file: planAhead_rdn.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the XADC wizard
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+planAhead -mode batch -source ../planAhead_rdn.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl
new file mode 100644
index 0000000..e8c0fdf
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl
@@ -0,0 +1,69 @@
+# file : planAhead_rdn.tcl
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+set device xc6slx45csg324-3
+set projName clkmgr_dcm
+set design clkmgr_dcm
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module clkmgr_dcm_exdes
+set_property top clkmgr_dcm_exdes [get_property srcset [current_run]]
+add_files -norecurse {../../../clkmgr_dcm.v}
+add_files -norecurse {../../example_design/clkmgr_dcm_exdes.v}
+import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/clkmgr_dcm_exdes.xdc}
+synth_design
+opt_design
+place_design
+route_design
+write_sdf -rename_top_module clkmgr_dcm_exdes -file routed.sdf
+write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module clkmgr_dcm_exdes -file routed.v
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file report.drc
+write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/xst.prj b/common/rtl/ipcore/clkmgr_dcm/implement/xst.prj
new file mode 100644
index 0000000..cd0e0e6
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/implement/xst.prj
@@ -0,0 +1,2 @@
+verilog work ../../clkmgr_dcm.v
+verilog work ../example_design/clkmgr_dcm_exdes.v
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/xst.scr b/common/rtl/ipcore/clkmgr_dcm/implement/xst.scr
new file mode 100644
index 0000000..20d09f4
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/implement/xst.scr
@@ -0,0 +1,9 @@
+run
+-ifmt MIXED
+-top clkmgr_dcm_exdes
+-p xc6slx45-csg324-3
+-ifn xst.prj
+-ofn clkmgr_dcm_exdes
+-keep_hierarchy soft
+-equivalent_register_removal no
+-max_fanout 65535
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v b/common/rtl/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v
new file mode 100644
index 0000000..ee24750
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v
@@ -0,0 +1,145 @@
+// file: clkmgr_dcm_tb.v
+//
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+
+//----------------------------------------------------------------------------
+// Clocking wizard demonstration testbench
+//----------------------------------------------------------------------------
+// This demonstration testbench instantiates the example design for the
+// clocking wizard. Input clocks are toggled, which cause the clocking
+// network to lock and the counters to increment.
+//----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+`define wait_lock @(posedge CLK_VALID)
+
+module clkmgr_dcm_tb ();
+
+ // Clock to Q delay of 100ps
+ localparam TCQ = 100;
+
+
+ // timescale is 1ps/1ps
+ localparam ONE_NS = 1000;
+ localparam PHASE_ERR_MARGIN = 100; // 100ps
+ // how many cycles to run
+ localparam COUNT_PHASE = 1024;
+ // we'll be using the period in many locations
+ localparam time PER1 = 20.0*ONE_NS;
+ localparam time PER1_1 = PER1/2;
+ localparam time PER1_2 = PER1 - PER1/2;
+
+ // Declare the input clock signals
+ reg CLK_IN1 = 1;
+
+ // The high bit of the sampling counter
+ wire COUNT;
+ // Status and control signals
+ reg RESET = 0;
+ wire INPUT_CLK_STOPPED;
+ wire CLK_VALID;
+ reg COUNTER_RESET = 0;
+wire [1:1] CLK_OUT;
+//Freq Check using the M & D values setting and actual Frequency generated
+
+
+ // Input clock generation
+ //------------------------------------
+ always begin
+ CLK_IN1 = #PER1_1 ~CLK_IN1;
+ CLK_IN1 = #PER1_2 ~CLK_IN1;
+ end
+
+ // Test sequence
+ reg [15*8-1:0] test_phase = "";
+ initial begin
+ // Set up any display statements using time to be readable
+ $timeformat(-12, 2, "ps", 10);
+ COUNTER_RESET = 0;
+ test_phase = "reset";
+ RESET = 1;
+ #(PER1*6);
+ RESET = 0;
+ test_phase = "wait lock";
+ `wait_lock;
+ #(PER1*6);
+ COUNTER_RESET = 1;
+ #(PER1*20)
+ COUNTER_RESET = 0;
+
+ test_phase = "counting";
+ #(PER1*COUNT_PHASE);
+
+ $display("SIMULATION PASSED");
+ $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
+ $finish;
+ end
+
+ // Instantiation of the example design containing the clock
+ // network and sampling counters
+ //---------------------------------------------------------
+ clkmgr_dcm_exdes
+ #(
+ .TCQ (TCQ)
+ ) dut
+ (// Clock in ports
+ .CLK_IN1 (CLK_IN1),
+ // Reset for logic in example design
+ .COUNTER_RESET (COUNTER_RESET),
+ .CLK_OUT (CLK_OUT),
+ // High bits of the counters
+ .COUNT (COUNT),
+ // Status and control signals
+ .RESET (RESET),
+ .INPUT_CLK_STOPPED (INPUT_CLK_STOPPED),
+ .CLK_VALID (CLK_VALID));
+
+// Freq Check
+
+endmodule
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl
new file mode 100644
index 0000000..e19ead8
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl
@@ -0,0 +1,8 @@
+# file: simcmds.tcl
+
+# create the simulation script
+vcd dumpfile isim.vcd
+vcd dumpvars -m /clkmgr_dcm_tb -l 0
+wave add /
+run 50000ns
+quit
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat
new file mode 100644
index 0000000..80904cb
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat
@@ -0,0 +1,59 @@
+REM file: simulate_isim.bat
+REM
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM
+
+vlogcomp -work work %XILINX%\verilog\src\glbl.v
+vlogcomp -work work ..\..\..\clkmgr_dcm.v
+vlogcomp -work work ..\..\example_design\clkmgr_dcm_exdes.v
+vlogcomp -work work ..\clkmgr_dcm_tb.v
+
+REM compile the project
+fuse work.clkmgr_dcm_tb work.glbl -L unisims_ver -o clkmgr_dcm_isim.exe
+
+REM run the simulation script
+.\clkmgr_dcm_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh
new file mode 100644
index 0000000..9fb5029
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh
@@ -0,0 +1,61 @@
+# file: simulate_isim.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# nt
+# create the project
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -work work ../../../clkmgr_dcm.v
+vlogcomp -work work ../../example_design/clkmgr_dcm_exdes.v
+vlogcomp -work work ../clkmgr_dcm_tb.v
+
+# compile the project
+fuse work.clkmgr_dcm_tb work.glbl -L unisims_ver -o clkmgr_dcm_isim.exe
+
+# run the simulation script
+./clkmgr_dcm_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat
new file mode 100644
index 0000000..7497cd9
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat
@@ -0,0 +1,61 @@
+REM file: simulate_mti.bat
+REM
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM
+
+REM set up the working directory
+vlib work
+
+REM compile all of the files
+vlog -work work %XILINX%\verilog\src\glbl.v
+vlog -work work ..\..\..\clkmgr_dcm.v
+vlog -work work ..\..\example_design\clkmgr_dcm_exdes.v
+vlog -work work ..\clkmgr_dcm_tb.v
+
+REM run the simulation
+vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.clkmgr_dcm_tb work.glbl
+
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do
new file mode 100644
index 0000000..b0e526f
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do
@@ -0,0 +1,65 @@
+# file: simulate_mti.do
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $env(XILINX)/verilog/src/glbl.v
+vlog -work work ../../../clkmgr_dcm.v
+vlog -work work ../../example_design/clkmgr_dcm_exdes.v
+vlog -work work ../clkmgr_dcm_tb.v
+
+# run the simulation
+vsim -t ps -voptargs="+acc" -L unisims_ver work.clkmgr_dcm_tb work.glbl
+do wave.do
+log clkmgr_dcm_tb/dut/counter
+log -r /*
+run 50000ns
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh
new file mode 100644
index 0000000..66099e0
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh
@@ -0,0 +1,61 @@
+#/bin/sh
+# file: simulate_mti.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $XILINX/verilog/src/glbl.v
+vlog -work work ../../../clkmgr_dcm.v
+vlog -work work ../../example_design/clkmgr_dcm_exdes.v
+vlog -work work ../clkmgr_dcm_tb.v
+
+# run the simulation
+vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.clkmgr_dcm_tb work.glbl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh
new file mode 100644
index 0000000..01b0412
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh
@@ -0,0 +1,62 @@
+#/bin/sh
+# file: simulate_ncsim.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# set up the working directory
+mkdir work
+
+# compile all of the files
+ncvlog -work work ${XILINX}/verilog/src/glbl.v
+ncvlog -work work ../../../clkmgr_dcm.v
+ncvlog -work work ../../example_design/clkmgr_dcm_exdes.v
+ncvlog -work work ../clkmgr_dcm_tb.v
+
+# elaborate and run the simulation
+ncelab -work work -access +wc work.clkmgr_dcm_tb work.glbl
+ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.clkmgr_dcm_tb
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh
new file mode 100644
index 0000000..39668df
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh
@@ -0,0 +1,72 @@
+#!/bin/sh
+# file: simulate_vcs.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# remove old files
+rm -rf simv* csrc DVEfiles AN.DB
+
+# compile all of the files
+# Note that -sverilog is not strictly required- You can
+# remove the -sverilog if you change the type of the
+# localparam for the periods in the testbench file to
+# [63:0] from time
+vlogan -sverilog \
+ ${XILINX}/verilog/src/glbl.v \
+ ../../../clkmgr_dcm.v \
+ ../../example_design/clkmgr_dcm_exdes.v \
+ ../clkmgr_dcm_tb.v
+
+# prepare the simulation
+vcs +vcs+lic+wait -debug clkmgr_dcm_tb glbl
+
+# run the simulation
+./simv -ucli -i ucli_commands.key
+
+# launch the viewer
+dve -vpd vcdplus.vpd -session vcs_session.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key
new file mode 100644
index 0000000..2bbdd0f
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key
@@ -0,0 +1,5 @@
+call {$vcdpluson}
+call {$vcdplusmemon(clkmgr_dcm_tb.dut.counter)}
+run
+call {$vcdplusclose}
+quit
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl
new file mode 100644
index 0000000..628e55a
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl
@@ -0,0 +1,18 @@
+gui_open_window Wave
+gui_sg_create clkmgr_dcm_group
+gui_list_add_group -id Wave.1 {clkmgr_dcm_group}
+gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.test_phase}
+gui_set_radix -radix {ascii} -signals {clkmgr_dcm_tb.test_phase}
+gui_sg_addsignal -group clkmgr_dcm_group {{Input_clocks}} -divider
+gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.CLK_IN1}
+gui_sg_addsignal -group clkmgr_dcm_group {{Output_clocks}} -divider
+gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.dut.clk}
+gui_list_expand -id Wave.1 clkmgr_dcm_tb.dut.clk
+gui_sg_addsignal -group clkmgr_dcm_group {{Status_control}} -divider
+gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.RESET}
+gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.USE_INCLK_STOPPED}
+gui_sg_addsignal -group clkmgr_dcm_group {{Counters}} -divider
+gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.COUNT}
+gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.dut.counter}
+gui_list_expand -id Wave.1 clkmgr_dcm_tb.dut.counter
+gui_zoom -window Wave.1 -full
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.do b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.do
new file mode 100644
index 0000000..eee7422
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.do
@@ -0,0 +1,60 @@
+# file: wave.do
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+add wave -noupdate -format Literal -radix ascii /clkmgr_dcm_tb/test_phase
+add wave -noupdate -divider {Input clocks}
+add wave -noupdate -format Logic /clkmgr_dcm_tb/CLK_IN1
+add wave -noupdate -divider {Output clocks}
+add wave -noupdate -format Logic /clkmgr_dcm_tb/dut/clk
+add wave -noupdate -divider Status/control
+add wave -noupdate -format Logic /clkmgr_dcm_tb/RESET
+add wave -noupdate -format Logic /clkmgr_dcm_tb/INPUT_CLK_STOPPED
+add wave -noupdate -divider Counters
+add wave -noupdate -format Literal -radix hexadecimal /clkmgr_dcm_tb/COUNT
+add wave -noupdate -format Literal -radix hexadecimal /clkmgr_dcm_tb/dut/counter
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.sv b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.sv
new file mode 100644
index 0000000..c3c3eef
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.sv
@@ -0,0 +1,118 @@
+# file: wave.sv
+#
+# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# Get the windows set up
+#
+if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} {
+ window geometry "Design Browser 1" 1054x819+536+322
+}
+window target "Design Browser 1" on
+browser using {Design Browser 1}
+browser set \
+ -scope nc::clkmgr_dcm_tb
+browser yview see nc::clkmgr_dcm_tb
+browser timecontrol set -lock 0
+
+if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} {
+ window geometry "Waveform 1" 1010x600+0+541
+}
+window target "Waveform 1" on
+waveform using {Waveform 1}
+waveform sidebar visibility partial
+waveform set \
+ -primarycursor TimeA \
+ -signalnames name \
+ -signalwidth 175 \
+ -units ns \
+ -valuewidth 75
+cursor set -using TimeA -time 0
+waveform baseline set -time 0
+waveform xview limits 0 20000n
+
+#
+# Define signal groups
+#
+catch {group new -name {Output clocks} -overlay 0}
+catch {group new -name {Status/control} -overlay 0}
+catch {group new -name {Counters} -overlay 0}
+
+set id [waveform add -signals [list {nc::clkmgr_dcm_tb.CLK_IN1}]]
+
+group using {Output clocks}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+ {clkmgr_dcm_tb.dut.clk} \
+
+group using {Counters}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+ {clkmgr_dcm_tb.dut.counter} \
+
+group using {Status/control}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+ {nc::clkmgr_dcm_tb.RESET} {nc::clkmgr_dcm_tb.INPUT_CLK_STOPPED}
+
+set id [waveform add -signals [list {nc::clkmgr_dcm_tb.COUNT} ]]
+
+set id [waveform add -signals [list {nc::clkmgr_dcm_tb.test_phase} ]]
+waveform format $id -radix %a
+
+set groupId [waveform add -groups {{Input clocks}}]
+set groupId [waveform add -groups {{Output clocks}}]
+set groupId [waveform add -groups {{Status/control}}]
+set groupId [waveform add -groups {{Counters}}]
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v
new file mode 100644
index 0000000..9618253
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v
@@ -0,0 +1,149 @@
+// file: clkmgr_dcm_tb.v
+//
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+
+//----------------------------------------------------------------------------
+// Clocking wizard demonstration testbench
+//----------------------------------------------------------------------------
+// This demonstration testbench instantiates the example design for the
+// clocking wizard. Input clocks are toggled, which cause the clocking
+// network to lock and the counters to increment.
+//----------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+`define wait_lock @(posedge CLK_VALID)
+
+module clkmgr_dcm_tb ();
+
+ // Clock to Q delay of 100ps
+ localparam TCQ = 100;
+
+
+ // timescale is 1ps/1ps
+ localparam ONE_NS = 1000;
+ localparam PHASE_ERR_MARGIN = 100; // 100ps
+ // how many cycles to run
+ localparam COUNT_PHASE = 1024;
+ // we'll be using the period in many locations
+ localparam time PER1 = 20.0*ONE_NS;
+ localparam time PER1_1 = PER1/2;
+ localparam time PER1_2 = PER1 - PER1/2;
+
+ // Declare the input clock signals
+ reg CLK_IN1 = 1;
+
+ // The high bit of the sampling counter
+ wire COUNT;
+ // Status and control signals
+ reg RESET = 0;
+ wire INPUT_CLK_STOPPED;
+ wire CLK_VALID;
+ reg COUNTER_RESET = 0;
+wire [1:1] CLK_OUT;
+//Freq Check using the M & D values setting and actual Frequency generated
+
+ reg [13:0] timeout_counter = 14'b00000000000000;
+
+ // Input clock generation
+ //------------------------------------
+ always begin
+ CLK_IN1 = #PER1_1 ~CLK_IN1;
+ CLK_IN1 = #PER1_2 ~CLK_IN1;
+ end
+
+ // Test sequence
+ reg [15*8-1:0] test_phase = "";
+ initial begin
+ // Set up any display statements using time to be readable
+ $timeformat(-12, 2, "ps", 10);
+ $display ("Timing checks are not valid");
+ COUNTER_RESET = 0;
+ test_phase = "reset";
+ RESET = 1;
+ #(PER1*6);
+ RESET = 0;
+ test_phase = "wait lock";
+ `wait_lock;
+ #(PER1*6);
+ COUNTER_RESET = 1;
+ #(PER1*19.5)
+ COUNTER_RESET = 0;
+ #(PER1*1)
+ $display ("Timing checks are valid");
+ test_phase = "counting";
+ #(PER1*COUNT_PHASE);
+
+ $display("SIMULATION PASSED");
+ $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
+ $finish;
+ end
+
+
+
+ // Instantiation of the example design containing the clock
+ // network and sampling counters
+ //---------------------------------------------------------
+ clkmgr_dcm_exdes
+ dut
+ (// Clock in ports
+ .CLK_IN1 (CLK_IN1),
+ // Reset for logic in example design
+ .COUNTER_RESET (COUNTER_RESET),
+ .CLK_OUT (CLK_OUT),
+ // High bits of the counters
+ .COUNT (COUNT),
+ // Status and control signals
+ .RESET (RESET),
+ .INPUT_CLK_STOPPED (INPUT_CLK_STOPPED),
+ .CLK_VALID (CLK_VALID));
+
+
+// Freq Check
+
+endmodule
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file
new file mode 100644
index 0000000..d59e315
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file
@@ -0,0 +1,2 @@
+COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X",
+SCOPE = clkmgr_dcm_tb.dut;
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl
new file mode 100644
index 0000000..14523af
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl
@@ -0,0 +1,9 @@
+# file: simcmds.tcl
+
+# create the simulation script
+vcd dumpfile isim.vcd
+vcd dumpvars -m /clkmgr_dcm_tb -l 0
+wave add /
+run 50000ns
+quit
+
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh
new file mode 100644
index 0000000..0152cb0
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh
@@ -0,0 +1,62 @@
+# file: simulate_isim.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# create the project
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -work work ../../implement/results/routed.v
+vlogcomp -work work clkmgr_dcm_tb.v
+
+# compile the project
+fuse work.clkmgr_dcm_tb work.glbl -L secureip -L simprims_ver -o clkmgr_dcm_isim.exe
+
+# run the simulation script
+./clkmgr_dcm_isim.exe -tclbatch simcmds.tcl -sdfmax /clkmgr_dcm_tb/dut=../../implement/results/routed.sdf
+
+# run the simulation script
+#./clkmgr_dcm_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat
new file mode 100644
index 0000000..8a08dc0
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat
@@ -0,0 +1,59 @@
+REM file: simulate_mti.bat
+REM
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM
+# set up the working directory
+set work work
+vlib work
+
+REM compile all of the files
+vlog -work work %XILINX%\verilog\src\glbl.v
+vlog -work work ..\..\implement\results\routed.v
+vlog -work work clkmgr_dcm_tb.v
+
+REM run the simulation
+vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clkmgr_dcm_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.clkmgr_dcm_tb work.glbl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do
new file mode 100644
index 0000000..bfeb9c5
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do
@@ -0,0 +1,65 @@
+# file: simulate_mti.do
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $env(XILINX)/verilog/src/glbl.v
+vlog -work work ../../implement/results/routed.v
+vlog -work work clkmgr_dcm_tb.v
+
+# run the simulation
+vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clkmgr_dcm_tb/dut=../../implement/results/routed.sdf +no_notifier work.clkmgr_dcm_tb work.glbl
+#do wave.do
+#log -r /*
+run 50000ns
+
+
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh
new file mode 100644
index 0000000..b842adc
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh
@@ -0,0 +1,61 @@
+#/bin/sh
+# file: simulate_mti.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vlog -work work $XILINX/verilog/src/glbl.v
+vlog -work work ../../implement/results/routed.v
+vlog -work work clkmgr_dcm_tb.v
+
+# run the simulation
+vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clkmgr_dcm_tb/dut=../../implement/results/routed.sdf +no_notifier work.clkmgr_dcm_tb work.glbl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh
new file mode 100644
index 0000000..fd18dde
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh
@@ -0,0 +1,64 @@
+#!/bin/sh
+# file: simulate_ncsim.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# set up the working directory
+mkdir work
+
+# compile all of the files
+ncvlog -work work ${XILINX}/verilog/src/glbl.v
+ncvlog -work work ../../implement/results/routed.v
+ncvlog -work work clkmgr_dcm_tb.v
+
+# elaborate and run the simulation
+ncsdfc ../../implement/results/routed.sdf
+
+ncelab -work work -access +wc -pulse_r 10 -nonotifier work.clkmgr_dcm_tb work.glbl -sdf_cmd_file sdf_cmd_file
+ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.clkmgr_dcm_tb
+
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh
new file mode 100644
index 0000000..26a8c27
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh
@@ -0,0 +1,72 @@
+#!/bin/sh
+# file: simulate_vcs.sh
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# remove old files
+rm -rf simv* csrc DVEfiles AN.DB
+
+# compile all of the files
+# Note that -sverilog is not strictly required- You can
+# remove the -sverilog if you change the type of the
+# localparam for the periods in the testbench file to
+# [63:0] from time
+ vlogan -sverilog \
+ clkmgr_dcm_tb.v \
+ ../../implement/results/routed.v
+
+
+# prepare the simulation
+vcs -sdf max:clkmgr_dcm_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \
+ +libext+.v -debug clkmgr_dcm_tb.v ../../implement/results/routed.v
+
+# run the simulation
+./simv -ucli -i ucli_commands.key
+
+# launch the viewer
+#dve -vpd vcdplus.vpd -session vcs_session.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key
new file mode 100644
index 0000000..b32669e
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key
@@ -0,0 +1,5 @@
+
+call {$vcdpluson}
+run 50000ns
+call {$vcdplusclose}
+quit
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl
new file mode 100644
index 0000000..6cc6e24
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl
@@ -0,0 +1 @@
+gui_open_window Wave
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/wave.do b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/wave.do
new file mode 100644
index 0000000..7cc804b
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/wave.do
@@ -0,0 +1,71 @@
+# file: wave.do
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /clkmgr_dcm_tb/CLK_IN1
+add wave -noupdate /clkmgr_dcm_tb/COUNT
+add wave -noupdate /clkmgr_dcm_tb/RESET
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {3223025 ps} 0}
+configure wave -namecolwidth 238
+configure wave -valuecolwidth 107
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {74848022 ps}
diff --git a/common/rtl/ipcore/clkmgr_dcm_flist.txt b/common/rtl/ipcore/clkmgr_dcm_flist.txt
new file mode 100644
index 0000000..bd1b2cd
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm_flist.txt
@@ -0,0 +1,54 @@
+# Output products list for <clkmgr_dcm>
+_xmsgs\pn_parser.xmsgs
+clkmgr_dcm.asy
+clkmgr_dcm.gise
+clkmgr_dcm.ucf
+clkmgr_dcm.v
+clkmgr_dcm.veo
+clkmgr_dcm.xco
+clkmgr_dcm.xdc
+clkmgr_dcm.xise
+clkmgr_dcm\clk_wiz_v3_6_readme.txt
+clkmgr_dcm\doc\clk_wiz_v3_6_readme.txt
+clkmgr_dcm\doc\clk_wiz_v3_6_vinfo.html
+clkmgr_dcm\doc\pg065_clk_wiz.pdf
+clkmgr_dcm\example_design\clkmgr_dcm_exdes.ucf
+clkmgr_dcm\example_design\clkmgr_dcm_exdes.v
+clkmgr_dcm\example_design\clkmgr_dcm_exdes.xdc
+clkmgr_dcm\implement\implement.bat
+clkmgr_dcm\implement\implement.sh
+clkmgr_dcm\implement\planAhead_ise.bat
+clkmgr_dcm\implement\planAhead_ise.sh
+clkmgr_dcm\implement\planAhead_ise.tcl
+clkmgr_dcm\implement\planAhead_rdn.bat
+clkmgr_dcm\implement\planAhead_rdn.sh
+clkmgr_dcm\implement\planAhead_rdn.tcl
+clkmgr_dcm\implement\xst.prj
+clkmgr_dcm\implement\xst.scr
+clkmgr_dcm\simulation\clkmgr_dcm_tb.v
+clkmgr_dcm\simulation\functional\simcmds.tcl
+clkmgr_dcm\simulation\functional\simulate_isim.bat
+clkmgr_dcm\simulation\functional\simulate_isim.sh
+clkmgr_dcm\simulation\functional\simulate_mti.bat
+clkmgr_dcm\simulation\functional\simulate_mti.do
+clkmgr_dcm\simulation\functional\simulate_mti.sh
+clkmgr_dcm\simulation\functional\simulate_ncsim.sh
+clkmgr_dcm\simulation\functional\simulate_vcs.sh
+clkmgr_dcm\simulation\functional\ucli_commands.key
+clkmgr_dcm\simulation\functional\vcs_session.tcl
+clkmgr_dcm\simulation\functional\wave.do
+clkmgr_dcm\simulation\functional\wave.sv
+clkmgr_dcm\simulation\timing\clkmgr_dcm_tb.v
+clkmgr_dcm\simulation\timing\sdf_cmd_file
+clkmgr_dcm\simulation\timing\simcmds.tcl
+clkmgr_dcm\simulation\timing\simulate_isim.sh
+clkmgr_dcm\simulation\timing\simulate_mti.bat
+clkmgr_dcm\simulation\timing\simulate_mti.do
+clkmgr_dcm\simulation\timing\simulate_mti.sh
+clkmgr_dcm\simulation\timing\simulate_ncsim.sh
+clkmgr_dcm\simulation\timing\simulate_vcs.sh
+clkmgr_dcm\simulation\timing\ucli_commands.key
+clkmgr_dcm\simulation\timing\vcs_session.tcl
+clkmgr_dcm\simulation\timing\wave.do
+clkmgr_dcm_flist.txt
+clkmgr_dcm_xmdf.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm_xmdf.tcl b/common/rtl/ipcore/clkmgr_dcm_xmdf.tcl
new file mode 100644
index 0000000..307029b
--- /dev/null
+++ b/common/rtl/ipcore/clkmgr_dcm_xmdf.tcl
@@ -0,0 +1,140 @@
+# The package naming convention is <core_name>_xmdf
+package provide clkmgr_dcm_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::clkmgr_dcm_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::clkmgr_dcm_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name clkmgr_dcm
+}
+# ::clkmgr_dcm_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::clkmgr_dcm_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/clk_wiz_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/doc/clk_wiz_ds709.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/doc/clk_wiz_gsg521.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/implement/implement.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/implement/implement.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/implement/xst.prj
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/implement/xst.scr
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/clkmgr_dcm_tb.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/simcmds.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/simulate_isim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/simulate_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/simulate_ncsim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/simulate_vcs.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/ucli_commands.key
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/vcs_session.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/wave.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/wave.sv
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm.ejp
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module clkmgr_dcm
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/common/rtl/ipcore/coregen.cgp b/common/rtl/ipcore/coregen.cgp
new file mode 100644
index 0000000..8bc2e70
--- /dev/null
+++ b/common/rtl/ipcore/coregen.cgp
@@ -0,0 +1,9 @@
+SET busformat = BusFormatAngleBracketNotRipped
+SET designentry = Verilog
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET package = csg324
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
diff --git a/common/rtl/ipcore/create_clkmgr_dcm.tcl b/common/rtl/ipcore/create_clkmgr_dcm.tcl
new file mode 100644
index 0000000..fec8dec
--- /dev/null
+++ b/common/rtl/ipcore/create_clkmgr_dcm.tcl
@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator create command
+##
+
+proc findRtfPath { relativePath } {
+ set xilenv ""
+ if { [info exists ::env(XILINX) ] } {
+ if { [info exists ::env(MYXILINX)] } {
+ set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+ } else {
+ set xilenv $::env(XILINX)
+ }
+ }
+ foreach path [ split $xilenv $::xilinx::path_sep ] {
+ set fullPath [ file join $path $relativePath ]
+ if { [ file exists $fullPath ] } {
+ return $fullPath
+ }
+ }
+ return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_create "xilinx.com:ip:clk_wiz:3.6" "clkmgr_dcm" "Clocking Wizard" "Clocking Wizard (xilinx.com:ip:clk_wiz:3.6) generated by Project Navigator" xc6slx45-3csg324 Verilog ]
+
+if { $result == 0 } {
+ puts "Core Generator create command completed successfully."
+} elseif { $result == 1 } {
+ puts "Core Generator create command failed."
+} elseif { $result == 3 || $result == 4 } {
+ # convert 'version check' result to real return range, bypassing any messages.
+ set result [ expr $result - 3 ]
+} else {
+ puts "Core Generator create cancelled."
+}
+exit $result
diff --git a/common/rtl/ipcore/edit_clkmgr_dcm.tcl b/common/rtl/ipcore/edit_clkmgr_dcm.tcl
new file mode 100644
index 0000000..4992eb1
--- /dev/null
+++ b/common/rtl/ipcore/edit_clkmgr_dcm.tcl
@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator edit command
+##
+
+proc findRtfPath { relativePath } {
+ set xilenv ""
+ if { [info exists ::env(XILINX) ] } {
+ if { [info exists ::env(MYXILINX)] } {
+ set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+ } else {
+ set xilenv $::env(XILINX)
+ }
+ }
+ foreach path [ split $xilenv $::xilinx::path_sep ] {
+ set fullPath [ file join $path $relativePath ]
+ if { [ file exists $fullPath ] } {
+ return $fullPath
+ }
+ }
+ return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_edit "clkmgr_dcm" xc6slx45-3csg324 Verilog ]
+
+if { $result == 0 } {
+ puts "Core Generator edit command completed successfully."
+} elseif { $result == 1 } {
+ puts "Core Generator edit command failed."
+} elseif { $result == 3 || $result == 4 } {
+ # convert 'version check' result to real return range, bypassing any messages.
+ set result [ expr $result - 3 ]
+} else {
+ puts "Core Generator edit cancelled."
+}
+exit $result
diff --git a/common/rtl/novena_clkmgr.v b/common/rtl/novena_clkmgr.v
new file mode 100644
index 0000000..97db451
--- /dev/null
+++ b/common/rtl/novena_clkmgr.v
@@ -0,0 +1,130 @@
+//======================================================================
+//
+// novena_clkmgr.v
+// ---------------
+// Clock and reset implementation for the Cryptech Novena
+// FPGA framework.
+//
+//
+// Author: Pavel Shatov
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module novena_clkmgr
+ (
+ input wire gclk_p, // signal from clock pins
+ input wire gclk_n, //
+
+ input wire reset_mcu_b, // cpu reset (async)
+
+ output wire sys_clk, // buffered system clock output
+ output wire sys_rst // system reset output (sync)
+ );
+
+ //
+ // Ports
+ //
+
+
+ //
+ // IBUFGDS
+ //
+ (* BUFFER_TYPE="NONE" *)
+ wire gclk;
+
+ IBUFGDS IBUFGDS_gclk
+ (
+ .I(gclk_p),
+ .IB(gclk_n),
+ .O(gclk)
+ );
+
+
+ //
+ // DCM
+ //
+ wire dcm_reset; // dcm reset
+ wire dcm_locked; // output clock valid
+ wire gclk_missing; // no input clock
+
+ clkmgr_dcm dcm
+ (
+ .CLK_IN1(gclk),
+ .RESET(dcm_reset),
+ .INPUT_CLK_STOPPED(gclk_missing),
+
+ .CLK_OUT1(sys_clk),
+ .CLK_VALID(dcm_locked)
+ );
+
+
+ //
+ // DCM Reset Logic
+ //
+
+ /* DCM should be reset on power-up, when input clock is stopped or when the
+ * CPU gets reset.
+ */
+
+ reg [15: 0] dcm_rst_shreg = {16{1'b1}}; // 16-bit shift register
+
+ always @(posedge gclk or negedge reset_mcu_b or posedge gclk_missing)
+ //
+ if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1))
+ dcm_rst_shreg <= {16{1'b1}};
+ else
+ dcm_rst_shreg <= {dcm_rst_shreg[14:0], 1'b0};
+
+ assign dcm_reset = dcm_rst_shreg[15];
+
+
+ //
+ // System Reset Logic
+ //
+
+ /* System reset is asserted for 16 cycles whenever DCM aquires lock. */
+
+ reg [15: 0] sys_rst_shreg = {16{1'b1}}; // 16-bit shift register
+
+ always @(posedge sys_clk or negedge reset_mcu_b or posedge gclk_missing or negedge dcm_locked)
+ //
+ if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1) || (dcm_locked == 1'b0))
+ sys_rst_shreg <= {16{1'b1}};
+ else if (dcm_locked == 1'b1)
+ sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b0};
+
+ assign sys_rst = sys_rst_shreg[15];
+
+
+endmodule
+
+//======================================================================
+// EOF novena_clkmgr.v
+//======================================================================