diff options
| -rwxr-xr-x | config/config.py | 27 | ||||
| -rw-r--r-- | eim/build/Makefile | 25 |
2 files changed, 35 insertions, 17 deletions
diff --git a/config/config.py b/config/config.py index 65c540f..ddf7d0b 100755 --- a/config/config.py +++ b/config/config.py @@ -111,7 +111,18 @@ class Core(object): return createMux_template.format(core = self, core0 = self) def listVfiles(self): - return "".join(" \\\n\t$(core_tree)/" + vfile for vfile in self.vfiles) + return "".join(" \\\n\t$(CORE_TREE)/" + vfile for vfile in self.vfiles) + + +class BoardCore(Core): + """ + Board-level cores have a slightly different API, which we handle + with a different template, at least for now. + """ + + def createInstance(self): + return createInstance_template_board.format(core = self) + class SubCore(Core): """" @@ -126,16 +137,6 @@ class SubCore(Core): return createMux_template.format(core = self, core0 = self.parent) -class BoardCore(Core): - """ - Board-level cores have a slightly different API, which we handle - with a different template. - """ - - def createInstance(self): - return createInstance_template_board.format(core = self) - - class TRNGCore(Core): """ The TRNG core has an internal mux and a collection of sub-cores. @@ -144,9 +145,11 @@ class TRNGCore(Core): a different instance template in the hope that it is easier to read. """ + subcore_names = ("avalanche_entropy", "rosc_entropy", "trng_mixer", "trng_csprng") + def __init__(self, name): super(TRNGCore, self).__init__(name) - self.subcores = tuple(SubCore(name, self) for name in ("avalanche_entropy", "rosc_entropy", "trng_mixer", "trng_csprng")) + self.subcores = tuple(SubCore(name, self) for name in self.subcore_names) def assign_core_number(self, n): n = super(TRNGCore, self).assign_core_number(n) diff --git a/eim/build/Makefile b/eim/build/Makefile index baefa7f..00d8604 100644 --- a/eim/build/Makefile +++ b/eim/build/Makefile @@ -1,6 +1,13 @@ -core_tree := $(abspath ../../../..) +# Localize all the relative path awfulness in one variable. -word_size := $(shell python -c 'from struct import pack; print len(pack("L", 0)) * 8') +CORE_TREE := $(abspath ../../../..) + +# Figure out what the native word size is on the build host, because +# the XiLinx tools care for some reason. + +WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0)) * 8') + +# Parameters to xilinkx.mk. project = novena_eim vendor = xilinx @@ -8,8 +15,10 @@ family = spartan6 part = xc6slx45csg324-3 top_module = novena_top isedir = /opt/Xilinx/14.7/ISE_DS -xil_env = . $(isedir)/settings$(word_size).sh -ucf = ../ucf/novena_eim.ucf +xil_env = . $(isedir)/settings$(WORD_SIZE).sh +ucf = ../ucf/$(project).ucf + +# Verilog files that always go with builds on this platform. vfiles = \ $(core_tree)/platform/novena/eim/rtl/novena_eim.v \ @@ -25,9 +34,15 @@ vfiles = \ $(core_tree)/comm/eim/src/rtl/eim_regs.v \ $(core_tree)/comm/eim/src/rtl/eim.v +# Verilog files selected by the core configuration script. + include $(core_tree)/platform/novena/config/core_vfiles.mk include xilinx.mk +# Fun extras for running verlator as a linter. + +VERILATOR_FLAGS = --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME + lint: - verilator --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME $(vfiles) ../../common/rtl/lint-dummy.v + verilator ${VERILATOR_FLAGS} $(vfiles) $(core_tree)/platform/novena/common/rtl/lint-dummy.v |