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-rw-r--r--common/rtl/novena_regs.v18
-rw-r--r--eim/build/Makefile1
-rw-r--r--eim/rtl/novena_eim.v32
-rw-r--r--i2c/iseconfig/novena_i2c.xise90
-rw-r--r--i2c/rtl/novena_i2c.v24
5 files changed, 107 insertions, 58 deletions
diff --git a/common/rtl/novena_regs.v b/common/rtl/novena_regs.v
index 716f650..eb89092 100644
--- a/common/rtl/novena_regs.v
+++ b/common/rtl/novena_regs.v
@@ -40,15 +40,19 @@
module board_regs
(
+ // Clock and reset.
input wire clk,
input wire rst,
+ // Control.
input wire cs,
input wire we,
- input wire [ 7 : 0] address,
+ // Data ports.
+ input wire [7 : 0] address,
input wire [31 : 0] write_data,
- output wire [31 : 0] read_data
+ output wire [31 : 0] read_data,
+ output wire error
);
@@ -70,6 +74,8 @@ module board_regs
// Registers.
//----------------------------------------------------------------
reg [31: 0] tmp_read_data;
+ reg write_error;
+ reg read_error;
// dummy register to check that you can actually write something
reg [31: 0] reg_dummy;
@@ -85,6 +91,7 @@ module board_regs
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
+ assign error = write_error | read_error;
//----------------------------------------------------------------
// storage registers for mapping memory to core interface
@@ -97,10 +104,14 @@ module board_regs
end
else if (cs && we)
begin
+ write_error <= 0;
+
// write operations
case (address)
ADDR_DUMMY_REG:
reg_dummy <= write_data;
+ default:
+ write_error <= 1;
endcase
end
end
@@ -108,6 +119,7 @@ module board_regs
always @*
begin
tmp_read_data = 32'h00000000;
+ read_error = 0;
if (cs && !we)
begin
@@ -121,6 +133,8 @@ module board_regs
tmp_read_data = core_version;
ADDR_DUMMY_REG:
tmp_read_data = reg_dummy;
+ default:
+ read_error = 1;
endcase
end
end
diff --git a/eim/build/Makefile b/eim/build/Makefile
index 5ef3e7e..70f9f84 100644
--- a/eim/build/Makefile
+++ b/eim/build/Makefile
@@ -14,7 +14,6 @@ vfiles = \
../../common/rtl/ipcore/clkmgr_dcm.v \
../../../common/core_selector/src/rtl/core_selector.v \
../../../common/core_selector/src/rtl/global_selector.v \
- ../../../common/core_selector/src/rtl/cipher_selector.v \
../../../common/core_selector/src/rtl/hash_selector.v \
../../../common/core_selector/src/rtl/rng_selector.v \
../../../../comm/eim/src/rtl/cdc_bus_pulse.v \
diff --git a/eim/rtl/novena_eim.v b/eim/rtl/novena_eim.v
index 71b64a9..0d8c8d0 100644
--- a/eim/rtl/novena_eim.v
+++ b/eim/rtl/novena_eim.v
@@ -41,30 +41,30 @@
module novena_top
(
// Differential input for 50 MHz general clock.
- input wire gclk_p_pin,
- input wire gclk_n_pin,
+ input wire gclk_p_pin,
+ input wire gclk_n_pin,
// Reset controlled by the CPU.
// this must be configured as input w/pullup
- input wire reset_mcu_b_pin,
+ input wire reset_mcu_b_pin,
// Cryptech avalanche noise board input and LED outputs
- input wire ct_noise,
+ input wire ct_noise,
output wire [7 : 0] ct_led,
// EIM interface
- input wire eim_bclk, // EIM burst clock. Started by the CPU.
- input wire eim_cs0_n, // Chip select (active low).
- inout wire [15 : 0] eim_da, // Bidirectional address and data port.
- input wire [18: 16] eim_a, // MSB part of address port.
- input wire eim_lba_n, // Latch address signal (active low).
- input wire eim_wr_n, // write enable signal (active low).
- input wire eim_oe_n, // output enable signal (active low).
- output wire eim_wait_n, // Data wait signal (active low).
+ input wire eim_bclk, // EIM burst clock. Started by the CPU.
+ input wire eim_cs0_n, // Chip select (active low).
+ inout wire [15 : 0] eim_da, // Bidirectional address and data port.
+ input wire [18: 16] eim_a, // MSB part of address port.
+ input wire eim_lba_n, // Latch address signal (active low).
+ input wire eim_wr_n, // write enable signal (active low).
+ input wire eim_oe_n, // output enable signal (active low).
+ output wire eim_wait_n, // Data wait signal (active low).
// Novena utility ports
- output wire apoptosis_pin, // Hold low to not restart after config.
- output wire led_pin // LED on edge close to the FPGA.
+ output wire apoptosis_pin, // Hold low to not restart after config.
+ output wire led_pin // LED on edge close to the FPGA.
);
@@ -156,15 +156,13 @@ module novena_top
.sys_clk(sys_clk),
.sys_rst(sys_rst),
- .noise(ct_noise),
-
.sys_eim_addr(sys_eim_addr),
.sys_eim_wr(sys_eim_wr),
.sys_eim_rd(sys_eim_rd),
-
.sys_write_data(sys_eim_dout),
.sys_read_data(tmp_read_data),
+ .noise(ct_noise),
.debug(ct_led)
);
diff --git a/i2c/iseconfig/novena_i2c.xise b/i2c/iseconfig/novena_i2c.xise
index 934ca05..fe2f4e1 100644
--- a/i2c/iseconfig/novena_i2c.xise
+++ b/i2c/iseconfig/novena_i2c.xise
@@ -17,103 +17,147 @@
<files>
<file xil_pn:name="../rtl/novena_i2c.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../common/rtl/novena_regs.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../common/rtl/novena_clkmgr.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../common/rtl/ipcore/clkmgr_dcm.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../ucf/novena_i2c.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../common/core_selector/src/rtl/core_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../../common/core_selector/src/rtl/global_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../../common/core_selector/src/rtl/cipher_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../../common/core_selector/src/rtl/hash_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../../common/core_selector/src/rtl/rng_selector.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../../../comm/coretest/src/rtl/coretest.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../../../comm/i2c/src/rtl/i2c_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../../../hash/sha1/src/rtl/sha1_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../../../hash/sha1/src/rtl/sha1_w_mem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../../../hash/sha1/src/rtl/sha1.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../../../hash/sha256/src/rtl/sha256_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../../../hash/sha256/src/rtl/sha256_k_constants.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../../../hash/sha256/src/rtl/sha256_w_mem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../../../hash/sha256/src/rtl/sha256.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_h_constants.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_k_constants.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_w_mem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../../hash/sha512/src/rtl/sha512.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../../../comm/i2c/src/rtl/i2c_regs.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+ </file>
+ <file xil_pn:name="../../../../rng/trng/src/rtl/trng.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+ </file>
+ <file xil_pn:name="../../../../rng/trng/src/rtl/trng_csprng_fifo.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+ </file>
+ <file xil_pn:name="../../../../rng/trng/src/rtl/trng_csprng.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+ </file>
+ <file xil_pn:name="../../../../rng/trng/src/rtl/trng_mixer.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
+ <file xil_pn:name="../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+ </file>
+ <file xil_pn:name="../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+ </file>
+ <file xil_pn:name="../../../../rng/rosc_entropy/src/rtl/rosc_entropy_core.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+ </file>
+ <file xil_pn:name="../../../../rng/rosc_entropy/src/rtl/rosc_entropy.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+ </file>
+ <file xil_pn:name="../../../../rng/rosc_entropy/src/rtl/rosc.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+ </file>
+ <file xil_pn:name="../../../../cipher/chacha/src/rtl/chacha_core.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+ </file>
+ <file xil_pn:name="../../../../cipher/chacha/src/rtl/chacha_qr.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+ </file>
</files>
<properties>
diff --git a/i2c/rtl/novena_i2c.v b/i2c/rtl/novena_i2c.v
index ade0bc2..d1833b2 100644
--- a/i2c/rtl/novena_i2c.v
+++ b/i2c/rtl/novena_i2c.v
@@ -55,7 +55,7 @@ module novena_top
inout wire i2c_sda,
// Novena utility ports
- output wire apoptosis_pin, // Hold low to not restart after config.
+ output wire apoptosis_pin, // Hold low to not restart after config.
output wire led_pin // LED on edge close to the FPGA.
);
@@ -105,6 +105,7 @@ module novena_top
wire [15 : 0] coretest_address;
wire [31 : 0] coretest_write_data;
wire [31 : 0] coretest_read_data;
+ wire coretest_error;
// I2C connections
wire [6:0] i2c_device_addr;
@@ -164,7 +165,8 @@ module novena_top
.core_we(coretest_we),
.core_address(coretest_address),
.core_write_data(coretest_write_data),
- .core_read_data(coretest_read_data)
+ .core_read_data(coretest_read_data),
+ .core_error(coretest_error)
);
wire select = (i2c_device_addr == I2C_DEVICE_ADDR);
@@ -184,24 +186,16 @@ module novena_top
.sys_clk(clk),
.sys_rst(sys_rst),
- .noise(ct_noise),
-
.sys_eim_addr(sys_eim_addr),
.sys_eim_wr(sys_eim_wr),
.sys_eim_rd(sys_eim_rd),
-
.sys_write_data(coretest_write_data),
- .sys_read_data(coretest_read_data)
- );
-
+ .sys_read_data(coretest_read_data),
+ .sys_error(coretest_error),
- //----------------------------------------------------------------
- // Cryptech Logic
- //
- // Logic specific to the Cryptech use of the Novena.
- // Currently we just hard wire the LED outputs.
- //----------------------------------------------------------------
- assign ct_led = {8{ct_noise}};
+ .noise(ct_noise),
+ .debug(ct_led)
+ );
//----------------------------------------------------------------
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 01:59:07 +0000