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authorPaul Selkirk <paul@psgd.org>2015-11-13 17:03:52 -0500
committerPaul Selkirk <paul@psgd.org>2015-11-13 17:03:52 -0500
commitb1e661bf4f8a715743222977067c1cf560408b40 (patch)
treedbda524f94b591a9952577303f768f96f8d5ae88 /i2c/build/Makefile
parent5ad8554e49ed204ffe5242493b16d7735cadb4e6 (diff)
parent47508ec70ea2c85cb1541b1c3a214439357ad735 (diff)
Merge branch 'config_core_selector'
Diffstat (limited to 'i2c/build/Makefile')
-rw-r--r--i2c/build/Makefile102
1 files changed, 38 insertions, 64 deletions
diff --git a/i2c/build/Makefile b/i2c/build/Makefile
index 1859da3..441b67a 100644
--- a/i2c/build/Makefile
+++ b/i2c/build/Makefile
@@ -1,70 +1,44 @@
-project = novena_i2c
-vendor = xilinx
-family = spartan6
-part = xc6slx45csg324-3
-top_module = novena_top
-isedir = /opt/Xilinx/14.7/ISE_DS
-xil_env = . $(isedir)/settings64.sh
-ucf = ../ucf/novena_i2c.ucf
+# Localize all the relative path awfulness in one variable.
+
+CORE_TREE := $(abspath ../../../..)
+
+# Figure out what the native word size is on the build host, because
+# the XiLinx tools care for some reason.
+
+WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0)) * 8')
+
+# Parameters to xilinx.mk.
+
+project = novena_eim
+vendor = xilinx
+family = spartan6
+part = xc6slx45csg324-3
+top_module = novena_top
+isedir = /opt/Xilinx/14.7/ISE_DS
+xil_env = . $(isedir)/settings$(WORD_SIZE).sh
+ucf = ../ucf/$(project).ucf
+
+# Verilog files that always go with builds on this platform.
vfiles = \
- ../rtl/novena_i2c.v \
- ../../common/rtl/novena_regs.v \
- ../../common/rtl/novena_clkmgr.v \
- ../../common/rtl/ipcore/clkmgr_dcm.v \
- ../../../common/core_selector/src/rtl/core_selector.v \
- ../../../common/core_selector/src/rtl/global_selector.v \
- ../../../common/core_selector/src/rtl/hash_selector.v \
- ../../../common/core_selector/src/rtl/rng_selector.v \
- ../../../common/core_selector/src/rtl/cipher_selector.v \
- ../../../common/core_selector/src/rtl/math_selector.v \
- ../../../../comm/i2c/src/rtl/i2c_regs.v \
- ../../../../comm/i2c/src/rtl/i2c_core.v \
- ../../../../comm/coretest/src/rtl/coretest.v \
- ../../../../hash/sha1/src/rtl/sha1.v \
- ../../../../hash/sha1/src/rtl/sha1_core.v \
- ../../../../hash/sha1/src/rtl/sha1_w_mem.v \
- ../../../../hash/sha256/src/rtl/sha256.v \
- ../../../../hash/sha256/src/rtl/sha256_core.v \
- ../../../../hash/sha256/src/rtl/sha256_k_constants.v \
- ../../../../hash/sha256/src/rtl/sha256_w_mem.v \
- ../../../../hash/sha512/src/rtl/sha512.v \
- ../../../../hash/sha512/src/rtl/sha512_core.v \
- ../../../../hash/sha512/src/rtl/sha512_h_constants.v \
- ../../../../hash/sha512/src/rtl/sha512_k_constants.v \
- ../../../../hash/sha512/src/rtl/sha512_w_mem.v \
- ../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy.v \
- ../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v \
- ../../../../rng/rosc_entropy/src/rtl/rosc.v \
- ../../../../rng/rosc_entropy/src/rtl/rosc_entropy.v \
- ../../../../rng/rosc_entropy/src/rtl/rosc_entropy_core.v \
- ../../../../rng/trng/src/rtl/trng.v \
- ../../../../rng/trng/src/rtl/trng_csprng.v \
- ../../../../rng/trng/src/rtl/trng_csprng_fifo.v \
- ../../../../rng/trng/src/rtl/trng_mixer.v \
- ../../../../cipher/aes/src/rtl/aes.v \
- ../../../../cipher/aes/src/rtl/aes_core.v \
- ../../../../cipher/aes/src/rtl/aes_decipher_block.v \
- ../../../../cipher/aes/src/rtl/aes_encipher_block.v \
- ../../../../cipher/aes/src/rtl/aes_inv_sbox.v \
- ../../../../cipher/aes/src/rtl/aes_key_mem.v \
- ../../../../cipher/aes/src/rtl/aes_sbox.v \
- ../../../../cipher/chacha/src/rtl/chacha.v \
- ../../../../cipher/chacha/src/rtl/chacha_core.v \
- ../../../../cipher/chacha/src/rtl/chacha_qr.v \
- ../../../../math/modexp/src/rtl/adder32.v \
- ../../../../math/modexp/src/rtl/blockmem1r1w.v \
- ../../../../math/modexp/src/rtl/blockmem2r1wptr.v \
- ../../../../math/modexp/src/rtl/blockmem2r1w.v \
- ../../../../math/modexp/src/rtl/blockmem2rptr1w.v \
- ../../../../math/modexp/src/rtl/modexp.v \
- ../../../../math/modexp/src/rtl/modexp_core.v \
- ../../../../math/modexp/src/rtl/montprod.v \
- ../../../../math/modexp/src/rtl/residue.v \
- ../../../../math/modexp/src/rtl/shl32.v \
- ../../../../math/modexp/src/rtl/shr32.v
+ $(CORE_TREE)/platform/novena/i2c/rtl/novena_i2c.v \
+ $(CORE_TREE)/platform/novena/common/rtl/novena_regs.v \
+ $(CORE_TREE)/platform/novena/common/rtl/novena_clkmgr.v \
+ $(CORE_TREE)/platform/novena/common/rtl/clkmgr_dcm.v \
+ $(CORE_TREE)/platform/novena/config/core_selector.v \
+ $(CORE_TREE)/comm/i2c/src/rtl/i2c_regs.v \
+ $(CORE_TREE)/comm/i2c/src/rtl/i2c_core.v \
+ $(CORE_TREE)/comm/coretest/src/rtl/coretest.v
+
+# Verilog files selected by the core configuration script.
+
+-include $(CORE_TREE)/platform/novena/config/core_vfiles.mk
include xilinx.mk
+# Fun extras for running verlator as a linter.
+
+VERILATOR_FLAGS = --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME
+
lint:
- verilator --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME $(vfiles) ../../common/rtl/lint-dummy.v
+ verilator ${VERILATOR_FLAGS} $(vfiles) $(CORE_TREE)/platform/novena/common/rtl/lint-dummy.v