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authorPaul Selkirk <paul@psgd.org>2015-11-18 18:55:59 -0500
committerPaul Selkirk <paul@psgd.org>2015-11-18 18:55:59 -0500
commita4737cc9305cbab9bb9c044fad48d75dff37568c (patch)
tree38a0e062a67d0086b4b12e0c25612fbdbdb546e3 /fmc/build/Makefile
parent81286a692a3edade788c6d42beec1a7c8e5e07c9 (diff)
Move core_selector config script to core/platform/common, generate project-specific core_selectors in the build directories.
Diffstat (limited to 'fmc/build/Makefile')
-rw-r--r--fmc/build/Makefile47
1 files changed, 41 insertions, 6 deletions
diff --git a/fmc/build/Makefile b/fmc/build/Makefile
index 1b81656..a7e8755 100644
--- a/fmc/build/Makefile
+++ b/fmc/build/Makefile
@@ -9,14 +9,40 @@ WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0))
# Parameters to xilinx.mk.
-project = novena_fmc
+project ?= novena_fmc
vendor = xilinx
family = spartan6
part = xc6slx45csg324-3
top_module = novena_fmc_top
isedir = /opt/Xilinx/14.7/ISE_DS
xil_env = . $(isedir)/settings$(WORD_SIZE).sh
-ucf = ../ucf/$(project).ucf
+ucf ?= ../ucf/$(project).ucf
+
+all: $(project).bit
+
+# Build the default core_selector if it doesn't already exist.
+
+CONFIG = $(CORE_TREE)/platform/common/config
+core_selector.v core_vfiles.mk:
+ $(CONFIG)/config.py -c $(CONFIG)/config.cfg
+
+# Build some different configurations
+
+bare:
+ $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s bare
+ $(MAKE) project=$(project)_bare ucf=$(ucf)
+
+trng:
+ $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s trng
+ $(MAKE) project=$(project)_trng ucf=$(ucf)
+
+hash:
+ $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s hash
+ $(MAKE) project=$(project)_hash ucf=$(ucf)
+
+rsa:
+ $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s rsa
+ $(MAKE) project=$(project)_rsa ucf=$(ucf)
# Verilog files that always go with builds on this platform.
@@ -25,7 +51,7 @@ vfiles = \
$(CORE_TREE)/platform/novena/common/rtl/novena_regs.v \
$(CORE_TREE)/platform/novena/common/rtl/novena_clkmgr.v \
$(CORE_TREE)/platform/novena/common/rtl/clkmgr_dcm.v \
- $(CORE_TREE)/platform/novena/config/core_selector.v \
+ ./core_selector.v \
$(CORE_TREE)/comm/fmc/src/rtl/cdc_bus_pulse.v \
$(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter_cdc.v \
$(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter.v \
@@ -35,13 +61,22 @@ vfiles = \
# Verilog files selected by the core configuration script.
--include $(CORE_TREE)/platform/novena/config/core_vfiles.mk
+-include ./core_vfiles.mk
include xilinx.mk
-# Fun extras for running verlator as a linter.
+# 'clean' target collects files by project name, and we just broke that
+
+junk += *.bgn *.bit *.bld *.cfi *.drc *.lso *.map *.mcs *.mrp *.ncd *.ngc \
+ *.ngd *.ngm *.pcf *.post_map.twr *.post_map.twx *.prj *.prm *.psr \
+ *.scr *.srp *.twr *.twx *_bd.bmm *_bitgen.xwb *_bitgen.xwbt \
+ *_err.twr *_err.twx *_par.grf *_par.ncd *_par.pad *_par.par \
+ *_par.ptwx *_par.unroutes *_par.xpi *_par_pad.csv *_par_pad.txt \
+ *_summary.xml *_usage.xml
+
+# Fun extras for running verilator as a linter.
-VERILATOR_FLAGS = --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME
+VERILATOR_FLAGS = --lint-only --top-module $(top_module) -Wall -Wno-fatal -Wno-DECLFILENAME
lint:
verilator ${VERILATOR_FLAGS} $(vfiles) $(CORE_TREE)/platform/novena/common/rtl/lint-dummy.v