Unify and refactor eim and i2c software.

Unify memory maps.
Move tc_init, tc_next, tc_wait_* into tc_[eim|i2c].c.
Move eim_setup into tc_eim.c, move i2c_open into tc_i2c.c.

7 files changed, 148 insertions, 155 deletions

diff --git a/eim/sw/cryptech_memory_map.h b/eim/sw/cryptech_memory_map.h
index c70e69c..5cf7f42 100644
--- a/eim/sw/cryptech_memory_map.h
+++ b/eim/sw/cryptech_memory_map.h
@@ -5,7 +5,7 @@
 // The memory map for Cryptech cores.
 //
 //
-// Author: Joachim Strombergson
+// Authors: Joachim Strombergson, Paul Selkirk
 // Copyright (c) 2015, NORDUnet A/S All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -36,35 +36,48 @@
 //
 //======================================================================
 
-// Include platform header and define base address based on platform.
-#include "novena-eim.h"
-#define CT_BASE_ADDR EIM_BASE_ADDR
+// BASE_ADDR, SEGMENT_SIZE, and ADDR are defined in tc_[eim|i2c].h,
+// which #includes this file.
 
+// default definitions from i2c, because defaults are good
+#ifndef BASE_ADDR
+#define BASE_ADDR               0
+#endif
+#ifndef SEGMENT_SIZE
+#define SEGMENT_SIZE            0x2000
+#endif
+#ifndef ADDR
+#define ADDR(x)                 (x)
+#endif
+
+#ifndef bitsToBytes
+#define bitsToBytes(x)          (x / 8)
+#endif
 
 // Segments.
-#define SEGMENT_OFFSET_GLOBALS  EIM_BASE_ADDR + 0x000000
-#define SEGMENT_OFFSET_HASHES   EIM_BASE_ADDR + 0x010000
-#define SEGMENT_OFFSET_RNGS     EIM_BASE_ADDR + 0x020000
-#define SEGMENT_OFFSET_CIPHERS  EIM_BASE_ADDR + 0x030000
+#define SEGMENT_OFFSET_GLOBALS  BASE_ADDR + (0 * SEGMENT_SIZE)
+#define SEGMENT_OFFSET_HASHES   BASE_ADDR + (1 * SEGMENT_SIZE)
+#define SEGMENT_OFFSET_RNGS     BASE_ADDR + (2 * SEGMENT_SIZE)
+#define SEGMENT_OFFSET_CIPHERS  BASE_ADDR + (3 * SEGMENT_SIZE)
 
 
 // addresses and codes common to all cores
-#define ADDR_NAME0              (0x00 << 2)
-#define ADDR_NAME1              (0x01 << 2)
-#define ADDR_VERSION            (0x02 << 2)
+#define ADDR_NAME0              ADDR(0x00)
+#define ADDR_NAME1              ADDR(0x01)
+#define ADDR_VERSION            ADDR(0x02)
 
 
 //------------------------------------------------------------------
 // Board segment.
 // Board-level registers and communication channel registers
 //------------------------------------------------------------------
-#define BOARD_CORE_SIZE         (0x100 << 2)
+#define BOARD_CORE_SIZE         ADDR(0x100)
 
 #define BOARD_ADDR_BASE         SEGMENT_OFFSET_GLOBALS + (0 * BOARD_CORE_SIZE)
 #define BOARD_ADDR_NAME0        BOARD_ADDR_BASE + ADDR_NAME0
 #define BOARD_ADDR_NAME1        BOARD_ADDR_BASE + ADDR_NAME1
 #define BOARD_ADDR_VERSION      BOARD_ADDR_BASE + ADDR_VERSION
-#define BOARD_ADDR_DUMMY        BOARD_ADDR_BASE + (0xFF << 2)
+#define BOARD_ADDR_DUMMY        BOARD_ADDR_BASE + ADDR(0xFF)
 
 #define COMM_ADDR_BASE          SEGMENT_OFFSET_GLOBALS + (1 * BOARD_CORE_SIZE)
 #define COMM_ADDR_NAME0         COMM_ADDR_BASE + ADDR_NAME0
@@ -75,17 +88,17 @@
 //------------------------------------------------------------------
 // Hashes segment.
 //------------------------------------------------------------------
-#define HASH_CORE_SIZE          (0x100 << 2)
+#define HASH_CORE_SIZE          ADDR(0x100)
 
 // addresses and codes common to all hash cores */
-#define ADDR_CTRL               (0x8 << 2)
+#define ADDR_CTRL               ADDR(0x8)
 #define CTRL_INIT_CMD           1
 #define CTRL_NEXT_CMD           2
-#define ADDR_STATUS             (9 << 2)
+#define ADDR_STATUS             ADDR(0x9)
 #define STATUS_READY_BIT        1
 #define STATUS_VALID_BIT        2
-#define ADDR_BLOCK              (0x10 << 2)
-#define ADDR_DIGEST             (0x20 << 2)    // except SHA512
+#define ADDR_BLOCK              ADDR(0x10)
+#define ADDR_DIGEST             ADDR(0x20)      // except SHA512
 
 // addresses and codes for the specific hash cores.
 #define SHA1_ADDR_BASE          SEGMENT_OFFSET_HASHES + (0 * HASH_CORE_SIZE)
@@ -96,8 +109,9 @@
 #define SHA1_ADDR_STATUS        SHA1_ADDR_BASE + ADDR_STATUS
 #define SHA1_ADDR_BLOCK         SHA1_ADDR_BASE + ADDR_BLOCK
 #define SHA1_ADDR_DIGEST        SHA1_ADDR_BASE + ADDR_DIGEST
-#define SHA1_BLOCK_LEN          512 / 8
-#define SHA1_DIGEST_LEN         160 / 8
+#define SHA1_BLOCK_LEN          bitsToBytes(512)
+#define SHA1_LENGTH_LEN         bitsToBytes(64)
+#define SHA1_DIGEST_LEN         bitsToBytes(160)
 
 #define SHA256_ADDR_BASE        SEGMENT_OFFSET_HASHES + (1 * HASH_CORE_SIZE)
 #define SHA256_ADDR_NAME0       SHA256_ADDR_BASE + ADDR_NAME0
@@ -107,8 +121,9 @@
 #define SHA256_ADDR_STATUS      SHA256_ADDR_BASE + ADDR_STATUS
 #define SHA256_ADDR_BLOCK       SHA256_ADDR_BASE + ADDR_BLOCK
 #define SHA256_ADDR_DIGEST      SHA256_ADDR_BASE + ADDR_DIGEST
-#define SHA256_BLOCK_LEN        512 / 8
-#define SHA256_DIGEST_LEN       256 / 8
+#define SHA256_BLOCK_LEN        bitsToBytes(512)
+#define SHA256_LENGTH_LEN       bitsToBytes(64)
+#define SHA256_DIGEST_LEN       bitsToBytes(256)
 
 #define SHA512_ADDR_BASE        SEGMENT_OFFSET_HASHES + (2 * HASH_CORE_SIZE)
 #define SHA512_ADDR_NAME0       SHA512_ADDR_BASE + ADDR_NAME0
@@ -117,12 +132,13 @@
 #define SHA512_ADDR_CTRL        SHA512_ADDR_BASE + ADDR_CTRL
 #define SHA512_ADDR_STATUS      SHA512_ADDR_BASE + ADDR_STATUS
 #define SHA512_ADDR_BLOCK       SHA512_ADDR_BASE + ADDR_BLOCK
-#define SHA512_ADDR_DIGEST      SHA512_ADDR_BASE + (0x40 << 2)
-#define SHA512_BLOCK_LEN        1024 / 8
-#define SHA512_224_DIGEST_LEN   224 / 8
-#define SHA512_256_DIGEST_LEN   256 / 8
-#define SHA384_DIGEST_LEN       384 / 8
-#define SHA512_DIGEST_LEN       512 / 8
+#define SHA512_ADDR_DIGEST      SHA512_ADDR_BASE + ADDR(0x40)
+#define SHA512_BLOCK_LEN        bitsToBytes(1024)
+#define SHA512_LENGTH_LEN       bitsToBytes(128)
+#define SHA512_224_DIGEST_LEN   bitsToBytes(224)
+#define SHA512_256_DIGEST_LEN   bitsToBytes(256)
+#define SHA384_DIGEST_LEN       bitsToBytes(384)
+#define SHA512_DIGEST_LEN       bitsToBytes(512)
 #define MODE_SHA_512_224        0 << 2
 #define MODE_SHA_512_256        1 << 2
 #define MODE_SHA_384            2 << 2
@@ -132,69 +148,69 @@
 // -----------------------------------------------------------------
 // TRNG segment.
 // -----------------------------------------------------------------
-#define TRNG_CORE_SIZE               (0x100 << 2)
+#define TRNG_CORE_SIZE          ADDR(0x100)
 
 // addresses and codes for the TRNG cores */
 #define TRNG_ADDR_BASE          SEGMENT_OFFSET_RNGS + (0 * TRNG_CORE_SIZE)
 #define TRNG_ADDR_NAME0         TRNG_ADDR_BASE + ADDR_NAME0
 #define TRNG_ADDR_NAME1         TRNG_ADDR_BASE + ADDR_NAME1
 #define TRNG_ADDR_VERSION       TRNG_ADDR_BASE + ADDR_VERSION
-#define TRNG_ADDR_CTRL          TRNG_ADDR_BASE + (0x10 << 2)
+#define TRNG_ADDR_CTRL          TRNG_ADDR_BASE + ADDR(0x10)
 #define TRNG_CTRL_DISCARD       1
 #define TRNG_CTRL_TEST_MODE     2
-#define TRNG_ADDR_STATUS        TRNG_ADDR_BASE + (0x11 << 2)
+#define TRNG_ADDR_STATUS        TRNG_ADDR_BASE + ADDR(0x11)
 // no status bits defined (yet)
-#define TRNG_ADDR_DELAY         TRNG_ADDR_BASE + (0x13 << 2)
+#define TRNG_ADDR_DELAY         TRNG_ADDR_BASE + ADDR(0x13)
 
 #define ENTROPY1_ADDR_BASE      SEGMENT_OFFSET_RNGS + (5 * TRNG_CORE_SIZE)
 #define ENTROPY1_ADDR_NAME0     ENTROPY1_ADDR_BASE + ADDR_NAME0
 #define ENTROPY1_ADDR_NAME1     ENTROPY1_ADDR_BASE + ADDR_NAME1
 #define ENTROPY1_ADDR_VERSION   ENTROPY1_ADDR_BASE + ADDR_VERSION
-#define ENTROPY1_ADDR_CTRL      ENTROPY1_ADDR_BASE + (0x10 << 2)
+#define ENTROPY1_ADDR_CTRL      ENTROPY1_ADDR_BASE + ADDR(0x10)
 #define ENTROPY1_CTRL_ENABLE    1
-#define ENTROPY1_ADDR_STATUS    ENTROPY1_ADDR_BASE + (0x11 << 2)
+#define ENTROPY1_ADDR_STATUS    ENTROPY1_ADDR_BASE + ADDR(0x11)
 #define ENTROPY1_STATUS_VALID   1
-#define ENTROPY1_ADDR_ENTROPY   ENTROPY1_ADDR_BASE + (0x20 << 2)
-#define ENTROPY1_ADDR_DELTA     ENTROPY1_ADDR_BASE + (0x30 << 2)
+#define ENTROPY1_ADDR_ENTROPY   ENTROPY1_ADDR_BASE + ADDR(0x20)
+#define ENTROPY1_ADDR_DELTA     ENTROPY1_ADDR_BASE + ADDR(0x30)
 
 #define ENTROPY2_ADDR_BASE      SEGMENT_OFFSET_RNGS + (6 * TRNG_CORE_SIZE)
 #define ENTROPY2_ADDR_NAME0     ENTROPY2_ADDR_BASE + ADDR_NAME0
 #define ENTROPY2_ADDR_NAME1     ENTROPY2_ADDR_BASE + ADDR_NAME1
 #define ENTROPY2_ADDR_VERSION   ENTROPY2_ADDR_BASE + ADDR_VERSION
-#define ENTROPY2_ADDR_CTRL      ENTROPY2_ADDR_BASE + (0x10 << 2)
+#define ENTROPY2_ADDR_CTRL      ENTROPY2_ADDR_BASE + ADDR(0x10)
 #define ENTROPY2_CTRL_ENABLE    1
-#define ENTROPY2_ADDR_STATUS    ENTROPY2_ADDR_BASE + (0x11 << 2)
+#define ENTROPY2_ADDR_STATUS    ENTROPY2_ADDR_BASE + ADDR(0x11)
 #define ENTROPY2_STATUS_VALID   1
-#define ENTROPY2_ADDR_OPA       ENTROPY2_ADDR_BASE + (0x18 << 2)
-#define ENTROPY2_ADDR_OPB       ENTROPY2_ADDR_BASE + (0x19 << 2)
-#define ENTROPY2_ADDR_ENTROPY   ENTROPY2_ADDR_BASE + (0x20 << 2)
-#define ENTROPY2_ADDR_RAW       ENTROPY2_ADDR_BASE + (0x21 << 2)
-#define ENTROPY2_ADDR_ROSC      ENTROPY2_ADDR_BASE + (0x22 << 2)
+#define ENTROPY2_ADDR_OPA       ENTROPY2_ADDR_BASE + ADDR(0x18)
+#define ENTROPY2_ADDR_OPB       ENTROPY2_ADDR_BASE + ADDR(0x19)
+#define ENTROPY2_ADDR_ENTROPY   ENTROPY2_ADDR_BASE + ADDR(0x20)
+#define ENTROPY2_ADDR_RAW       ENTROPY2_ADDR_BASE + ADDR(0x21)
+#define ENTROPY2_ADDR_ROSC      ENTROPY2_ADDR_BASE + ADDR(0x22)
 
 #define MIXER_ADDR_BASE         SEGMENT_OFFSET_RNGS + (0x0a * TRNG_CORE_SIZE)
 #define MIXER_ADDR_NAME0        MIXER_ADDR_BASE + ADDR_NAME0
 #define MIXER_ADDR_NAME1        MIXER_ADDR_BASE + ADDR_NAME1
 #define MIXER_ADDR_VERSION      MIXER_ADDR_BASE + ADDR_VERSION
-#define MIXER_ADDR_CTRL         MIXER_ADDR_BASE + (0x10 << 2)
+#define MIXER_ADDR_CTRL         MIXER_ADDR_BASE + ADDR(0x10)
 #define MIXER_CTRL_ENABLE       1
 #define MIXER_CTRL_RESTART      2
-#define MIXER_ADDR_STATUS       MIXER_ADDR_BASE + (0x11 << 2)
+#define MIXER_ADDR_STATUS       MIXER_ADDR_BASE + ADDR(0x11)
 // no status bits defined (yet)
-#define MIXER_ADDR_TIMEOUT      MIXER_ADDR_BASE + (0x20 << 2)
+#define MIXER_ADDR_TIMEOUT      MIXER_ADDR_BASE + ADDR(0x20)
 
 #define CSPRNG_ADDR_BASE        SEGMENT_OFFSET_RNGS + (0x0b * TRNG_CORE_SIZE)
 #define CSPRNG_ADDR_NAME0       CSPRNG_ADDR_BASE + ADDR_NAME0
 #define CSPRNG_ADDR_NAME1       CSPRNG_ADDR_BASE + ADDR_NAME1
 #define CSPRNG_ADDR_VERSION     CSPRNG_ADDR_BASE + ADDR_VERSION
-#define CSPRNG_ADDR_CTRL        CSPRNG_ADDR_BASE + (0x10 << 2)
+#define CSPRNG_ADDR_CTRL        CSPRNG_ADDR_BASE + ADDR(0x10)
 #define CSPRNG_CTRL_ENABLE      1
 #define CSPRNG_CTRL_SEED        2
-#define CSPRNG_ADDR_STATUS      CSPRNG_ADDR_BASE + (0x11 << 2)
+#define CSPRNG_ADDR_STATUS      CSPRNG_ADDR_BASE + ADDR(0x11)
 #define CSPRNG_STATUS_VALID     1
-#define CSPRNG_ADDR_RANDOM      CSPRNG_ADDR_BASE + (0x20 << 2)
-#define CSPRNG_ADDR_NROUNDS     CSPRNG_ADDR_BASE + (0x40 << 2)
-#define CSPRNG_ADDR_NBLOCKS_LO  CSPRNG_ADDR_BASE + (0x41 << 2)
-#define CSPRNG_ADDR_NBLOCKS_HI  CSPRNG_ADDR_BASE + (0x42 << 2)
+#define CSPRNG_ADDR_RANDOM      CSPRNG_ADDR_BASE + ADDR(0x20)
+#define CSPRNG_ADDR_NROUNDS     CSPRNG_ADDR_BASE + ADDR(0x40)
+#define CSPRNG_ADDR_NBLOCKS_LO  CSPRNG_ADDR_BASE + ADDR(0x41)
+#define CSPRNG_ADDR_NBLOCKS_HI  CSPRNG_ADDR_BASE + ADDR(0x42)
 
 //======================================================================
 // EOF cryptech_memory_map.h
diff --git a/eim/sw/hash_eim.c b/eim/sw/hash_eim.c
index 8ea761b..e698129 100644
--- a/eim/sw/hash_eim.c
+++ b/eim/sw/hash_eim.c
@@ -101,55 +101,25 @@ struct ctrl *find_algo(char *algo)
     return NULL;
 }
 
-/* ---------------- test-case low-level code ---------------- */
-
-int tc_init(off_t offset, int mode)
-{
-    uint8_t buf[4] = { 0, 0, 0, CTRL_INIT_CMD + mode };
-
-    return tc_write(offset, buf, 4);
-}
-
-int tc_next(off_t offset, int mode)
-{
-    uint8_t buf[4] = { 0, 0, 0, CTRL_NEXT_CMD + mode };
-
-    return tc_write(offset, buf, 4);
-}
-
-int tc_wait_ready(off_t offset)
-{
-    return tc_wait(offset, STATUS_READY_BIT, NULL);
-}
-
-int tc_wait_valid(off_t offset)
-{
-    return tc_wait(offset, STATUS_VALID_BIT, NULL);
-}
-
 /* ---------------- hash ---------------- */
 
-int transmit(off_t offset, uint8_t *block, int blen, int mode, int first)
+static int transmit(off_t offset, uint8_t *block, int blen, int mode, int first)
 {
-    off_t base = offset & ~(0xff);
+    off_t base = offset & ~(0x1ff);
+    uint8_t ctrl_cmd[4] = { 0 };
 
     if (tc_write(offset, block, blen) != 0)
         return 1;
 
-    if (first) {
-        if (tc_init(base + ADDR_CTRL, mode) != 0)
-            return 1;
-    }
-    else {
-        if (tc_next(base + ADDR_CTRL, mode) != 0)
-            return 1;
-    }
+    ctrl_cmd[3] = (first ? CTRL_INIT_CMD : CTRL_NEXT_CMD) | mode;
 
-    return tc_wait_ready(base + ADDR_STATUS);
+    return
+	tc_write(base + ADDR_CTRL, ctrl_cmd, 4) ||
+	tc_wait_ready(base + ADDR_STATUS);
 }
 
-int pad_transmit(off_t offset, uint8_t *block, uint8_t flen, uint8_t blen,
-                 uint8_t mode, long long tlen, int first)
+static int pad_transmit(off_t offset, uint8_t *block, uint8_t flen, uint8_t blen,
+			uint8_t mode, long long tlen, int first)
 {
     assert(flen < blen);
 
@@ -173,7 +143,7 @@ int pad_transmit(off_t offset, uint8_t *block, uint8_t flen, uint8_t blen,
 }
 
 /* return number of digest bytes read */
-int hash(char *algo, char *file, uint8_t *digest)
+static int hash(char *algo, char *file, uint8_t *digest)
 {
     uint8_t block[SHA512_BLOCK_LEN];
     struct ctrl *ctrl;
@@ -305,11 +275,6 @@ int main(int argc, char *argv[])
             printf("reading from stdin\n");
     }
 
-    if (eim_setup() != 0) {
-        fprintf(stderr, "EIM setup failed\n");
-        return EXIT_FAILURE;
-    }
-
     dlen = hash(algo, file, digest);
     if (dlen < 0)
         return EXIT_FAILURE;
diff --git a/eim/sw/hash_tester_eim.c b/eim/sw/hash_tester_eim.c
index 75b0f1d..8b4f04b 100644
--- a/eim/sw/hash_tester_eim.c
+++ b/eim/sw/hash_tester_eim.c
@@ -227,32 +227,6 @@ const uint8_t SHA512_DOUBLE_DIGEST[] =
   0xc7, 0xd3, 0x29, 0xee, 0xb6, 0xdd, 0x26, 0x54,
   0x5e, 0x96, 0xe5, 0x5b, 0x87, 0x4b, 0xe9, 0x09 };
 
-/* ---------------- test-case low-level code ---------------- */
-
-int tc_init(off_t offset)
-{
-    uint8_t buf[4] = { 0, 0, 0, CTRL_INIT_CMD };
-
-    return tc_write(offset, buf, 4);
-}
-
-int tc_next(off_t offset)
-{
-    uint8_t buf[4] = { 0, 0, 0, CTRL_NEXT_CMD };
-
-    return tc_write(offset, buf, 4);
-}
-
-int tc_wait_ready(off_t offset)
-{
-    return tc_wait(offset, STATUS_READY_BIT, NULL);
-}
-
-int tc_wait_valid(off_t offset)
-{
-    return tc_wait(offset, STATUS_VALID_BIT, NULL);
-}
-
 /* ---------------- sanity test case ---------------- */
 
 int TC0()
@@ -635,12 +609,6 @@ int main(int argc, char *argv[])
         }
     }
 
-    /* set up EIM */
-    if (eim_setup() != 0) {
-        fprintf(stderr, "EIM setup failed\n");
-        return EXIT_FAILURE;
-    }
-
     /* repeat one test until interrupted */
     if (repeat) {
         tcfp tc;
diff --git a/eim/sw/tc_eim.c b/eim/sw/tc_eim.c
index 0d8c83c..d44b685 100644
--- a/eim/sw/tc_eim.c
+++ b/eim/sw/tc_eim.c
@@ -44,10 +44,26 @@
 #include "tc_eim.h"
 
 extern int debug;
+static int inited = 0;
+
+/* ---------------- EIM low-level code ---------------- */
+static int init(void)
+{
+    if (inited)
+        return 0;
+
+    if (eim_setup() != 0) {
+        fprintf(stderr, "EIM setup failed\n");
+        return -1;
+    }
+
+    inited = 1;
+    return 0;
+}
 
 /* ---------------- test-case low-level code ---------------- */
 
-static void dump(char *label, const uint8_t *buf, int len)
+static void dump(char *label, const uint8_t *buf, size_t len)
 {
     if (debug) {
         int i;
@@ -58,8 +74,11 @@ static void dump(char *label, const uint8_t *buf, int len)
     }
 }
 
-int tc_write(off_t offset, const uint8_t *buf, int len)
+int tc_write(off_t offset, const uint8_t *buf, size_t len)
 {
+    if (init() != 0)
+        return -1;
+
     dump("write ", buf, len);
 
     for (; len > 0; offset += 4, buf += 4, len -= 4) {
@@ -71,11 +90,14 @@ int tc_write(off_t offset, const uint8_t *buf, int len)
     return 0;
 }
 
-int tc_read(off_t offset, uint8_t *buf, int len)
+int tc_read(off_t offset, uint8_t *buf, size_t len)
 {
     uint8_t *rbuf = buf;
     int rlen = len;
 
+    if (init() != 0)
+        return -1;
+
     for (; rlen > 0; offset += 4, rbuf += 4, rlen -= 4) {
         uint32_t val;
         eim_read_32(offset, &val);
@@ -87,7 +109,7 @@ int tc_read(off_t offset, uint8_t *buf, int len)
     return 0;
 }
 
-int tc_expected(off_t offset, const uint8_t *expected, int len)
+int tc_expected(off_t offset, const uint8_t *expected, size_t len)
 {
     uint8_t *buf;
     int i;
@@ -116,22 +138,48 @@ errout:
     return 1;
 }
 
+int tc_init(off_t offset)
+{
+    uint8_t buf[4] = { 0, 0, 0, CTRL_INIT_CMD };
+
+    return tc_write(offset, buf, 4);
+}
+
+int tc_next(off_t offset)
+{
+    uint8_t buf[4] = { 0, 0, 0, CTRL_NEXT_CMD };
+
+    return tc_write(offset, buf, 4);
+}
+
 int tc_wait(off_t offset, uint8_t status, int *count)
 {
     uint8_t buf[4];
     int i;
 
     for (i = 1; ; ++i) {
-	if (count && (*count > 0) && (i >= *count)) {
-	    fprintf(stderr, "tc_wait timed out\n");
-	    return 1;
-	}
+        if (count && (*count > 0) && (i >= *count)) {
+            fprintf(stderr, "tc_wait timed out\n");
+            return 1;
+        }
         if (tc_read(offset, buf, 4) != 0)
             return -1;
         if (buf[3] & status) {
-	    if (count)
-		*count = i;
+            if (count)
+                *count = i;
             return 0;
-	}
+        }
     }
 }
+
+int tc_wait_ready(off_t offset)
+{
+    int limit = 256;
+    return tc_wait(offset, STATUS_READY_BIT, &limit);
+}
+
+int tc_wait_valid(off_t offset)
+{
+    int limit = 256;
+    return tc_wait(offset, STATUS_VALID_BIT, &limit);
+}
diff --git a/eim/sw/tc_eim.h b/eim/sw/tc_eim.h
index 257822d..5da18e4 100644
--- a/eim/sw/tc_eim.h
+++ b/eim/sw/tc_eim.h
@@ -34,9 +34,17 @@
  */
 
 #include "novena-eim.h"
+#define BASE_ADDR               EIM_BASE_ADDR
+#define SEGMENT_SIZE            0x10000
+#define ADDR(x)                 (x << 2)
+#include "cryptech_memory_map.h"
 
 /* test case public functions */
-int tc_write(off_t offset, const uint8_t *buf, int len);
-int tc_read(off_t offset, uint8_t *buf, int len);
-int tc_expected(off_t offset, const uint8_t *expected, int len);
+int tc_write(off_t offset, const uint8_t *buf, size_t len);
+int tc_read(off_t offset, uint8_t *buf, size_t len);
+int tc_expected(off_t offset, const uint8_t *expected, size_t len);
+int tc_init(off_t offset);
+int tc_next(off_t offset);
 int tc_wait(off_t offset, uint8_t status, int *count);
+int tc_wait_ready(off_t offset);
+int tc_wait_valid(off_t offset);
diff --git a/eim/sw/trng_extractor_eim.c b/eim/sw/trng_extractor_eim.c
index 18fc1d6..be6ab16 100644
--- a/eim/sw/trng_extractor_eim.c
+++ b/eim/sw/trng_extractor_eim.c
@@ -145,12 +145,6 @@ int main(int argc, char *argv[])
         goto errout;
     }
 
-    /* set up EIM */
-    if (eim_setup() != 0) {
-        fprintf(stderr, "EIM setup failed\n");
-        return EXIT_FAILURE;
-    }
-
     /* get the data */
     for (i = 0; i < num_words; ++i) {
         if (extract(status_addr, data_addr, &data) != 0)
diff --git a/eim/sw/trng_tester_eim.c b/eim/sw/trng_tester_eim.c
index d25b784..def75ab 100644
--- a/eim/sw/trng_tester_eim.c
+++ b/eim/sw/trng_tester_eim.c
@@ -312,12 +312,6 @@ int main(int argc, char *argv[])
         }
     }
 
-    /* set up EIM */
-    if (eim_setup() != 0) {
-        fprintf(stderr, "EIM setup failed\n");
-        return EXIT_FAILURE;
-    }
-
     /* repeat one test until interrupted */
     if (repeat) {
         tcfp tc;