Merge branch 'config_core_selector'

2 files changed, 50 insertions, 76 deletions

diff --git a/eim/build/Makefile b/eim/build/Makefile
index 678a2e5..a7eec60 100644
--- a/eim/build/Makefile
+++ b/eim/build/Makefile
@@ -1,74 +1,48 @@
-project = novena_eim
-vendor = xilinx
-family = spartan6
-part = xc6slx45csg324-3
-top_module = novena_top
-isedir = /opt/Xilinx/14.7/ISE_DS
-xil_env = . $(isedir)/settings64.sh
-ucf = ../ucf/novena_eim.ucf
+# Localize all the relative path awfulness in one variable.
+
+CORE_TREE	:= $(abspath ../../../..)
+
+# Figure out what the native word size is on the build host, because
+# the XiLinx tools care for some reason.
+
+WORD_SIZE	:= $(shell python -c 'from struct import pack; print len(pack("L", 0)) * 8')
+
+# Parameters to xilinx.mk.
+
+project		= novena_eim
+vendor		= xilinx
+family		= spartan6
+part		= xc6slx45csg324-3
+top_module	= novena_top
+isedir		= /opt/Xilinx/14.7/ISE_DS
+xil_env		= . $(isedir)/settings$(WORD_SIZE).sh
+ucf		= ../ucf/$(project).ucf
+
+# Verilog files that always go with builds on this platform.
 
 vfiles = \
-	../rtl/novena_eim.v \
-	../../common/rtl/novena_regs.v \
-	../../common/rtl/novena_clkmgr.v \
-	../../common/rtl/clkmgr_dcm.v \
-	../../../common/core_selector/src/rtl/core_selector.v \
-	../../../common/core_selector/src/rtl/global_selector.v \
-	../../../common/core_selector/src/rtl/hash_selector.v \
-	../../../common/core_selector/src/rtl/rng_selector.v \
-	../../../common/core_selector/src/rtl/cipher_selector.v \
-	../../../common/core_selector/src/rtl/math_selector.v \
-	../../../../comm/eim/src/rtl/cdc_bus_pulse.v \
-	../../../../comm/eim/src/rtl/eim_arbiter_cdc.v \
-	../../../../comm/eim/src/rtl/eim_arbiter.v \
-	../../../../comm/eim/src/rtl/eim_da_phy.v \
-	../../../../comm/eim/src/rtl/eim_indicator.v \
-	../../../../comm/eim/src/rtl/eim_regs.v \
-	../../../../comm/eim/src/rtl/eim.v \
-	../../../../hash/sha1/src/rtl/sha1.v \
-	../../../../hash/sha1/src/rtl/sha1_core.v \
-	../../../../hash/sha1/src/rtl/sha1_w_mem.v \
-	../../../../hash/sha256/src/rtl/sha256.v \
-	../../../../hash/sha256/src/rtl/sha256_core.v \
-	../../../../hash/sha256/src/rtl/sha256_k_constants.v \
-	../../../../hash/sha256/src/rtl/sha256_w_mem.v \
-	../../../../hash/sha512/src/rtl/sha512.v \
-	../../../../hash/sha512/src/rtl/sha512_core.v \
-	../../../../hash/sha512/src/rtl/sha512_h_constants.v \
-	../../../../hash/sha512/src/rtl/sha512_k_constants.v \
-	../../../../hash/sha512/src/rtl/sha512_w_mem.v \
-	../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy.v \
-	../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v \
-	../../../../rng/rosc_entropy/src/rtl/rosc.v \
-	../../../../rng/rosc_entropy/src/rtl/rosc_entropy.v \
-	../../../../rng/rosc_entropy/src/rtl/rosc_entropy_core.v \
-	../../../../rng/trng/src/rtl/trng.v \
-	../../../../rng/trng/src/rtl/trng_csprng.v \
-	../../../../rng/trng/src/rtl/trng_csprng_fifo.v \
-	../../../../rng/trng/src/rtl/trng_mixer.v \
-	../../../../cipher/aes/src/rtl/aes.v \
-	../../../../cipher/aes/src/rtl/aes_core.v \
-	../../../../cipher/aes/src/rtl/aes_decipher_block.v \
-	../../../../cipher/aes/src/rtl/aes_encipher_block.v \
-	../../../../cipher/aes/src/rtl/aes_inv_sbox.v \
-	../../../../cipher/aes/src/rtl/aes_key_mem.v \
-	../../../../cipher/aes/src/rtl/aes_sbox.v \
-	../../../../cipher/chacha/src/rtl/chacha.v \
-	../../../../cipher/chacha/src/rtl/chacha_core.v \
-	../../../../cipher/chacha/src/rtl/chacha_qr.v \
-	../../../../math/modexps6/src/rtl/modexps6_adder64_carry32.v \
-	../../../../math/modexps6/src/rtl/modexps6_buffer_core.v \
-	../../../../math/modexps6/src/rtl/modexps6_buffer_user.v \
-	../../../../math/modexps6/src/rtl/modexps6_modinv32.v \
-	../../../../math/modexps6/src/rtl/modexps6_montgomery_coeff.v \
-	../../../../math/modexps6/src/rtl/modexps6_montgomery_multiplier.v \
-	../../../../math/modexps6/src/rtl/modexps6_top.v \
-	../../../../math/modexps6/src/rtl/modexps6_wrapper.v \
-	../../../../math/modexps6/src/rtl/ram_1rw_1ro_readfirst.v \
-	../../../../math/modexps6/src/rtl/ipcore/multiplier_s6.v \
-	../../../../math/modexps6/src/rtl/ipcore/subtractor_s6.v
+	$(CORE_TREE)/platform/novena/eim/rtl/novena_eim.v \
+	$(CORE_TREE)/platform/novena/common/rtl/novena_regs.v \
+	$(CORE_TREE)/platform/novena/common/rtl/novena_clkmgr.v \
+	$(CORE_TREE)/platform/novena/common/rtl/clkmgr_dcm.v \
+	$(CORE_TREE)/platform/novena/config/core_selector.v \
+	$(CORE_TREE)/comm/eim/src/rtl/cdc_bus_pulse.v \
+	$(CORE_TREE)/comm/eim/src/rtl/eim_arbiter_cdc.v \
+	$(CORE_TREE)/comm/eim/src/rtl/eim_arbiter.v \
+	$(CORE_TREE)/comm/eim/src/rtl/eim_da_phy.v \
+	$(CORE_TREE)/comm/eim/src/rtl/eim_indicator.v \
+	$(CORE_TREE)/comm/eim/src/rtl/eim_regs.v \
+	$(CORE_TREE)/comm/eim/src/rtl/eim.v
+
+# Verilog files selected by the core configuration script.
+
+-include $(CORE_TREE)/platform/novena/config/core_vfiles.mk
 
 include xilinx.mk
 
+# Fun extras for running verlator as a linter.
+
+VERILATOR_FLAGS	= --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME
+
 lint:
-	verilator --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME $(vfiles) ../../common/rtl/lint-dummy.v
+	verilator ${VERILATOR_FLAGS} $(vfiles) $(CORE_TREE)/platform/novena/common/rtl/lint-dummy.v
diff --git a/eim/build/xilinx.mk b/eim/build/xilinx.mk
index 8a81ef9..7a8d9d4 100644
--- a/eim/build/xilinx.mk
+++ b/eim/build/xilinx.mk
@@ -1,6 +1,6 @@
 # The top level module should define the variables below then include
 # this file.  The files listed should be in the same directory as the
-# Makefile.  
+# Makefile.
 #
 #   variable	description
 #   ----------  -------------
@@ -11,7 +11,7 @@
 #   vfiles	all local .v files
 #   xilinx_cores  all local .xco files
 #   vendor      vendor of FPGA (xilinx, altera, etc.)
-#   family      FPGA device family (spartan3e) 
+#   family      FPGA device family (spartan3e)
 #   part        FPGA part name (xc4vfx12-10-sf363)
 #   flashsize   size of flash for mcs file (16384)
 #   optfile     (optional) xst extra opttions file to put in .scr
@@ -40,7 +40,7 @@ xil_env ?= . $(isedir)/settings32.sh
 flashsize ?= 8192
 ucf ?= $(project).ucf
 
-libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs)) 
+libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs))
 mkfiles = $(libmks) xilinx.mk
 include $(libmks)
 
@@ -110,9 +110,9 @@ $(project)_par.ncd: $(project).ncd
 		:; \
 	else \
 		$(MAKE) etwr; \
-	fi 
-junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad 
-junk += $(project)_par_pad.csv $(project)_par_pad.txt 
+	fi
+junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad
+junk += $(project)_par_pad.csv $(project)_par_pad.txt
 junk += $(project)_par.grf $(project)_par.ptwx
 junk += $(project)_par.unroutes $(project)_par.xpi
 
@@ -126,7 +126,7 @@ $(project).ncd: $(project).ngd
 	$(xil_env); \
 	map $(intstyle) $(map_opts) $$smartguide $<
 junk += $(project).ncd $(project).pcf $(project).ngm $(project).mrp $(project).map
-junk += smartguide.ncd $(project).psr 
+junk += smartguide.ncd $(project).psr
 junk += $(project)_summary.xml $(project)_usage.xml
 
 $(project).ngd: $(project).ngc $(ucf)
@@ -135,7 +135,7 @@ junk += $(project).ngd $(project).bld
 
 $(project).ngc: $(vfiles) $(local_corengcs) $(project).scr $(project).prj
 	$(xil_env); xst $(intstyle) -ifn $(project).scr
-junk += xlnx_auto* $(top_module).lso $(project).srp 
+junk += xlnx_auto* $(top_module).lso $(project).srp
 junk += netlist.lst xst $(project).ngc
 
 $(project).prj: $(vfiles) $(mkfiles)