Handle reset high/low logic in the config file. Connect error signals.

3 files changed, 57 insertions, 39 deletions

diff --git a/config/config.cfg b/config/config.cfg
index 9bb01ae..a4120b1 100644
--- a/config/config.cfg
+++ b/config/config.cfg
@@ -86,6 +86,7 @@ vfiles =
 	cipher/chacha/src/rtl/chacha_qr.v
 
 [modexps6]
+reset_high = true
 vfiles =
 	math/modexps6/src/rtl/modexps6_adder64_carry32.v
 	math/modexps6/src/rtl/modexps6_buffer_core.v
diff --git a/config/config.py b/config/config.py
index 2a11bd6..3ae809b 100755
--- a/config/config.py
+++ b/config/config.py
@@ -56,14 +56,14 @@ Generate core_selector.v for a set of cores.
 # - Figure out whether this really belongs in the novena repository at
 #   all, seems more generic than that.
 
+
 def main():
     """
     Parse arguments and config file, generate core list, generate output.
     """
 
-    from argparse       import ArgumentParser, FileType, ArgumentDefaultsHelpFormatter
-    from ConfigParser   import RawConfigParser
-    from sys            import exit
+    from argparse import ArgumentParser, FileType, ArgumentDefaultsHelpFormatter
+    from sys      import exit
 
     parser = ArgumentParser(description = __doc__, formatter_class = ArgumentDefaultsHelpFormatter)
     parser.add_argument("-d", "--debug",   help = "enable debugging",   action = "store_true")
@@ -88,11 +88,16 @@ def main():
         cores.insert(1, "comm_regs")
 
         cores = tuple(Core.new(core) for core in cores)
+
         core_number = 0
         for core in cores:
             core_number = core.assign_core_number(core_number)
-        for core in cores[2:]:
-            core.add_vfiles(cfg)
+
+        cores[0].reset_high = True
+        cores[1].reset_high = True
+
+        for core in cores:
+            core.configure(cfg)
 
         args.verilog.write(createModule_template.format(
             addrs = "".join(core.createAddr()     for core in cores),
@@ -108,6 +113,28 @@ def main():
         exit(str(e))
 
 
+try:
+    import ConfigParser as configparser
+except ImportError:
+    import configparser   
+
+class RawConfigParser(configparser.RawConfigParser):
+    """
+    RawConfigParser with a few extensions.
+    """
+
+    def getboolean(self, section, option, default = False):
+        if self.has_option(section, option):
+            return super(RawConfigParser, self).getboolean(section, option)
+        else:
+            return default
+
+    def getvalues(self, section, option):
+        if self.has_option(section, option):
+            for value in self.get(section, option).split():
+                yield value
+
+
 class Core(object):
     """
     Data and methods for a generic core.  We can use this directly for
@@ -127,7 +154,8 @@ class Core(object):
     def __init__(self, name):
         self.name = name
         self.core_number = None
-        self.vfiles = ()
+        self.vfiles = []
+        self.reset_high = False
         self.instance_number = self._instance_count.get(name, 0)
         self._instance_count[name] = self.instance_number + 1
 
@@ -139,13 +167,13 @@ class Core(object):
         self.core_number = n
         return n + 1
 
-    def add_vfiles(self, cfg):
+    def configure(self, cfg):
         if self.instance_number == 0:
-            self.vfiles = cfg.get(self.name, "vfiles").split()
-            if cfg.has_option(self.name, "requires"):
-                for required in cfg.get(self.name, "requires").split():
-                    if required not in self._instance_count:
-                        self.vfiles.extend(cfg.get(required, "vfiles").split())
+            self.vfiles.extend(cfg.getvalues(self.name, "vfiles"))
+            for required in cfg.getvalues(self.name, "requires"):
+                if required not in self._instance_count:
+                    self.vfiles.extend(cfg.getvalues(required, "vfiles"))
+        self.reset_high = cfg.getboolean(self.name, "reset_high", self.reset_high)
 
     @property
     def instance_name(self):
@@ -160,7 +188,7 @@ class Core(object):
 
     @property
     def reset_pin(self):
-        return ".rst(sys_rst)"
+        return ".rst(sys_rst)" if self.reset_high else ".reset_n(~sys_rst)"
 
     def createInstance(self):
         return createInstance_template_generic.format(core = self)
@@ -175,17 +203,6 @@ class Core(object):
         return "".join(" \\\n\t$(CORE_TREE)/" + vfile for vfile in self.vfiles)
 
 
-class InvertedResetCore(Core):
-    """
-    Core which inverts the reset signal.  Seems to vary by author.
-    No, I don't know why we don't just pick one convention or the other.
-    """
-
-    @property
-    def reset_pin(self):
-        return ".reset_n(~sys_rst)"
-
-
 class SubCore(Core):
     """"
     Override mux handling for TRNG's sub-cores.
@@ -199,7 +216,7 @@ class SubCore(Core):
         return createMux_template.format(core = self, core0 = self.parent)
 
 
-class TRNGCore(InvertedResetCore):
+class TRNGCore(Core):
     """
     The TRNG core has an internal mux and a collection of sub-cores.
     Mostly this means that our method calls have to iterate over all
@@ -252,16 +269,9 @@ class ModExpS6Core(Core):
 
 
 # Hook special classes in as handlers for the cores that require them.
-# Moving the reset-high/reset-low logic to the config file should simplify this.
 
 Core.special_class.update(
     trng        = TRNGCore,
-    aes         = InvertedResetCore,
-    chacha      = InvertedResetCore,
-    sha1        = InvertedResetCore,
-    sha256      = InvertedResetCore,
-    sha512      = InvertedResetCore,
-    modexp      = InvertedResetCore,
     modexps6    = ModExpS6Core)
 
 
@@ -296,7 +306,8 @@ createInstance_template_generic = """\
 
       .address(addr_core_reg),
       .write_data(sys_write_data),
-      .read_data(read_data_{core.instance_name})
+      .read_data(read_data_{core.instance_name}),
+      .error(error_{core.instance_name})
       );
 
    reg  [31: 0] read_data_{core.instance_name}_reg;
@@ -315,7 +326,6 @@ createInstance_template_ModExpS6 = """\
    //----------------------------------------------------------------
    wire                 enable_{core.instance_name} = (addr_core_num >= CORE_ADDR_{core.upper_instance_name}) && (addr_core_num <= CORE_ADDR_{core.upper_instance_name} + 3);
    wire [31: 0]         read_data_{core.instance_name};
-   wire                 error_{core.instance_name};
    wire [1:0]           {core.instance_name}_prefix = addr_core_num[1:0] - CORE_ADDR_{core.upper_instance_name};
 
    {core.name}_wrapper {core.instance_name}_inst
@@ -358,6 +368,7 @@ createInstance_template_TRNG = """\
       .address({{{core.instance_name}_prefix, addr_core_reg}}),
       .write_data(sys_write_data),
       .read_data(read_data_{core.instance_name}),
+      .error(error_{core.instance_name}),
 
       .avalanche_noise(noise),
       .debug(debug)
diff --git a/config/core_selector.v b/config/core_selector.v
index 16d1a09..cc7ca14 100644
--- a/config/core_selector.v
+++ b/config/core_selector.v
@@ -58,7 +58,8 @@ module core_selector
 
       .address(addr_core_reg),
       .write_data(sys_write_data),
-      .read_data(read_data_board_regs)
+      .read_data(read_data_board_regs),
+      .error(error_board_regs)
       );
 
    reg  [31: 0] read_data_board_regs_reg;
@@ -83,7 +84,8 @@ module core_selector
 
       .address(addr_core_reg),
       .write_data(sys_write_data),
-      .read_data(read_data_comm_regs)
+      .read_data(read_data_comm_regs),
+      .error(error_comm_regs)
       );
 
    reg  [31: 0] read_data_comm_regs_reg;
@@ -108,7 +110,8 @@ module core_selector
 
       .address(addr_core_reg),
       .write_data(sys_write_data),
-      .read_data(read_data_sha256)
+      .read_data(read_data_sha256),
+      .error(error_sha256)
       );
 
    reg  [31: 0] read_data_sha256_reg;
@@ -133,7 +136,8 @@ module core_selector
 
       .address(addr_core_reg),
       .write_data(sys_write_data),
-      .read_data(read_data_aes)
+      .read_data(read_data_aes),
+      .error(error_aes)
       );
 
    reg  [31: 0] read_data_aes_reg;
@@ -160,6 +164,7 @@ module core_selector
       .address({trng_prefix, addr_core_reg}),
       .write_data(sys_write_data),
       .read_data(read_data_trng),
+      .error(error_trng),
 
       .avalanche_noise(noise),
       .debug(debug)
@@ -187,7 +192,8 @@ module core_selector
 
       .address(addr_core_reg),
       .write_data(sys_write_data),
-      .read_data(read_data_modexp)
+      .read_data(read_data_modexp),
+      .error(error_modexp)
       );
 
    reg  [31: 0] read_data_modexp_reg;