Comment update.

1 files changed, 4 insertions, 6 deletions

diff --git a/config/config.py b/config/config.py
index 26385d0..c0c3c5e 100755
--- a/config/config.py
+++ b/config/config.py
@@ -1,9 +1,10 @@
 #!/usr/bin/env python
+
 """
-Generate core_selector.v for a set of cores.
+Generate core_selector.v and core_vfiles.mk for a set of cores.
 """
 
-# History of cryptech bus addressing scheme, as best I understand it.
+# History of Cryptech bus addressing scheme, as best I understand it.
 #
 # The old old addressing scheme that Joachim and Paul came up with
 # was:
@@ -33,7 +34,7 @@ Generate core_selector.v for a set of cores.
 # Except that this would waste space for most cores, and make things
 # very confusing for the TRNG cores.  So, instead, we keep Paul's
 # two-level (no segment) scheme and handle modexps6 as a set of four
-# consecutive "cores" with a 10-bit composite register selector.
+# contiguous "cores" with a 10-bit composite register selector.
 
 # The modexps6 core also drags in a one clock cycle delay to other
 # cores, to compensate for the extra clock cycle consumed by the block
@@ -41,9 +42,6 @@ Generate core_selector.v for a set of cores.
 
 # To Do:
 #
-# - Move reset-high/reset-low to a boolean variable in the config
-#   file, simplify Core classes accordingly.
-#
 # - Consider automating the one-clock-cycle delay stuff by adding
 #   another boolean flag to the config file.  Default would be no
 #   delay, if any included core sets the "I use block memories" flag,