diff options
author | Paul Selkirk <paul@psgd.org> | 2015-10-19 17:55:04 -0400 |
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committer | Paul Selkirk <paul@psgd.org> | 2015-10-19 17:55:04 -0400 |
commit | 3d96445bf19f3fd15b2ad9fe4cd7a08bad9c0e41 (patch) | |
tree | f16879437e301ff221f82047638afe4d44b71d41 /common/rtl/ipcore/_xmsgs | |
parent | 76774e17233eb7d2a3430317278c8932c8ccb2d7 (diff) |
integrate Pavel's new clkmgr code
Diffstat (limited to 'common/rtl/ipcore/_xmsgs')
-rw-r--r-- | common/rtl/ipcore/_xmsgs/cg.xmsgs | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/common/rtl/ipcore/_xmsgs/cg.xmsgs b/common/rtl/ipcore/_xmsgs/cg.xmsgs deleted file mode 100644 index 985e6e3..0000000 --- a/common/rtl/ipcore/_xmsgs/cg.xmsgs +++ /dev/null @@ -1,27 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?>
-<!-- IMPORTANT: This is an internal file that has been generated
- by the Xilinx ISE software. Any direct editing or
- changes made to this file may result in unpredictable
- behavior or data corruption. It is strongly advised that
- users do not edit the contents of this file. -->
-<messages> -<msg type="info" file="sim" num="172" delta="old" >Generating IP...
-</msg>
- -<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'clkmgr_dcm' already exists in the project. Output products for this core may be overwritten.</arg>
-</msg>
- -<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'clkmgr_dcm' already exists in the project. Output products for this core may be overwritten.</arg>
-</msg>
- -<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Component clk_wiz_v3_6 does not have a valid model name for Verilog synthesis</arg>
-</msg>
- -<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
-</msg>
- -<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
-</msg>
- -</messages> -
|