diff options
| author | Rob Austein <sra@hactrn.net> | 2015-09-23 16:21:34 -0400 |
|---|---|---|
| committer | Rob Austein <sra@hactrn.net> | 2015-09-23 16:21:34 -0400 |
| commit | 99c3749c85b85b4865c4baafdd16b2cbb3ac52f2 (patch) | |
| tree | 99a2ecef007a8a5c6c77644758f2017549243529 | |
| parent | f141a79d805acbab07876d9f007e8809603718b5 (diff) | |
| parent | 5f1de63e3bc6043ee10683a2c9fd8a7c03a3983a (diff) | |
Merge branch 'modexps6' into config_core_selector_sra
72 files changed, 1900 insertions, 3951 deletions
diff --git a/common/rtl/ipcore/_xmsgs/cg.xmsgs b/common/rtl/ipcore/_xmsgs/cg.xmsgs deleted file mode 100644 index 985e6e3..0000000 --- a/common/rtl/ipcore/_xmsgs/cg.xmsgs +++ /dev/null @@ -1,27 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?>
-<!-- IMPORTANT: This is an internal file that has been generated
- by the Xilinx ISE software. Any direct editing or
- changes made to this file may result in unpredictable
- behavior or data corruption. It is strongly advised that
- users do not edit the contents of this file. -->
-<messages> -<msg type="info" file="sim" num="172" delta="old" >Generating IP...
-</msg>
- -<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'clkmgr_dcm' already exists in the project. Output products for this core may be overwritten.</arg>
-</msg>
- -<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'clkmgr_dcm' already exists in the project. Output products for this core may be overwritten.</arg>
-</msg>
- -<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Component clk_wiz_v3_6 does not have a valid model name for Verilog synthesis</arg>
-</msg>
- -<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
-</msg>
- -<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
-</msg>
- -</messages> -
diff --git a/common/rtl/ipcore/clkmgr_dcm.asy b/common/rtl/ipcore/clkmgr_dcm.asy deleted file mode 100644 index 016d02a..0000000 --- a/common/rtl/ipcore/clkmgr_dcm.asy +++ /dev/null @@ -1,25 +0,0 @@ -Version 4 -SymbolType BLOCK -TEXT 32 32 LEFT 4 clkmgr_dcm -RECTANGLE Normal 32 32 576 1088 -LINE Normal 0 80 32 80 -PIN 0 80 LEFT 36 -PINATTR PinName clk_in1 -PINATTR Polarity IN -LINE Normal 0 432 32 432 -PIN 0 432 LEFT 36 -PINATTR PinName reset -PINATTR Polarity IN -LINE Normal 608 80 576 80 -PIN 608 80 RIGHT 36 -PINATTR PinName clk_out1 -PINATTR Polarity OUT -LINE Normal 608 880 576 880 -PIN 608 880 RIGHT 36 -PINATTR PinName input_clk_stopped -PINATTR Polarity OUT -LINE Normal 608 1008 576 1008 -PIN 608 1008 RIGHT 36 -PINATTR PinName clk_valid -PINATTR Polarity OUT -
diff --git a/common/rtl/ipcore/clkmgr_dcm.gise b/common/rtl/ipcore/clkmgr_dcm.gise deleted file mode 100644 index ed6d0f7..0000000 --- a/common/rtl/ipcore/clkmgr_dcm.gise +++ /dev/null @@ -1,31 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <!-- -->
-
- <!-- For tool use only. Do not edit. -->
-
- <!-- -->
-
- <!-- ProjectNavigator created generated project file. -->
-
- <!-- For use in tracking generated file and other information -->
-
- <!-- allowing preservation of process status. -->
-
- <!-- -->
-
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
-
- <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
- <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="clkmgr_dcm.xise"/>
-
- <files xmlns="http://www.xilinx.com/XMLSchema">
- <file xil_pn:fileType="FILE_ASY" xil_pn:name="clkmgr_dcm.asy" xil_pn:origination="imported"/>
- <file xil_pn:fileType="FILE_VEO" xil_pn:name="clkmgr_dcm.veo" xil_pn:origination="imported"/>
- </files>
-
- <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
-
-</generated_project>
diff --git a/common/rtl/ipcore/clkmgr_dcm.ncf b/common/rtl/ipcore/clkmgr_dcm.ncf deleted file mode 100644 index ef4e259..0000000 --- a/common/rtl/ipcore/clkmgr_dcm.ncf +++ /dev/null @@ -1,60 +0,0 @@ -# file: clkmgr_dcm.ucf -# -# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# - -# Input clock periods. These duplicate the values entered for the -# input clocks. You can use these to time your system -#---------------------------------------------------------------- -NET "CLK_IN1" TNM_NET = "CLK_IN1"; -TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps; - - -# FALSE PATH constraints -PIN "RESET" TIG; - - diff --git a/common/rtl/ipcore/clkmgr_dcm.sym b/common/rtl/ipcore/clkmgr_dcm.sym deleted file mode 100644 index 7d178b8..0000000 --- a/common/rtl/ipcore/clkmgr_dcm.sym +++ /dev/null @@ -1,24 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?>
-<symbol version="7" name="clkmgr_dcm">
- <symboltype>BLOCK</symboltype>
- <timestamp>2015-1-28T21:56:19</timestamp>
- <pin polarity="Input" x="0" y="80" name="clk_in1" />
- <pin polarity="Input" x="0" y="432" name="reset" />
- <pin polarity="Output" x="608" y="80" name="clk_out1" />
- <pin polarity="Output" x="608" y="880" name="input_clk_stopped" />
- <pin polarity="Output" x="608" y="1008" name="clk_valid" />
- <graph>
- <text style="fontsize:40;fontname:Arial" x="32" y="32">clkmgr_dcm</text>
- <rect width="544" x="32" y="32" height="1056" />
- <line x2="32" y1="80" y2="80" x1="0" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin clk_in1" />
- <line x2="32" y1="432" y2="432" x1="0" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="432" type="pin reset" />
- <line x2="576" y1="80" y2="80" x1="608" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="80" type="pin clk_out1" />
- <line x2="576" y1="880" y2="880" x1="608" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="880" type="pin input_clk_stopped" />
- <line x2="576" y1="1008" y2="1008" x1="608" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="1008" type="pin clk_valid" />
- </graph>
-</symbol>
diff --git a/common/rtl/ipcore/clkmgr_dcm.ucf b/common/rtl/ipcore/clkmgr_dcm.ucf deleted file mode 100644 index 658fdb4..0000000 --- a/common/rtl/ipcore/clkmgr_dcm.ucf +++ /dev/null @@ -1,59 +0,0 @@ -# file: clkmgr_dcm.ucf
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# Input clock periods. These duplicate the values entered for the
-# input clocks. You can use these to time your system
-#----------------------------------------------------------------
-NET "CLK_IN1" TNM_NET = "CLK_IN1";
-TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
-
-
-# FALSE PATH constraints
-PIN "RESET" TIG;
-
diff --git a/common/rtl/ipcore/clkmgr_dcm.v b/common/rtl/ipcore/clkmgr_dcm.v index 71477a8..6e57c3d 100644 --- a/common/rtl/ipcore/clkmgr_dcm.v +++ b/common/rtl/ipcore/clkmgr_dcm.v @@ -62,6 +62,10 @@ //----------------------------------------------------------------------------
// __primary______________50____________0.010
+/*verilator lint_off PINCONNECTEMPTY*/
+/*verilator lint_off UNDRIVEN*/
+/*verilator lint_off UNUSED*/
+
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clkmgr_dcm,clk_wiz_v3_6,{component_name=clkmgr_dcm,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=true,use_status=false,use_freeze=false,use_clk_valid=true,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
diff --git a/common/rtl/ipcore/clkmgr_dcm.veo b/common/rtl/ipcore/clkmgr_dcm.veo deleted file mode 100644 index c4e1d31..0000000 --- a/common/rtl/ipcore/clkmgr_dcm.veo +++ /dev/null @@ -1,79 +0,0 @@ -//
-// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-//----------------------------------------------------------------------------
-// User entered comments
-//----------------------------------------------------------------------------
-// None
-//
-//----------------------------------------------------------------------------
-// "Output Output Phase Duty Pk-to-Pk Phase"
-// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
-//----------------------------------------------------------------------------
-// CLK_OUT1____50.000______0.000______50.0______200.000____150.000
-//
-//----------------------------------------------------------------------------
-// "Input Clock Freq (MHz) Input Jitter (UI)"
-//----------------------------------------------------------------------------
-// __primary______________50____________0.010
-
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-
- clkmgr_dcm instance_name
- (// Clock in ports
- .CLK_IN1(CLK_IN1), // IN
- // Clock out ports
- .CLK_OUT1(CLK_OUT1), // OUT
- // Status and control signals
- .RESET(RESET),// IN
- .INPUT_CLK_STOPPED(INPUT_CLK_STOPPED), // OUT
- .CLK_VALID(CLK_VALID)); // OUT
-// INST_TAG_END ------ End INSTANTIATION Template ---------
diff --git a/common/rtl/ipcore/clkmgr_dcm.xco b/common/rtl/ipcore/clkmgr_dcm.xco deleted file mode 100644 index 37f1a1d..0000000 --- a/common/rtl/ipcore/clkmgr_dcm.xco +++ /dev/null @@ -1,269 +0,0 @@ -##############################################################
-#
-# Xilinx Core Generator version 14.7
-# Date: Sun Feb 01 07:49:40 2015
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# Generated from component: xilinx.com:ip:clk_wiz:3.6
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc6slx45
-SET devicefamily = spartan6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = csg324
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
-# END Select
-# BEGIN Parameters
-CSET calc_done=DONE
-CSET clk_in_sel_port=CLK_IN_SEL
-CSET clk_out1_port=CLK_OUT1
-CSET clk_out1_use_fine_ps_gui=false
-CSET clk_out2_port=CLK_OUT2
-CSET clk_out2_use_fine_ps_gui=false
-CSET clk_out3_port=CLK_OUT3
-CSET clk_out3_use_fine_ps_gui=false
-CSET clk_out4_port=CLK_OUT4
-CSET clk_out4_use_fine_ps_gui=false
-CSET clk_out5_port=CLK_OUT5
-CSET clk_out5_use_fine_ps_gui=false
-CSET clk_out6_port=CLK_OUT6
-CSET clk_out6_use_fine_ps_gui=false
-CSET clk_out7_port=CLK_OUT7
-CSET clk_out7_use_fine_ps_gui=false
-CSET clk_valid_port=CLK_VALID
-CSET clkfb_in_n_port=CLKFB_IN_N
-CSET clkfb_in_p_port=CLKFB_IN_P
-CSET clkfb_in_port=CLKFB_IN
-CSET clkfb_in_signaling=SINGLE
-CSET clkfb_out_n_port=CLKFB_OUT_N
-CSET clkfb_out_p_port=CLKFB_OUT_P
-CSET clkfb_out_port=CLKFB_OUT
-CSET clkfb_stopped_port=CLKFB_STOPPED
-CSET clkin1_jitter_ps=200.0
-CSET clkin1_ui_jitter=0.010
-CSET clkin2_jitter_ps=100.0
-CSET clkin2_ui_jitter=0.010
-CSET clkout1_drives=BUFG
-CSET clkout1_requested_duty_cycle=50.0
-CSET clkout1_requested_out_freq=50
-CSET clkout1_requested_phase=0.000
-CSET clkout2_drives=BUFG
-CSET clkout2_requested_duty_cycle=50.0
-CSET clkout2_requested_out_freq=50
-CSET clkout2_requested_phase=0
-CSET clkout2_used=false
-CSET clkout3_drives=BUFG
-CSET clkout3_requested_duty_cycle=50.0
-CSET clkout3_requested_out_freq=100.000
-CSET clkout3_requested_phase=0.000
-CSET clkout3_used=false
-CSET clkout4_drives=BUFG
-CSET clkout4_requested_duty_cycle=50.0
-CSET clkout4_requested_out_freq=100.000
-CSET clkout4_requested_phase=0.000
-CSET clkout4_used=false
-CSET clkout5_drives=BUFG
-CSET clkout5_requested_duty_cycle=50.0
-CSET clkout5_requested_out_freq=100.000
-CSET clkout5_requested_phase=0.000
-CSET clkout5_used=false
-CSET clkout6_drives=BUFG
-CSET clkout6_requested_duty_cycle=50.0
-CSET clkout6_requested_out_freq=100.000
-CSET clkout6_requested_phase=0.000
-CSET clkout6_used=false
-CSET clkout7_drives=BUFG
-CSET clkout7_requested_duty_cycle=50.0
-CSET clkout7_requested_out_freq=100.000
-CSET clkout7_requested_phase=0.000
-CSET clkout7_used=false
-CSET clock_mgr_type=MANUAL
-CSET component_name=clkmgr_dcm
-CSET daddr_port=DADDR
-CSET dclk_port=DCLK
-CSET dcm_clk_feedback=1X
-CSET dcm_clk_out1_port=CLK0
-CSET dcm_clk_out2_port=CLK0
-CSET dcm_clk_out3_port=CLK0
-CSET dcm_clk_out4_port=CLK0
-CSET dcm_clk_out5_port=CLK0
-CSET dcm_clk_out6_port=CLK0
-CSET dcm_clkdv_divide=2.0
-CSET dcm_clkfx_divide=1
-CSET dcm_clkfx_multiply=4
-CSET dcm_clkgen_clk_out1_port=CLKFX
-CSET dcm_clkgen_clk_out2_port=CLKFX
-CSET dcm_clkgen_clk_out3_port=CLKFX
-CSET dcm_clkgen_clkfx_divide=1
-CSET dcm_clkgen_clkfx_md_max=0.000
-CSET dcm_clkgen_clkfx_multiply=4
-CSET dcm_clkgen_clkfxdv_divide=2
-CSET dcm_clkgen_clkin_period=10.000
-CSET dcm_clkgen_notes=None
-CSET dcm_clkgen_spread_spectrum=NONE
-CSET dcm_clkgen_startup_wait=false
-CSET dcm_clkin_divide_by_2=false
-CSET dcm_clkin_period=20.000
-CSET dcm_clkout_phase_shift=NONE
-CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
-CSET dcm_notes=None
-CSET dcm_phase_shift=0
-CSET dcm_pll_cascade=NONE
-CSET dcm_startup_wait=false
-CSET den_port=DEN
-CSET din_port=DIN
-CSET dout_port=DOUT
-CSET drdy_port=DRDY
-CSET dwe_port=DWE
-CSET feedback_source=FDBK_AUTO
-CSET in_freq_units=Units_MHz
-CSET in_jitter_units=Units_UI
-CSET input_clk_stopped_port=INPUT_CLK_STOPPED
-CSET jitter_options=UI
-CSET jitter_sel=No_Jitter
-CSET locked_port=LOCKED
-CSET mmcm_bandwidth=OPTIMIZED
-CSET mmcm_clkfbout_mult_f=4.000
-CSET mmcm_clkfbout_phase=0.000
-CSET mmcm_clkfbout_use_fine_ps=false
-CSET mmcm_clkin1_period=10.000
-CSET mmcm_clkin2_period=10.000
-CSET mmcm_clkout0_divide_f=4.000
-CSET mmcm_clkout0_duty_cycle=0.500
-CSET mmcm_clkout0_phase=0.000
-CSET mmcm_clkout0_use_fine_ps=false
-CSET mmcm_clkout1_divide=1
-CSET mmcm_clkout1_duty_cycle=0.500
-CSET mmcm_clkout1_phase=0.000
-CSET mmcm_clkout1_use_fine_ps=false
-CSET mmcm_clkout2_divide=1
-CSET mmcm_clkout2_duty_cycle=0.500
-CSET mmcm_clkout2_phase=0.000
-CSET mmcm_clkout2_use_fine_ps=false
-CSET mmcm_clkout3_divide=1
-CSET mmcm_clkout3_duty_cycle=0.500
-CSET mmcm_clkout3_phase=0.000
-CSET mmcm_clkout3_use_fine_ps=false
-CSET mmcm_clkout4_cascade=false
-CSET mmcm_clkout4_divide=1
-CSET mmcm_clkout4_duty_cycle=0.500
-CSET mmcm_clkout4_phase=0.000
-CSET mmcm_clkout4_use_fine_ps=false
-CSET mmcm_clkout5_divide=1
-CSET mmcm_clkout5_duty_cycle=0.500
-CSET mmcm_clkout5_phase=0.000
-CSET mmcm_clkout5_use_fine_ps=false
-CSET mmcm_clkout6_divide=1
-CSET mmcm_clkout6_duty_cycle=0.500
-CSET mmcm_clkout6_phase=0.000
-CSET mmcm_clkout6_use_fine_ps=false
-CSET mmcm_clock_hold=false
-CSET mmcm_compensation=ZHOLD
-CSET mmcm_divclk_divide=1
-CSET mmcm_notes=None
-CSET mmcm_ref_jitter1=0.010
-CSET mmcm_ref_jitter2=0.010
-CSET mmcm_startup_wait=false
-CSET num_out_clks=1
-CSET override_dcm=false
-CSET override_dcm_clkgen=false
-CSET override_mmcm=false
-CSET override_pll=false
-CSET platform=nt
-CSET pll_bandwidth=OPTIMIZED
-CSET pll_clk_feedback=CLKFBOUT
-CSET pll_clkfbout_mult=8
-CSET pll_clkfbout_phase=0.000
-CSET pll_clkin_period=20.0
-CSET pll_clkout0_divide=2
-CSET pll_clkout0_duty_cycle=0.500
-CSET pll_clkout0_phase=0.000
-CSET pll_clkout1_divide=10
-CSET pll_clkout1_duty_cycle=0.500
-CSET pll_clkout1_phase=0.000
-CSET pll_clkout2_divide=1
-CSET pll_clkout2_duty_cycle=0.500
-CSET pll_clkout2_phase=0.000
-CSET pll_clkout3_divide=1
-CSET pll_clkout3_duty_cycle=0.500
-CSET pll_clkout3_phase=0.000
-CSET pll_clkout4_divide=1
-CSET pll_clkout4_duty_cycle=0.500
-CSET pll_clkout4_phase=0.000
-CSET pll_clkout5_divide=1
-CSET pll_clkout5_duty_cycle=0.500
-CSET pll_clkout5_phase=0.000
-CSET pll_compensation=SYSTEM_SYNCHRONOUS
-CSET pll_divclk_divide=1
-CSET pll_notes=None
-CSET pll_ref_jitter=0.010
-CSET power_down_port=POWER_DOWN
-CSET prim_in_freq=50
-CSET prim_in_jitter=0.010
-CSET prim_source=No_buffer
-CSET primary_port=CLK_IN1
-CSET primitive=MMCM
-CSET primtype_sel=DCM_SP
-CSET psclk_port=PSCLK
-CSET psdone_port=PSDONE
-CSET psen_port=PSEN
-CSET psincdec_port=PSINCDEC
-CSET relative_inclk=REL_PRIMARY
-CSET reset_port=RESET
-CSET secondary_in_freq=100.000
-CSET secondary_in_jitter=0.010
-CSET secondary_port=CLK_IN2
-CSET secondary_source=Single_ended_clock_capable_pin
-CSET ss_mod_freq=250
-CSET ss_mode=CENTER_HIGH
-CSET status_port=STATUS
-CSET summary_strings=empty
-CSET use_clk_valid=true
-CSET use_clkfb_stopped=false
-CSET use_dyn_phase_shift=false
-CSET use_dyn_reconfig=false
-CSET use_freeze=false
-CSET use_freq_synth=true
-CSET use_inclk_stopped=true
-CSET use_inclk_switchover=false
-CSET use_locked=false
-CSET use_max_i_jitter=false
-CSET use_min_o_jitter=false
-CSET use_min_power=false
-CSET use_phase_alignment=true
-CSET use_power_down=false
-CSET use_reset=true
-CSET use_spread_spectrum=false
-CSET use_spread_spectrum_1=false
-CSET use_status=false
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2012-05-10T12:44:55Z
-# END Extra information
-GENERATE
-# CRC: d6857c2d
diff --git a/common/rtl/ipcore/clkmgr_dcm.xdc b/common/rtl/ipcore/clkmgr_dcm.xdc deleted file mode 100644 index 9ecc102..0000000 --- a/common/rtl/ipcore/clkmgr_dcm.xdc +++ /dev/null @@ -1,67 +0,0 @@ -# file: clkmgr_dcm.xdc
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# Input clock periods. These duplicate the values entered for the
-# input clocks. You can use these to time your system
-#----------------------------------------------------------------
-create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1]
-set_propagated_clock CLK_IN1
-set_input_jitter CLK_IN1 0.2
-
-set_false_path -from [get_ports "RESET"]
-
-# Derived clock periods. These are commented out because they are
-# automatically propogated by the tools
-# However, if you'd like to use them for module level testing, you
-# can copy them into your module level timing checks
-#-----------------------------------------------------------------
-
-#-----------------------------------------------------------------
-
-#-----------------------------------------------------------------
diff --git a/common/rtl/ipcore/clkmgr_dcm.xise b/common/rtl/ipcore/clkmgr_dcm.xise deleted file mode 100644 index 7369d3b..0000000 --- a/common/rtl/ipcore/clkmgr_dcm.xise +++ /dev/null @@ -1,74 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no" ?> -<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> - - <header> - <!-- ISE source project file created by Project Navigator. --> - <!-- --> - <!-- This file contains project source information including a list of --> - <!-- project source files, project and process properties. This file, --> - <!-- along with the project source files, is sufficient to open and --> - <!-- implement in ISE Project Navigator. --> - <!-- --> - <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> - </header> - - <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/> - - <files> - <file xil_pn:name="clkmgr_dcm.ucf" xil_pn:type="FILE_UCF"> - <association xil_pn:name="Implementation" xil_pn:seqID="0"/> - </file> - <file xil_pn:name="clkmgr_dcm.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> - <association xil_pn:name="Implementation" xil_pn:seqID="1"/> - <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/> - <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/> - <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/> - </file> - </files> - - <properties> - <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> - <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/> - <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> - <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> - <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> - <property xil_pn:name="Implementation Top" xil_pn:value="Module|clkmgr_dcm" xil_pn:valueState="non-default"/> - <property xil_pn:name="Implementation Top File" xil_pn:value="clkmgr_dcm.v" xil_pn:valueState="non-default"/> - <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clkmgr_dcm" xil_pn:valueState="non-default"/> - <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/> - <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> - <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> - <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> - <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> - <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> - <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> - <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> - <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> - <!-- --> - <!-- The following properties are for internal use only. These should not be modified.--> - <!-- --> - <property xil_pn:name="PROP_DesignName" xil_pn:value="clkmgr_dcm" xil_pn:valueState="non-default"/> - <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> - <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-02-01T08:50:04" xil_pn:valueState="non-default"/> - <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="67BEB73269CA45ADBC7997434CEC13CB" xil_pn:valueState="non-default"/> - <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> - <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> - </properties> - - <bindings> - <binding xil_pn:location="/clkmgr_dcm" xil_pn:name="clkmgr_dcm.ucf"/> - </bindings> - - <libraries/> - - <autoManagedFiles> - <!-- The following files are identified by `include statements in verilog --> - <!-- source files and are automatically managed by Project Navigator. --> - <!-- --> - <!-- Do not hand-edit this section, as it will be overwritten when the --> - <!-- project is analyzed based on files automatically identified as --> - <!-- include files. --> - </autoManagedFiles> - -</project> diff --git a/common/rtl/ipcore/clkmgr_dcm/clk_wiz_v3_6_readme.txt b/common/rtl/ipcore/clkmgr_dcm/clk_wiz_v3_6_readme.txt deleted file mode 100644 index 91dcdd0..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/clk_wiz_v3_6_readme.txt +++ /dev/null @@ -1,184 +0,0 @@ -CHANGE LOG for LogiCORE Clocking Wizard V3.6 - - Release Date: June 19, 2013 --------------------------------------------------------------------------------- - -Table of Contents - -1. INTRODUCTION -2. DEVICE SUPPORT -3. NEW FEATURE HISTORY -4. RESOLVED ISSUES -5. KNOWN ISSUES & LIMITATIONS -6. TECHNICAL SUPPORT & FEEDBACK -7. CORE RELEASE HISTORY -8. LEGAL DISCLAIMER - --------------------------------------------------------------------------------- - - -1. INTRODUCTION - -For installation instructions for this release, please go to: - - http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm - -For system requirements: - - http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm - -This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 -solution. For the latest core updates, see the product page at: - - http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ - -................................................................................ - -2. DEVICE SUPPORT - - - 2.1 ISE - - - The following device families are supported by the core for this release. - - All 7 Series devices - - - Zynq-7000 devices - Zynq-7000 - Defense Grade Zynq-7000Q (XQ) - - - All Virtex-6 devices - - - All Spartan-6 devices - - -................................................................................ - -3. NEW FEATURE HISTORY - - - 3.1 ISE - - - Spread Spectrum support for 7 series MMCME2 - - - ISE 14.2 software support - -................................................................................ - -4. RESOLVED ISSUES - - - 4.1 ISE - - Resolved issue with example design becoming core top in planAhead - - Resolved issue with Virtex6 MMCM instantiation for VHDL project - Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm - -................................................................................ - -5. KNOWN ISSUES & LIMITATIONS - - - 5.1 ISE - - - The most recent information, including known issues, workarounds, and - resolutions for this version is provided in the IP Release Notes Guide - located at - - www.xilinx.com/support/documentation/user_guides/xtp025.pdf - - -................................................................................ - -6. TECHNICAL SUPPORT & FEEDBACK - - -To obtain technical support, create a WebCase at www.xilinx.com/support. -Questions are routed to a team with expertise using this product. - -Xilinx provides technical support for use of this product when used -according to the guidelines described in the core documentation, and -cannot guarantee timing, functionality, or support of this product for -designs that do not follow specified guidelines. - - -................................................................................ - -7. CORE RELEASE HISTORY - - -Date By Version Description -================================================================================ -06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support -10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support -07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support -04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support -01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support -06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support -03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support -12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support -09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support -07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support -04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support -12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support -09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support -06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support -04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support -================================================================================ - -................................................................................ - -8. LEGAL DISCLAIMER - -(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. - -This file contains confidential and proprietary information -of Xilinx, Inc. and is protected under U.S. and -international copyright and other intellectual property -laws. - -DISCLAIMER -This disclaimer is not a license and does not grant any -rights to the materials distributed herewith. Except as -otherwise provided in a valid license issued to you by -Xilinx, and to the maximum extent permitted by applicable -law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -(2) Xilinx shall not be liable (whether in contract or tort, -including negligence, or under any other theory of -liability) for any loss or damage of any kind or nature -related to, arising under or in connection with these -materials, including for any direct, or any indirect, -special, incidental, or consequential loss or damage -(including loss of data, profits, goodwill, or any type of -loss or damage suffered as a result of any action brought -by a third party) even if such damage or loss was -reasonably foreseeable or Xilinx had been advised of the -possibility of the same. - -CRITICAL APPLICATIONS -Xilinx products are not designed or intended to be fail- -safe, or for use in any application requiring fail-safe -performance, such as life-support or safety devices or -systems, Class III medical devices, nuclear facilities, -applications related to the deployment of airbags, or any -other applications that could lead to death, personal -injury, or severe property or environmental damage -(individually and collectively, "Critical -Applications"). Customer assumes the sole risk and -liability of any use of Xilinx products in Critical -Applications, subject only to applicable laws and -regulations governing limitations on product liability. - -THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -PART OF THIS FILE AT ALL TIMES. - diff --git a/common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_readme.txt b/common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_readme.txt deleted file mode 100644 index 91dcdd0..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_readme.txt +++ /dev/null @@ -1,184 +0,0 @@ -CHANGE LOG for LogiCORE Clocking Wizard V3.6 - - Release Date: June 19, 2013 --------------------------------------------------------------------------------- - -Table of Contents - -1. INTRODUCTION -2. DEVICE SUPPORT -3. NEW FEATURE HISTORY -4. RESOLVED ISSUES -5. KNOWN ISSUES & LIMITATIONS -6. TECHNICAL SUPPORT & FEEDBACK -7. CORE RELEASE HISTORY -8. LEGAL DISCLAIMER - --------------------------------------------------------------------------------- - - -1. INTRODUCTION - -For installation instructions for this release, please go to: - - http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm - -For system requirements: - - http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm - -This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 -solution. For the latest core updates, see the product page at: - - http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ - -................................................................................ - -2. DEVICE SUPPORT - - - 2.1 ISE - - - The following device families are supported by the core for this release. - - All 7 Series devices - - - Zynq-7000 devices - Zynq-7000 - Defense Grade Zynq-7000Q (XQ) - - - All Virtex-6 devices - - - All Spartan-6 devices - - -................................................................................ - -3. NEW FEATURE HISTORY - - - 3.1 ISE - - - Spread Spectrum support for 7 series MMCME2 - - - ISE 14.2 software support - -................................................................................ - -4. RESOLVED ISSUES - - - 4.1 ISE - - Resolved issue with example design becoming core top in planAhead - - Resolved issue with Virtex6 MMCM instantiation for VHDL project - Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm - -................................................................................ - -5. KNOWN ISSUES & LIMITATIONS - - - 5.1 ISE - - - The most recent information, including known issues, workarounds, and - resolutions for this version is provided in the IP Release Notes Guide - located at - - www.xilinx.com/support/documentation/user_guides/xtp025.pdf - - -................................................................................ - -6. TECHNICAL SUPPORT & FEEDBACK - - -To obtain technical support, create a WebCase at www.xilinx.com/support. -Questions are routed to a team with expertise using this product. - -Xilinx provides technical support for use of this product when used -according to the guidelines described in the core documentation, and -cannot guarantee timing, functionality, or support of this product for -designs that do not follow specified guidelines. - - -................................................................................ - -7. CORE RELEASE HISTORY - - -Date By Version Description -================================================================================ -06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support -10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support -07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support -04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support -01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support -06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support -03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support -12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support -09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support -07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support -04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support -12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support -09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support -06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support -04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support -================================================================================ - -................................................................................ - -8. LEGAL DISCLAIMER - -(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. - -This file contains confidential and proprietary information -of Xilinx, Inc. and is protected under U.S. and -international copyright and other intellectual property -laws. - -DISCLAIMER -This disclaimer is not a license and does not grant any -rights to the materials distributed herewith. Except as -otherwise provided in a valid license issued to you by -Xilinx, and to the maximum extent permitted by applicable -law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -(2) Xilinx shall not be liable (whether in contract or tort, -including negligence, or under any other theory of -liability) for any loss or damage of any kind or nature -related to, arising under or in connection with these -materials, including for any direct, or any indirect, -special, incidental, or consequential loss or damage -(including loss of data, profits, goodwill, or any type of -loss or damage suffered as a result of any action brought -by a third party) even if such damage or loss was -reasonably foreseeable or Xilinx had been advised of the -possibility of the same. - -CRITICAL APPLICATIONS -Xilinx products are not designed or intended to be fail- -safe, or for use in any application requiring fail-safe -performance, such as life-support or safety devices or -systems, Class III medical devices, nuclear facilities, -applications related to the deployment of airbags, or any -other applications that could lead to death, personal -injury, or severe property or environmental damage -(individually and collectively, "Critical -Applications"). Customer assumes the sole risk and -liability of any use of Xilinx products in Critical -Applications, subject only to applicable laws and -regulations governing limitations on product liability. - -THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -PART OF THIS FILE AT ALL TIMES. - diff --git a/common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_vinfo.html b/common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_vinfo.html deleted file mode 100644 index d6deba0..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/doc/clk_wiz_v3_6_vinfo.html +++ /dev/null @@ -1,195 +0,0 @@ -<HTML> -<HEAD> -<TITLE>clk_wiz_v3_6_vinfo</TITLE> -<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1"> -</HEAD> -<BODY> -<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1"> -CHANGE LOG for LogiCORE Clocking Wizard V3.6 - - Release Date: June 19, 2013 --------------------------------------------------------------------------------- - -Table of Contents - -1. INTRODUCTION -2. DEVICE SUPPORT -3. NEW FEATURE HISTORY -4. RESOLVED ISSUES -5. KNOWN ISSUES & LIMITATIONS -6. TECHNICAL SUPPORT & FEEDBACK -7. CORE RELEASE HISTORY -8. LEGAL DISCLAIMER - --------------------------------------------------------------------------------- - - -1. INTRODUCTION - -For installation instructions for this release, please go to: - - <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A> - -For system requirements: - - <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A> - -This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 -solution. For the latest core updates, see the product page at: - - <A HREF="http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/">www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/</A> - -................................................................................ - -2. DEVICE SUPPORT - - - 2.1 ISE - - - The following device families are supported by the core for this release. - - All 7 Series devices - - - Zynq-7000 devices - Zynq-7000 - Defense Grade Zynq-7000Q (XQ) - - - All Virtex-6 devices - - - All Spartan-6 devices - - -................................................................................ - -3. NEW FEATURE HISTORY - - - 3.1 ISE - - - Spread Spectrum support for 7 series MMCME2 - - - ISE 14.2 software support - -................................................................................ - -4. RESOLVED ISSUES - - - 4.1 ISE - - Resolved issue with example design becoming core top in planAhead - - Resolved issue with Virtex6 MMCM instantiation for VHDL project - Please refer to AR 50719 - <A HREF="http://www.xilinx.com/support/answers/50719.htm">www.xilinx.com/support/answers/50719.htm</A> - -................................................................................ - -5. KNOWN ISSUES & LIMITATIONS - - - 5.1 ISE - - - The most recent information, including known issues, workarounds, and - resolutions for this version is provided in the IP Release Notes Guide - located at - - <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A> - - -................................................................................ - -6. TECHNICAL SUPPORT & FEEDBACK - - -To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A> -Questions are routed to a team with expertise using this product. - -Xilinx provides technical support for use of this product when used -according to the guidelines described in the core documentation, and -cannot guarantee timing, functionality, or support of this product for -designs that do not follow specified guidelines. - - -................................................................................ - -7. CORE RELEASE HISTORY - - -Date By Version Description -================================================================================ -06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support -10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support -07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support -04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support -01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support -06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support -03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support -12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support -09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support -07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support -04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support -12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support -09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support -06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support -04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support -================================================================================ - -................................................................................ - -8. LEGAL DISCLAIMER - -(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. - -This file contains confidential and proprietary information -of Xilinx, Inc. and is protected under U.S. and -international copyright and other intellectual property -laws. - -DISCLAIMER -This disclaimer is not a license and does not grant any -rights to the materials distributed herewith. Except as -otherwise provided in a valid license issued to you by -Xilinx, and to the maximum extent permitted by applicable -law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -(2) Xilinx shall not be liable (whether in contract or tort, -including negligence, or under any other theory of -liability) for any loss or damage of any kind or nature -related to, arising under or in connection with these -materials, including for any direct, or any indirect, -special, incidental, or consequential loss or damage -(including loss of data, profits, goodwill, or any type of -loss or damage suffered as a result of any action brought -by a third party) even if such damage or loss was -reasonably foreseeable or Xilinx had been advised of the -possibility of the same. - -CRITICAL APPLICATIONS -Xilinx products are not designed or intended to be fail- -safe, or for use in any application requiring fail-safe -performance, such as life-support or safety devices or -systems, Class III medical devices, nuclear facilities, -applications related to the deployment of airbags, or any -other applications that could lead to death, personal -injury, or severe property or environmental damage -(individually and collectively, "Critical -Applications"). Customer assumes the sole risk and -liability of any use of Xilinx products in Critical -Applications, subject only to applicable laws and -regulations governing limitations on product liability. - -THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -PART OF THIS FILE AT ALL TIMES. - -</FONT> -</PRE> -</BODY> -</HTML> diff --git a/common/rtl/ipcore/clkmgr_dcm/doc/pg065_clk_wiz.pdf b/common/rtl/ipcore/clkmgr_dcm/doc/pg065_clk_wiz.pdf Binary files differdeleted file mode 100644 index a7daa60..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/doc/pg065_clk_wiz.pdf +++ /dev/null diff --git a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf b/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf deleted file mode 100644 index dffb528..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.ucf +++ /dev/null @@ -1,60 +0,0 @@ -# file: clkmgr_dcm_exdes.ucf
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# Input clock periods. These duplicate the values entered for the
-# input clocks. You can use these to time your system
-#----------------------------------------------------------------
-NET "CLK_IN1" TNM_NET = "CLK_IN1";
-TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
-
-
-# FALSE PATH constraints
-PIN "COUNTER_RESET" TIG;
-PIN "RESET" TIG;
-
diff --git a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v b/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v deleted file mode 100644 index 10627b3..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.v +++ /dev/null @@ -1,164 +0,0 @@ -// file: clkmgr_dcm_exdes.v
-//
-// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-
-//----------------------------------------------------------------------------
-// Clocking wizard example design
-//----------------------------------------------------------------------------
-// This example design instantiates the created clocking network, where each
-// output clock drives a counter. The high bit of each counter is ported.
-//----------------------------------------------------------------------------
-
-`timescale 1ps/1ps
-
-module clkmgr_dcm_exdes
- #(
- parameter TCQ = 100
- )
- (// Clock in ports
- input CLK_IN1,
- // Reset that only drives logic in example design
- input COUNTER_RESET,
- output [1:1] CLK_OUT,
- // High bits of counters driven by clocks
- output COUNT,
- // Status and control signals
- input RESET,
- output INPUT_CLK_STOPPED,
- output CLK_VALID
- );
-
- // Parameters for the counters
- //-------------------------------
- // Counter width
- localparam C_W = 16;
- // Create reset for the counters
- wire reset_int = RESET || COUNTER_RESET;
-
- reg rst_sync;
- reg rst_sync_int;
- reg rst_sync_int1;
- reg rst_sync_int2;
-
-
-
- // Declare the clocks and counter
- wire clk_int;
- wire clk_n;
- wire clk;
- reg [C_W-1:0] counter;
-
- // Insert BUFGs on all input clocks that don't already have them
- //--------------------------------------------------------------
- BUFG clkin1_buf
- (.O (clk_in1_buf),
- .I (CLK_IN1));
-
- // Instantiation of the clocking network
- //--------------------------------------
- clkmgr_dcm clknetwork
- (// Clock in ports
- .CLK_IN1 (clk_in1_buf),
- // Clock out ports
- .CLK_OUT1 (clk_int),
- // Status and control signals
- .RESET (RESET),
- .INPUT_CLK_STOPPED (INPUT_CLK_STOPPED),
- .CLK_VALID (CLK_VALID));
-
- assign clk_n = ~clk;
-
- ODDR2 clkout_oddr
- (.Q (CLK_OUT[1]),
- .C0 (clk),
- .C1 (clk_n),
- .CE (1'b1),
- .D0 (1'b1),
- .D1 (1'b0),
- .R (1'b0),
- .S (1'b0));
-
- // Connect the output clocks to the design
- //-----------------------------------------
- assign clk = clk_int;
-
-
- // Reset synchronizer
- //-----------------------------------
- always @(posedge reset_int or posedge clk) begin
- if (reset_int) begin
- rst_sync <= 1'b1;
- rst_sync_int <= 1'b1;
- rst_sync_int1 <= 1'b1;
- rst_sync_int2 <= 1'b1;
- end
- else begin
- rst_sync <= 1'b0;
- rst_sync_int <= rst_sync;
- rst_sync_int1 <= rst_sync_int;
- rst_sync_int2 <= rst_sync_int1;
- end
- end
-
-
- // Output clock sampling
- //-----------------------------------
- always @(posedge clk or posedge rst_sync_int2) begin
- if (rst_sync_int2) begin
- counter <= #TCQ { C_W { 1'b 0 } };
- end else begin
- counter <= #TCQ counter + 1'b 1;
- end
- end
-
- // alias the high bit to the output
- assign COUNT = counter[C_W-1];
-
-
-
-endmodule
diff --git a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc b/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc deleted file mode 100644 index 787023d..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/example_design/clkmgr_dcm_exdes.xdc +++ /dev/null @@ -1,69 +0,0 @@ -# file: clkmgr_dcm_exdes.xdc
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# Input clock periods. These duplicate the values entered for the
-# input clocks. You can use these to time your system
-#----------------------------------------------------------------
-create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1]
-set_propagated_clock CLK_IN1
-set_input_jitter CLK_IN1 0.2
-
-# FALSE PATH constraint added on COUNTER_RESET
-set_false_path -from [get_ports "COUNTER_RESET"]
-set_false_path -from [get_ports "RESET"]
-
-# Derived clock periods. These are commented out because they are
-# automatically propogated by the tools
-# However, if you'd like to use them for module level testing, you
-# can copy them into your module level timing checks
-#-----------------------------------------------------------------
-
-#-----------------------------------------------------------------
-
-#-----------------------------------------------------------------
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/implement.bat b/common/rtl/ipcore/clkmgr_dcm/implement/implement.bat deleted file mode 100644 index 3d313d5..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/implement.bat +++ /dev/null @@ -1,90 +0,0 @@ -REM file: implement.bat
-REM
-REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-REM
-
-REM -----------------------------------------------------------------------------
-REM Script to synthesize and implement the RTL provided for the clocking wizard
-REM -----------------------------------------------------------------------------
-
-REM Clean up the results directory
-rmdir /S /Q results
-mkdir results
-
-REM Copy unisim_comp.v file to results directory
-copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\
-
-REM Synthesize the Verilog Wrapper Files
-echo 'Synthesizing Clocking Wizard design with XST'
-xst -ifn xst.scr
-move clkmgr_dcm_exdes.ngc results\
-
-REM Copy the constraints files generated by Coregen
-echo 'Copying files from constraints directory to results directory'
-copy ..\example_design\clkmgr_dcm_exdes.ucf results\
-
-cd results
-
-echo 'Running ngdbuild'
-ngdbuild -uc clkmgr_dcm_exdes.ucf clkmgr_dcm_exdes
-
-echo 'Running map'
-map -timing -pr b clkmgr_dcm_exdes -o mapped.ncd
-
-echo 'Running par'
-par -w mapped.ncd routed mapped.pcf
-
-echo 'Running trce'
-trce -e 10 routed -o routed mapped.pcf
-
-echo 'Running design through bitgen'
-bitgen -w routed
-
-echo 'Running netgen to create gate level model for the clocking wizard example design'
-netgen -ofmt verilog -sim -sdf_anno false -tm clkmgr_dcm_exdes -w routed.ncd routed.v
-cd ..
-
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/implement.sh b/common/rtl/ipcore/clkmgr_dcm/implement/implement.sh deleted file mode 100644 index 2c64bee..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/implement.sh +++ /dev/null @@ -1,91 +0,0 @@ -#!/bin/sh
-# file: implement.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-#-----------------------------------------------------------------------------
-# Script to synthesize and implement the RTL provided for the clocking wizard
-#-----------------------------------------------------------------------------
-
-# Clean up the results directory
-rm -rf results
-mkdir results
-
-# Copy unisim_comp.v file to results directory
-cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
-
-# Synthesize the Verilog Wrapper Files
-echo 'Synthesizing Clocking Wizard design with XST'
-xst -ifn xst.scr
-mv clkmgr_dcm_exdes.ngc results/
-
-# Copy the constraints files generated by Coregen
-echo 'Copying files from constraints directory to results directory'
-cp ../example_design/clkmgr_dcm_exdes.ucf results/
-
-cd results
-
-echo 'Running ngdbuild'
-ngdbuild -uc clkmgr_dcm_exdes.ucf clkmgr_dcm_exdes
-
-echo 'Running map'
-map -timing clkmgr_dcm_exdes -o mapped.ncd
-
-echo 'Running par'
-par -w mapped.ncd routed mapped.pcf
-
-echo 'Running trce'
-trce -e 10 routed -o routed mapped.pcf
-
-echo 'Running design through bitgen'
-bitgen -w routed
-
-echo 'Running netgen to create gate level model for the clocking wizard example design'
-netgen -ofmt verilog -sim -sdf_anno false -tm clkmgr_dcm_exdes -w routed.ncd routed.v
-
-cd ..
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.bat b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.bat deleted file mode 100644 index 9782028..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.bat +++ /dev/null @@ -1,58 +0,0 @@ -REM file: planAhead_ise.bat
-REM
-REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-REM
-
-REM-----------------------------------------------------------------------------
-REM Script to synthesize and implement the RTL provided for the clocking wizard
-REM-----------------------------------------------------------------------------
-
-del \f results
-mkdir results
-cd results
-
-planAhead -mode batch -source ..\planAhead_ise.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.sh b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.sh deleted file mode 100644 index 7f436b6..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.sh +++ /dev/null @@ -1,59 +0,0 @@ -#!/bin/sh
-# file: planAhead_ise.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-#-----------------------------------------------------------------------------
-# Script to synthesize and implement the RTL provided for the clocking wizard
-#-----------------------------------------------------------------------------
-
-rm -rf results
-mkdir results
-cd results
-
-planAhead -mode batch -source ../planAhead_ise.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.tcl b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.tcl deleted file mode 100644 index ab77638..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_ise.tcl +++ /dev/null @@ -1,78 +0,0 @@ -# file: planAhead_ise.tcl
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-set projDir [file dirname [info script]]
-set projName clkmgr_dcm
-set topName clkmgr_dcm_exdes
-set device xc6slx45csg324-3
-
-create_project $projName $projDir/results/$projName -part $device
-
-set_property design_mode RTL [get_filesets sources_1]
-
-## Source files
-#set verilogSources [glob $srcDir/*.v]
-import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/clkmgr_dcm_exdes.v
-import_files -fileset [get_filesets sources_1] -force -norecurse ../../../clkmgr_dcm.v
-
-
-#UCF file
-import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/clkmgr_dcm_exdes.ucf
-
-set_property top $topName [get_property srcset [current_run]]
-
-launch_runs -runs synth_1
-wait_on_run synth_1
-
-set_property add_step Bitgen [get_runs impl_1]
-launch_runs -runs impl_1
-wait_on_run impl_1
-
-
-
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.bat b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.bat deleted file mode 100644 index 3e1e03b..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.bat +++ /dev/null @@ -1,58 +0,0 @@ -REM file: planAhead_rdn.sh
-REM
-REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-REM
-
-REM-----------------------------------------------------------------------------
-REM Script to synthesize and implement the RTL provided for the XADC wizard
-REM-----------------------------------------------------------------------------
-
-del \f results
-mkdir results
-cd results
-
-planAhead -mode batch -source ..\planAhead_rdn.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.sh b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.sh deleted file mode 100644 index a5adee8..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.sh +++ /dev/null @@ -1,57 +0,0 @@ -#!/bin/sh
-# file: planAhead_rdn.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-#-----------------------------------------------------------------------------
-# Script to synthesize and implement the RTL provided for the XADC wizard
-#-----------------------------------------------------------------------------
-rm -rf results
-mkdir results
-cd results
-planAhead -mode batch -source ../planAhead_rdn.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl b/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl deleted file mode 100644 index e8c0fdf..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/planAhead_rdn.tcl +++ /dev/null @@ -1,69 +0,0 @@ -# file : planAhead_rdn.tcl
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-set device xc6slx45csg324-3
-set projName clkmgr_dcm
-set design clkmgr_dcm
-set projDir [file dirname [info script]]
-create_project $projName $projDir/results/$projName -part $device -force
-set_property design_mode RTL [current_fileset -srcset]
-set top_module clkmgr_dcm_exdes
-set_property top clkmgr_dcm_exdes [get_property srcset [current_run]]
-add_files -norecurse {../../../clkmgr_dcm.v}
-add_files -norecurse {../../example_design/clkmgr_dcm_exdes.v}
-import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/clkmgr_dcm_exdes.xdc}
-synth_design
-opt_design
-place_design
-route_design
-write_sdf -rename_top_module clkmgr_dcm_exdes -file routed.sdf
-write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module clkmgr_dcm_exdes -file routed.v
-report_timing -nworst 30 -path_type full -file routed.twr
-report_drc -file report.drc
-write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/xst.prj b/common/rtl/ipcore/clkmgr_dcm/implement/xst.prj deleted file mode 100644 index cd0e0e6..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/xst.prj +++ /dev/null @@ -1,2 +0,0 @@ -verilog work ../../clkmgr_dcm.v
-verilog work ../example_design/clkmgr_dcm_exdes.v
diff --git a/common/rtl/ipcore/clkmgr_dcm/implement/xst.scr b/common/rtl/ipcore/clkmgr_dcm/implement/xst.scr deleted file mode 100644 index 20d09f4..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/implement/xst.scr +++ /dev/null @@ -1,9 +0,0 @@ -run
--ifmt MIXED
--top clkmgr_dcm_exdes
--p xc6slx45-csg324-3
--ifn xst.prj
--ofn clkmgr_dcm_exdes
--keep_hierarchy soft
--equivalent_register_removal no
--max_fanout 65535
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v b/common/rtl/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v deleted file mode 100644 index ee24750..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/clkmgr_dcm_tb.v +++ /dev/null @@ -1,145 +0,0 @@ -// file: clkmgr_dcm_tb.v
-//
-// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-
-//----------------------------------------------------------------------------
-// Clocking wizard demonstration testbench
-//----------------------------------------------------------------------------
-// This demonstration testbench instantiates the example design for the
-// clocking wizard. Input clocks are toggled, which cause the clocking
-// network to lock and the counters to increment.
-//----------------------------------------------------------------------------
-
-`timescale 1ps/1ps
-
-`define wait_lock @(posedge CLK_VALID)
-
-module clkmgr_dcm_tb ();
-
- // Clock to Q delay of 100ps
- localparam TCQ = 100;
-
-
- // timescale is 1ps/1ps
- localparam ONE_NS = 1000;
- localparam PHASE_ERR_MARGIN = 100; // 100ps
- // how many cycles to run
- localparam COUNT_PHASE = 1024;
- // we'll be using the period in many locations
- localparam time PER1 = 20.0*ONE_NS;
- localparam time PER1_1 = PER1/2;
- localparam time PER1_2 = PER1 - PER1/2;
-
- // Declare the input clock signals
- reg CLK_IN1 = 1;
-
- // The high bit of the sampling counter
- wire COUNT;
- // Status and control signals
- reg RESET = 0;
- wire INPUT_CLK_STOPPED;
- wire CLK_VALID;
- reg COUNTER_RESET = 0;
-wire [1:1] CLK_OUT;
-//Freq Check using the M & D values setting and actual Frequency generated
-
-
- // Input clock generation
- //------------------------------------
- always begin
- CLK_IN1 = #PER1_1 ~CLK_IN1;
- CLK_IN1 = #PER1_2 ~CLK_IN1;
- end
-
- // Test sequence
- reg [15*8-1:0] test_phase = "";
- initial begin
- // Set up any display statements using time to be readable
- $timeformat(-12, 2, "ps", 10);
- COUNTER_RESET = 0;
- test_phase = "reset";
- RESET = 1;
- #(PER1*6);
- RESET = 0;
- test_phase = "wait lock";
- `wait_lock;
- #(PER1*6);
- COUNTER_RESET = 1;
- #(PER1*20)
- COUNTER_RESET = 0;
-
- test_phase = "counting";
- #(PER1*COUNT_PHASE);
-
- $display("SIMULATION PASSED");
- $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
- $finish;
- end
-
- // Instantiation of the example design containing the clock
- // network and sampling counters
- //---------------------------------------------------------
- clkmgr_dcm_exdes
- #(
- .TCQ (TCQ)
- ) dut
- (// Clock in ports
- .CLK_IN1 (CLK_IN1),
- // Reset for logic in example design
- .COUNTER_RESET (COUNTER_RESET),
- .CLK_OUT (CLK_OUT),
- // High bits of the counters
- .COUNT (COUNT),
- // Status and control signals
- .RESET (RESET),
- .INPUT_CLK_STOPPED (INPUT_CLK_STOPPED),
- .CLK_VALID (CLK_VALID));
-
-// Freq Check
-
-endmodule
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl deleted file mode 100644 index e19ead8..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simcmds.tcl +++ /dev/null @@ -1,8 +0,0 @@ -# file: simcmds.tcl
-
-# create the simulation script
-vcd dumpfile isim.vcd
-vcd dumpvars -m /clkmgr_dcm_tb -l 0
-wave add /
-run 50000ns
-quit
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat deleted file mode 100644 index 80904cb..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.bat +++ /dev/null @@ -1,59 +0,0 @@ -REM file: simulate_isim.bat
-REM
-REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-REM
-
-vlogcomp -work work %XILINX%\verilog\src\glbl.v
-vlogcomp -work work ..\..\..\clkmgr_dcm.v
-vlogcomp -work work ..\..\example_design\clkmgr_dcm_exdes.v
-vlogcomp -work work ..\clkmgr_dcm_tb.v
-
-REM compile the project
-fuse work.clkmgr_dcm_tb work.glbl -L unisims_ver -o clkmgr_dcm_isim.exe
-
-REM run the simulation script
-.\clkmgr_dcm_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh deleted file mode 100644 index 9fb5029..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_isim.sh +++ /dev/null @@ -1,61 +0,0 @@ -# file: simulate_isim.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# nt
-# create the project
-vlogcomp -work work ${XILINX}/verilog/src/glbl.v
-vlogcomp -work work ../../../clkmgr_dcm.v
-vlogcomp -work work ../../example_design/clkmgr_dcm_exdes.v
-vlogcomp -work work ../clkmgr_dcm_tb.v
-
-# compile the project
-fuse work.clkmgr_dcm_tb work.glbl -L unisims_ver -o clkmgr_dcm_isim.exe
-
-# run the simulation script
-./clkmgr_dcm_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat deleted file mode 100644 index 7497cd9..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.bat +++ /dev/null @@ -1,61 +0,0 @@ -REM file: simulate_mti.bat
-REM
-REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-REM
-
-REM set up the working directory
-vlib work
-
-REM compile all of the files
-vlog -work work %XILINX%\verilog\src\glbl.v
-vlog -work work ..\..\..\clkmgr_dcm.v
-vlog -work work ..\..\example_design\clkmgr_dcm_exdes.v
-vlog -work work ..\clkmgr_dcm_tb.v
-
-REM run the simulation
-vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.clkmgr_dcm_tb work.glbl
-
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do deleted file mode 100644 index b0e526f..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.do +++ /dev/null @@ -1,65 +0,0 @@ -# file: simulate_mti.do
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# set up the working directory
-set work work
-vlib work
-
-# compile all of the files
-vlog -work work $env(XILINX)/verilog/src/glbl.v
-vlog -work work ../../../clkmgr_dcm.v
-vlog -work work ../../example_design/clkmgr_dcm_exdes.v
-vlog -work work ../clkmgr_dcm_tb.v
-
-# run the simulation
-vsim -t ps -voptargs="+acc" -L unisims_ver work.clkmgr_dcm_tb work.glbl
-do wave.do
-log clkmgr_dcm_tb/dut/counter
-log -r /*
-run 50000ns
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh deleted file mode 100644 index 66099e0..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_mti.sh +++ /dev/null @@ -1,61 +0,0 @@ -#/bin/sh
-# file: simulate_mti.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-# set up the working directory
-set work work
-vlib work
-
-# compile all of the files
-vlog -work work $XILINX/verilog/src/glbl.v
-vlog -work work ../../../clkmgr_dcm.v
-vlog -work work ../../example_design/clkmgr_dcm_exdes.v
-vlog -work work ../clkmgr_dcm_tb.v
-
-# run the simulation
-vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.clkmgr_dcm_tb work.glbl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh deleted file mode 100644 index 01b0412..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_ncsim.sh +++ /dev/null @@ -1,62 +0,0 @@ -#/bin/sh
-# file: simulate_ncsim.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# set up the working directory
-mkdir work
-
-# compile all of the files
-ncvlog -work work ${XILINX}/verilog/src/glbl.v
-ncvlog -work work ../../../clkmgr_dcm.v
-ncvlog -work work ../../example_design/clkmgr_dcm_exdes.v
-ncvlog -work work ../clkmgr_dcm_tb.v
-
-# elaborate and run the simulation
-ncelab -work work -access +wc work.clkmgr_dcm_tb work.glbl
-ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.clkmgr_dcm_tb
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh deleted file mode 100644 index 39668df..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/simulate_vcs.sh +++ /dev/null @@ -1,72 +0,0 @@ -#!/bin/sh
-# file: simulate_vcs.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# remove old files
-rm -rf simv* csrc DVEfiles AN.DB
-
-# compile all of the files
-# Note that -sverilog is not strictly required- You can
-# remove the -sverilog if you change the type of the
-# localparam for the periods in the testbench file to
-# [63:0] from time
-vlogan -sverilog \
- ${XILINX}/verilog/src/glbl.v \
- ../../../clkmgr_dcm.v \
- ../../example_design/clkmgr_dcm_exdes.v \
- ../clkmgr_dcm_tb.v
-
-# prepare the simulation
-vcs +vcs+lic+wait -debug clkmgr_dcm_tb glbl
-
-# run the simulation
-./simv -ucli -i ucli_commands.key
-
-# launch the viewer
-dve -vpd vcdplus.vpd -session vcs_session.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key deleted file mode 100644 index 2bbdd0f..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/ucli_commands.key +++ /dev/null @@ -1,5 +0,0 @@ -call {$vcdpluson}
-call {$vcdplusmemon(clkmgr_dcm_tb.dut.counter)}
-run
-call {$vcdplusclose}
-quit
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl deleted file mode 100644 index 628e55a..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/vcs_session.tcl +++ /dev/null @@ -1,18 +0,0 @@ -gui_open_window Wave
-gui_sg_create clkmgr_dcm_group
-gui_list_add_group -id Wave.1 {clkmgr_dcm_group}
-gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.test_phase}
-gui_set_radix -radix {ascii} -signals {clkmgr_dcm_tb.test_phase}
-gui_sg_addsignal -group clkmgr_dcm_group {{Input_clocks}} -divider
-gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.CLK_IN1}
-gui_sg_addsignal -group clkmgr_dcm_group {{Output_clocks}} -divider
-gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.dut.clk}
-gui_list_expand -id Wave.1 clkmgr_dcm_tb.dut.clk
-gui_sg_addsignal -group clkmgr_dcm_group {{Status_control}} -divider
-gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.RESET}
-gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.USE_INCLK_STOPPED}
-gui_sg_addsignal -group clkmgr_dcm_group {{Counters}} -divider
-gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.COUNT}
-gui_sg_addsignal -group clkmgr_dcm_group {clkmgr_dcm_tb.dut.counter}
-gui_list_expand -id Wave.1 clkmgr_dcm_tb.dut.counter
-gui_zoom -window Wave.1 -full
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.do b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.do deleted file mode 100644 index eee7422..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.do +++ /dev/null @@ -1,60 +0,0 @@ -# file: wave.do
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-add wave -noupdate -format Literal -radix ascii /clkmgr_dcm_tb/test_phase
-add wave -noupdate -divider {Input clocks}
-add wave -noupdate -format Logic /clkmgr_dcm_tb/CLK_IN1
-add wave -noupdate -divider {Output clocks}
-add wave -noupdate -format Logic /clkmgr_dcm_tb/dut/clk
-add wave -noupdate -divider Status/control
-add wave -noupdate -format Logic /clkmgr_dcm_tb/RESET
-add wave -noupdate -format Logic /clkmgr_dcm_tb/INPUT_CLK_STOPPED
-add wave -noupdate -divider Counters
-add wave -noupdate -format Literal -radix hexadecimal /clkmgr_dcm_tb/COUNT
-add wave -noupdate -format Literal -radix hexadecimal /clkmgr_dcm_tb/dut/counter
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.sv b/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.sv deleted file mode 100644 index c3c3eef..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/functional/wave.sv +++ /dev/null @@ -1,118 +0,0 @@ -# file: wave.sv
-#
-# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-# Get the windows set up
-#
-if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} {
- window geometry "Design Browser 1" 1054x819+536+322
-}
-window target "Design Browser 1" on
-browser using {Design Browser 1}
-browser set \
- -scope nc::clkmgr_dcm_tb
-browser yview see nc::clkmgr_dcm_tb
-browser timecontrol set -lock 0
-
-if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} {
- window geometry "Waveform 1" 1010x600+0+541
-}
-window target "Waveform 1" on
-waveform using {Waveform 1}
-waveform sidebar visibility partial
-waveform set \
- -primarycursor TimeA \
- -signalnames name \
- -signalwidth 175 \
- -units ns \
- -valuewidth 75
-cursor set -using TimeA -time 0
-waveform baseline set -time 0
-waveform xview limits 0 20000n
-
-#
-# Define signal groups
-#
-catch {group new -name {Output clocks} -overlay 0}
-catch {group new -name {Status/control} -overlay 0}
-catch {group new -name {Counters} -overlay 0}
-
-set id [waveform add -signals [list {nc::clkmgr_dcm_tb.CLK_IN1}]]
-
-group using {Output clocks}
-group set -overlay 0
-group set -comment {}
-group clear 0 end
-
-group insert \
- {clkmgr_dcm_tb.dut.clk} \
-
-group using {Counters}
-group set -overlay 0
-group set -comment {}
-group clear 0 end
-
-group insert \
- {clkmgr_dcm_tb.dut.counter} \
-
-group using {Status/control}
-group set -overlay 0
-group set -comment {}
-group clear 0 end
-
-group insert \
- {nc::clkmgr_dcm_tb.RESET} {nc::clkmgr_dcm_tb.INPUT_CLK_STOPPED}
-
-set id [waveform add -signals [list {nc::clkmgr_dcm_tb.COUNT} ]]
-
-set id [waveform add -signals [list {nc::clkmgr_dcm_tb.test_phase} ]]
-waveform format $id -radix %a
-
-set groupId [waveform add -groups {{Input clocks}}]
-set groupId [waveform add -groups {{Output clocks}}]
-set groupId [waveform add -groups {{Status/control}}]
-set groupId [waveform add -groups {{Counters}}]
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v deleted file mode 100644 index 9618253..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/clkmgr_dcm_tb.v +++ /dev/null @@ -1,149 +0,0 @@ -// file: clkmgr_dcm_tb.v
-//
-// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-
-//----------------------------------------------------------------------------
-// Clocking wizard demonstration testbench
-//----------------------------------------------------------------------------
-// This demonstration testbench instantiates the example design for the
-// clocking wizard. Input clocks are toggled, which cause the clocking
-// network to lock and the counters to increment.
-//----------------------------------------------------------------------------
-
-`timescale 1ps/1ps
-
-`define wait_lock @(posedge CLK_VALID)
-
-module clkmgr_dcm_tb ();
-
- // Clock to Q delay of 100ps
- localparam TCQ = 100;
-
-
- // timescale is 1ps/1ps
- localparam ONE_NS = 1000;
- localparam PHASE_ERR_MARGIN = 100; // 100ps
- // how many cycles to run
- localparam COUNT_PHASE = 1024;
- // we'll be using the period in many locations
- localparam time PER1 = 20.0*ONE_NS;
- localparam time PER1_1 = PER1/2;
- localparam time PER1_2 = PER1 - PER1/2;
-
- // Declare the input clock signals
- reg CLK_IN1 = 1;
-
- // The high bit of the sampling counter
- wire COUNT;
- // Status and control signals
- reg RESET = 0;
- wire INPUT_CLK_STOPPED;
- wire CLK_VALID;
- reg COUNTER_RESET = 0;
-wire [1:1] CLK_OUT;
-//Freq Check using the M & D values setting and actual Frequency generated
-
- reg [13:0] timeout_counter = 14'b00000000000000;
-
- // Input clock generation
- //------------------------------------
- always begin
- CLK_IN1 = #PER1_1 ~CLK_IN1;
- CLK_IN1 = #PER1_2 ~CLK_IN1;
- end
-
- // Test sequence
- reg [15*8-1:0] test_phase = "";
- initial begin
- // Set up any display statements using time to be readable
- $timeformat(-12, 2, "ps", 10);
- $display ("Timing checks are not valid");
- COUNTER_RESET = 0;
- test_phase = "reset";
- RESET = 1;
- #(PER1*6);
- RESET = 0;
- test_phase = "wait lock";
- `wait_lock;
- #(PER1*6);
- COUNTER_RESET = 1;
- #(PER1*19.5)
- COUNTER_RESET = 0;
- #(PER1*1)
- $display ("Timing checks are valid");
- test_phase = "counting";
- #(PER1*COUNT_PHASE);
-
- $display("SIMULATION PASSED");
- $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
- $finish;
- end
-
-
-
- // Instantiation of the example design containing the clock
- // network and sampling counters
- //---------------------------------------------------------
- clkmgr_dcm_exdes
- dut
- (// Clock in ports
- .CLK_IN1 (CLK_IN1),
- // Reset for logic in example design
- .COUNTER_RESET (COUNTER_RESET),
- .CLK_OUT (CLK_OUT),
- // High bits of the counters
- .COUNT (COUNT),
- // Status and control signals
- .RESET (RESET),
- .INPUT_CLK_STOPPED (INPUT_CLK_STOPPED),
- .CLK_VALID (CLK_VALID));
-
-
-// Freq Check
-
-endmodule
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file deleted file mode 100644 index d59e315..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/sdf_cmd_file +++ /dev/null @@ -1,2 +0,0 @@ -COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X",
-SCOPE = clkmgr_dcm_tb.dut;
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl deleted file mode 100644 index 14523af..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simcmds.tcl +++ /dev/null @@ -1,9 +0,0 @@ -# file: simcmds.tcl
-
-# create the simulation script
-vcd dumpfile isim.vcd
-vcd dumpvars -m /clkmgr_dcm_tb -l 0
-wave add /
-run 50000ns
-quit
-
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh deleted file mode 100644 index 0152cb0..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_isim.sh +++ /dev/null @@ -1,62 +0,0 @@ -# file: simulate_isim.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# create the project
-vlogcomp -work work ${XILINX}/verilog/src/glbl.v
-vlogcomp -work work ../../implement/results/routed.v
-vlogcomp -work work clkmgr_dcm_tb.v
-
-# compile the project
-fuse work.clkmgr_dcm_tb work.glbl -L secureip -L simprims_ver -o clkmgr_dcm_isim.exe
-
-# run the simulation script
-./clkmgr_dcm_isim.exe -tclbatch simcmds.tcl -sdfmax /clkmgr_dcm_tb/dut=../../implement/results/routed.sdf
-
-# run the simulation script
-#./clkmgr_dcm_isim.exe -gui -tclbatch simcmds.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat deleted file mode 100644 index 8a08dc0..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.bat +++ /dev/null @@ -1,59 +0,0 @@ -REM file: simulate_mti.bat
-REM
-REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-REM
-# set up the working directory
-set work work
-vlib work
-
-REM compile all of the files
-vlog -work work %XILINX%\verilog\src\glbl.v
-vlog -work work ..\..\implement\results\routed.v
-vlog -work work clkmgr_dcm_tb.v
-
-REM run the simulation
-vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clkmgr_dcm_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.clkmgr_dcm_tb work.glbl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do deleted file mode 100644 index bfeb9c5..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.do +++ /dev/null @@ -1,65 +0,0 @@ -# file: simulate_mti.do
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# set up the working directory
-set work work
-vlib work
-
-# compile all of the files
-vlog -work work $env(XILINX)/verilog/src/glbl.v
-vlog -work work ../../implement/results/routed.v
-vlog -work work clkmgr_dcm_tb.v
-
-# run the simulation
-vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clkmgr_dcm_tb/dut=../../implement/results/routed.sdf +no_notifier work.clkmgr_dcm_tb work.glbl
-#do wave.do
-#log -r /*
-run 50000ns
-
-
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh deleted file mode 100644 index b842adc..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_mti.sh +++ /dev/null @@ -1,61 +0,0 @@ -#/bin/sh
-# file: simulate_mti.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# set up the working directory
-set work work
-vlib work
-
-# compile all of the files
-vlog -work work $XILINX/verilog/src/glbl.v
-vlog -work work ../../implement/results/routed.v
-vlog -work work clkmgr_dcm_tb.v
-
-# run the simulation
-vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax clkmgr_dcm_tb/dut=../../implement/results/routed.sdf +no_notifier work.clkmgr_dcm_tb work.glbl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh deleted file mode 100644 index fd18dde..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_ncsim.sh +++ /dev/null @@ -1,64 +0,0 @@ -#!/bin/sh
-# file: simulate_ncsim.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# set up the working directory
-mkdir work
-
-# compile all of the files
-ncvlog -work work ${XILINX}/verilog/src/glbl.v
-ncvlog -work work ../../implement/results/routed.v
-ncvlog -work work clkmgr_dcm_tb.v
-
-# elaborate and run the simulation
-ncsdfc ../../implement/results/routed.sdf
-
-ncelab -work work -access +wc -pulse_r 10 -nonotifier work.clkmgr_dcm_tb work.glbl -sdf_cmd_file sdf_cmd_file
-ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.clkmgr_dcm_tb
-
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh deleted file mode 100644 index 26a8c27..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/simulate_vcs.sh +++ /dev/null @@ -1,72 +0,0 @@ -#!/bin/sh
-# file: simulate_vcs.sh
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# remove old files
-rm -rf simv* csrc DVEfiles AN.DB
-
-# compile all of the files
-# Note that -sverilog is not strictly required- You can
-# remove the -sverilog if you change the type of the
-# localparam for the periods in the testbench file to
-# [63:0] from time
- vlogan -sverilog \
- clkmgr_dcm_tb.v \
- ../../implement/results/routed.v
-
-
-# prepare the simulation
-vcs -sdf max:clkmgr_dcm_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \
- +libext+.v -debug clkmgr_dcm_tb.v ../../implement/results/routed.v
-
-# run the simulation
-./simv -ucli -i ucli_commands.key
-
-# launch the viewer
-#dve -vpd vcdplus.vpd -session vcs_session.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key deleted file mode 100644 index b32669e..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/ucli_commands.key +++ /dev/null @@ -1,5 +0,0 @@ -
-call {$vcdpluson}
-run 50000ns
-call {$vcdplusclose}
-quit
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl deleted file mode 100644 index 6cc6e24..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/vcs_session.tcl +++ /dev/null @@ -1 +0,0 @@ -gui_open_window Wave
diff --git a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/wave.do b/common/rtl/ipcore/clkmgr_dcm/simulation/timing/wave.do deleted file mode 100644 index 7cc804b..0000000 --- a/common/rtl/ipcore/clkmgr_dcm/simulation/timing/wave.do +++ /dev/null @@ -1,71 +0,0 @@ -# file: wave.do
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate /clkmgr_dcm_tb/CLK_IN1
-add wave -noupdate /clkmgr_dcm_tb/COUNT
-add wave -noupdate /clkmgr_dcm_tb/RESET
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {3223025 ps} 0}
-configure wave -namecolwidth 238
-configure wave -valuecolwidth 107
-configure wave -justifyvalue left
-configure wave -signalnamewidth 0
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ps
-update
-WaveRestoreZoom {0 ps} {74848022 ps}
diff --git a/common/rtl/ipcore/clkmgr_dcm_flist.txt b/common/rtl/ipcore/clkmgr_dcm_flist.txt deleted file mode 100644 index bd1b2cd..0000000 --- a/common/rtl/ipcore/clkmgr_dcm_flist.txt +++ /dev/null @@ -1,54 +0,0 @@ -# Output products list for <clkmgr_dcm>
-_xmsgs\pn_parser.xmsgs
-clkmgr_dcm.asy
-clkmgr_dcm.gise
-clkmgr_dcm.ucf
-clkmgr_dcm.v
-clkmgr_dcm.veo
-clkmgr_dcm.xco
-clkmgr_dcm.xdc
-clkmgr_dcm.xise
-clkmgr_dcm\clk_wiz_v3_6_readme.txt
-clkmgr_dcm\doc\clk_wiz_v3_6_readme.txt
-clkmgr_dcm\doc\clk_wiz_v3_6_vinfo.html
-clkmgr_dcm\doc\pg065_clk_wiz.pdf
-clkmgr_dcm\example_design\clkmgr_dcm_exdes.ucf
-clkmgr_dcm\example_design\clkmgr_dcm_exdes.v
-clkmgr_dcm\example_design\clkmgr_dcm_exdes.xdc
-clkmgr_dcm\implement\implement.bat
-clkmgr_dcm\implement\implement.sh
-clkmgr_dcm\implement\planAhead_ise.bat
-clkmgr_dcm\implement\planAhead_ise.sh
-clkmgr_dcm\implement\planAhead_ise.tcl
-clkmgr_dcm\implement\planAhead_rdn.bat
-clkmgr_dcm\implement\planAhead_rdn.sh
-clkmgr_dcm\implement\planAhead_rdn.tcl
-clkmgr_dcm\implement\xst.prj
-clkmgr_dcm\implement\xst.scr
-clkmgr_dcm\simulation\clkmgr_dcm_tb.v
-clkmgr_dcm\simulation\functional\simcmds.tcl
-clkmgr_dcm\simulation\functional\simulate_isim.bat
-clkmgr_dcm\simulation\functional\simulate_isim.sh
-clkmgr_dcm\simulation\functional\simulate_mti.bat
-clkmgr_dcm\simulation\functional\simulate_mti.do
-clkmgr_dcm\simulation\functional\simulate_mti.sh
-clkmgr_dcm\simulation\functional\simulate_ncsim.sh
-clkmgr_dcm\simulation\functional\simulate_vcs.sh
-clkmgr_dcm\simulation\functional\ucli_commands.key
-clkmgr_dcm\simulation\functional\vcs_session.tcl
-clkmgr_dcm\simulation\functional\wave.do
-clkmgr_dcm\simulation\functional\wave.sv
-clkmgr_dcm\simulation\timing\clkmgr_dcm_tb.v
-clkmgr_dcm\simulation\timing\sdf_cmd_file
-clkmgr_dcm\simulation\timing\simcmds.tcl
-clkmgr_dcm\simulation\timing\simulate_isim.sh
-clkmgr_dcm\simulation\timing\simulate_mti.bat
-clkmgr_dcm\simulation\timing\simulate_mti.do
-clkmgr_dcm\simulation\timing\simulate_mti.sh
-clkmgr_dcm\simulation\timing\simulate_ncsim.sh
-clkmgr_dcm\simulation\timing\simulate_vcs.sh
-clkmgr_dcm\simulation\timing\ucli_commands.key
-clkmgr_dcm\simulation\timing\vcs_session.tcl
-clkmgr_dcm\simulation\timing\wave.do
-clkmgr_dcm_flist.txt
-clkmgr_dcm_xmdf.tcl
diff --git a/common/rtl/ipcore/clkmgr_dcm_xmdf.tcl b/common/rtl/ipcore/clkmgr_dcm_xmdf.tcl deleted file mode 100644 index 307029b..0000000 --- a/common/rtl/ipcore/clkmgr_dcm_xmdf.tcl +++ /dev/null @@ -1,140 +0,0 @@ -# The package naming convention is <core_name>_xmdf
-package provide clkmgr_dcm_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is <core_name>_xmdf
-namespace eval ::clkmgr_dcm_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::clkmgr_dcm_xmdf::xmdfInit { instance } {
-# Variable containg name of library into which module is compiled
-# Recommendation: <module_name>
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name clkmgr_dcm
-}
-# ::clkmgr_dcm_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::clkmgr_dcm_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be magically
-# available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/clk_wiz_readme.txt
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/doc/clk_wiz_ds709.pdf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/doc/clk_wiz_gsg521.pdf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/implement/implement.bat
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/implement/implement.sh
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/implement/xst.prj
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/implement/xst.scr
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/clkmgr_dcm_tb.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/simcmds.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/simulate_isim.sh
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/simulate_mti.do
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/simulate_ncsim.sh
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/simulate_vcs.sh
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/ucli_commands.key
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/vcs_session.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/wave.do
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm/simulation/functional/wave.sv
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm.asy
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm.ejp
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm.ucf
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm.veo
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkmgr_dcm_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module clkmgr_dcm
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/common/rtl/ipcore/coregen.cgp b/common/rtl/ipcore/coregen.cgp deleted file mode 100644 index 8bc2e70..0000000 --- a/common/rtl/ipcore/coregen.cgp +++ /dev/null @@ -1,9 +0,0 @@ -SET busformat = BusFormatAngleBracketNotRipped -SET designentry = Verilog -SET device = xc6slx45 -SET devicefamily = spartan6 -SET flowvendor = Other -SET package = csg324 -SET speedgrade = -3 -SET verilogsim = true -SET vhdlsim = false diff --git a/common/rtl/ipcore/create_clkmgr_dcm.tcl b/common/rtl/ipcore/create_clkmgr_dcm.tcl deleted file mode 100644 index fec8dec..0000000 --- a/common/rtl/ipcore/create_clkmgr_dcm.tcl +++ /dev/null @@ -1,37 +0,0 @@ -##
-## Core Generator Run Script, generator for Project Navigator create command
-##
-
-proc findRtfPath { relativePath } {
- set xilenv ""
- if { [info exists ::env(XILINX) ] } {
- if { [info exists ::env(MYXILINX)] } {
- set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
- } else {
- set xilenv $::env(XILINX)
- }
- }
- foreach path [ split $xilenv $::xilinx::path_sep ] {
- set fullPath [ file join $path $relativePath ]
- if { [ file exists $fullPath ] } {
- return $fullPath
- }
- }
- return ""
-}
-
-source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
-
-set result [ run_cg_create "xilinx.com:ip:clk_wiz:3.6" "clkmgr_dcm" "Clocking Wizard" "Clocking Wizard (xilinx.com:ip:clk_wiz:3.6) generated by Project Navigator" xc6slx45-3csg324 Verilog ]
-
-if { $result == 0 } {
- puts "Core Generator create command completed successfully."
-} elseif { $result == 1 } {
- puts "Core Generator create command failed."
-} elseif { $result == 3 || $result == 4 } {
- # convert 'version check' result to real return range, bypassing any messages.
- set result [ expr $result - 3 ]
-} else {
- puts "Core Generator create cancelled."
-}
-exit $result
diff --git a/common/rtl/ipcore/edit_clkmgr_dcm.tcl b/common/rtl/ipcore/edit_clkmgr_dcm.tcl deleted file mode 100644 index 4992eb1..0000000 --- a/common/rtl/ipcore/edit_clkmgr_dcm.tcl +++ /dev/null @@ -1,37 +0,0 @@ -##
-## Core Generator Run Script, generator for Project Navigator edit command
-##
-
-proc findRtfPath { relativePath } {
- set xilenv ""
- if { [info exists ::env(XILINX) ] } {
- if { [info exists ::env(MYXILINX)] } {
- set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
- } else {
- set xilenv $::env(XILINX)
- }
- }
- foreach path [ split $xilenv $::xilinx::path_sep ] {
- set fullPath [ file join $path $relativePath ]
- if { [ file exists $fullPath ] } {
- return $fullPath
- }
- }
- return ""
-}
-
-source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
-
-set result [ run_cg_edit "clkmgr_dcm" xc6slx45-3csg324 Verilog ]
-
-if { $result == 0 } {
- puts "Core Generator edit command completed successfully."
-} elseif { $result == 1 } {
- puts "Core Generator edit command failed."
-} elseif { $result == 3 || $result == 4 } {
- # convert 'version check' result to real return range, bypassing any messages.
- set result [ expr $result - 3 ]
-} else {
- puts "Core Generator edit cancelled."
-}
-exit $result
diff --git a/common/rtl/lint-dummy.v b/common/rtl/lint-dummy.v new file mode 100644 index 0000000..9d4d2d3 --- /dev/null +++ b/common/rtl/lint-dummy.v @@ -0,0 +1,125 @@ +// dummy modules for Xilinx IP for verilator linting + +// The module definitions are ganked from +// /opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/unisims. It would be easier +// to run verilator with -I for that directory, but verilator really +// doesn't like the Xilinx code. + +/*verilator lint_off UNDRIVEN*/ +/*verilator lint_off UNUSED*/ + +module DCM_SP ( + CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, + CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS, + CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST); +parameter real CLKDV_DIVIDE = 2.0; +parameter integer CLKFX_DIVIDE = 1; +parameter integer CLKFX_MULTIPLY = 4; +parameter CLKIN_DIVIDE_BY_2 = "FALSE"; +parameter real CLKIN_PERIOD = 10.0; +parameter CLKOUT_PHASE_SHIFT = "NONE"; +parameter CLK_FEEDBACK = "1X"; +parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; +parameter DFS_FREQUENCY_MODE = "LOW"; +parameter DLL_FREQUENCY_MODE = "LOW"; +parameter DSS_MODE = "NONE"; +parameter DUTY_CYCLE_CORRECTION = "TRUE"; +parameter FACTORY_JF = 16'hC080; +parameter integer PHASE_SHIFT = 0; +parameter STARTUP_WAIT = "FALSE"; +output CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90; +output CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE; +output [7:0] STATUS; +input CLKFB, CLKIN, DSSEN; +input PSCLK, PSEN, PSINCDEC, RST; +endmodule + +module BUFG (O, I); + output O; + input I; +endmodule + +module IBUFGDS (O, I, IB); + output O; + input I, IB; +endmodule + +module IOBUF (O, IO, I, T); + parameter CAPACITANCE = "DONT_CARE"; + parameter integer DRIVE = 12; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IFD_DELAY_VALUE = "AUTO"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + output O; + inout IO; + input I, T; +endmodule + +module FDCE (Q, C, CE, CLR, D); + parameter INIT = 1'b0; + output Q; + input C, CE, CLR, D; +endmodule + +module FD (Q, C, D); + parameter INIT = 1'b0; + output Q; + input C, D; +endmodule + +module DSP48A1 (BCOUT, CARRYOUT, CARRYOUTF, M, P, PCOUT, A, B, C, CARRYIN, CEA, CEB, CEC, CECARRYIN, CED, CEM, CEOPMODE, CEP, CLK, D, OPMODE, PCIN, RSTA, RSTB, RSTC, RSTCARRYIN, RSTD, RSTM, RSTOPMODE, RSTP); + parameter integer A0REG = 0; + parameter integer A1REG = 1; + parameter integer B0REG = 0; + parameter integer B1REG = 1; + parameter integer CARRYINREG = 1; + parameter integer CARRYOUTREG = 1; + parameter CARRYINSEL = "OPMODE5"; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter integer PREG = 1; + parameter RSTTYPE = "SYNC"; + output [17:0] BCOUT; + output CARRYOUT; + output CARRYOUTF; + output [35:0] M; + output [47:0] P; + output [47:0] PCOUT; + input [17:0] A; + input [17:0] B; + input [47:0] C; + input CARRYIN; + input CEA; + input CEB; + input CEC; + input CECARRYIN; + input CED; + input CEM; + input CEOPMODE; + input CEP; + input CLK; + input [17:0] D; + input [7:0] OPMODE; + input [47:0] PCIN; + input RSTA; + input RSTB; + input RSTC; + input RSTCARRYIN; + input RSTD; + input RSTM; + input RSTOPMODE; + input RSTP; +endmodule + +module GND(G); + output G; +endmodule + +module VCC(P); + output P; +endmodule + diff --git a/eim/build/Makefile b/eim/build/Makefile index d598126..badda45 100644 --- a/eim/build/Makefile +++ b/eim/build/Makefile @@ -51,16 +51,19 @@ vfiles = \ ../../../../cipher/chacha/src/rtl/chacha.v \ ../../../../cipher/chacha/src/rtl/chacha_core.v \ ../../../../cipher/chacha/src/rtl/chacha_qr.v \ - ../../../../math/modexp/src/rtl/adder32.v \ - ../../../../math/modexp/src/rtl/blockmem1r1w.v \ - ../../../../math/modexp/src/rtl/blockmem2r1wptr.v \ - ../../../../math/modexp/src/rtl/blockmem2r1w.v \ - ../../../../math/modexp/src/rtl/blockmem2rptr1w.v \ - ../../../../math/modexp/src/rtl/modexp.v \ - ../../../../math/modexp/src/rtl/modexp_core.v \ - ../../../../math/modexp/src/rtl/montprod.v \ - ../../../../math/modexp/src/rtl/residue.v \ - ../../../../math/modexp/src/rtl/shl32.v \ - ../../../../math/modexp/src/rtl/shr32.v + ../../../../math/modexps6/src/rtl/modexps6_adder64_carry32.v \ + ../../../../math/modexps6/src/rtl/modexps6_buffer_core.v \ + ../../../../math/modexps6/src/rtl/modexps6_buffer_user.v \ + ../../../../math/modexps6/src/rtl/modexps6_modinv32.v \ + ../../../../math/modexps6/src/rtl/modexps6_montgomery_coeff.v \ + ../../../../math/modexps6/src/rtl/modexps6_montgomery_multiplier.v \ + ../../../../math/modexps6/src/rtl/modexps6_top.v \ + ../../../../math/modexps6/src/rtl/modexps6_wrapper.v \ + ../../../../math/modexps6/src/rtl/ram_1rw_1ro_readfirst.v \ + ../../../../math/modexps6/src/rtl/ipcore/multiplier_s6.v \ + ../../../../math/modexps6/src/rtl/ipcore/subtractor_s6.v include xilinx.mk + +lint: + verilator --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME $(vfiles) ../../common/rtl/lint-dummy.v diff --git a/eim/build/xilinx.mk b/eim/build/xilinx.mk index 8065e45..8a81ef9 100644 --- a/eim/build/xilinx.mk +++ b/eim/build/xilinx.mk @@ -31,7 +31,9 @@ # TODO: .xco files are device dependant, should use a template based system coregen_work_dir ?= ./coregen-tmp -map_opts ?= -timing -ol high -detail -pr b -register_duplication -w -xe n +#map_opts ?= -timing -ol high -detail -pr b -register_duplication -w -xe n +# from https://github.com/fpga-logi/logi-hard/blob/master/build_lib/synth/xilinx.mk: +map_opts ?= -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off par_opts ?= -ol high isedir ?= /opt/Xilinx/13.3/ISE_DS xil_env ?= . $(isedir)/settings32.sh diff --git a/eim/iseconfig/novena_eim.xise b/eim/iseconfig/novena_eim.xise index b7708eb..e89c042 100644 --- a/eim/iseconfig/novena_eim.xise +++ b/eim/iseconfig/novena_eim.xise @@ -17,87 +17,71 @@ <files> <file xil_pn:name="../rtl/novena_eim.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> - <association xil_pn:name="Implementation" xil_pn:seqID="56"/> + <association xil_pn:name="Implementation" xil_pn:seqID="54"/> </file> <file xil_pn:name="../../common/rtl/novena_regs.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> - <association xil_pn:name="Implementation" xil_pn:seqID="35"/> + <association xil_pn:name="Implementation" xil_pn:seqID="36"/> </file> <file xil_pn:name="../../common/rtl/novena_clkmgr.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> - <association xil_pn:name="Implementation" xil_pn:seqID="53"/> - </file> - <file xil_pn:name="../../common/rtl/ipcore/clkmgr_dcm.xco" xil_pn:type="FILE_COREGEN"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> - <association xil_pn:name="Implementation" xil_pn:seqID="45"/> + <association xil_pn:name="Implementation" xil_pn:seqID="51"/> </file> <file xil_pn:name="../../../common/core_selector/src/rtl/core_selector.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> - <association xil_pn:name="Implementation" xil_pn:seqID="54"/> + <association xil_pn:name="Implementation" xil_pn:seqID="52"/> </file> <file xil_pn:name="../../../common/core_selector/src/rtl/global_selector.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> - <association xil_pn:name="Implementation" xil_pn:seqID="49"/> + <association xil_pn:name="Implementation" xil_pn:seqID="47"/> </file> <file xil_pn:name="../../../common/core_selector/src/rtl/cipher_selector.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> - <association xil_pn:name="Implementation" xil_pn:seqID="50"/> + <association xil_pn:name="Implementation" xil_pn:seqID="48"/> </file> <file xil_pn:name="../../../common/core_selector/src/rtl/hash_selector.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/> - <association xil_pn:name="Implementation" xil_pn:seqID="48"/> + <association xil_pn:name="Implementation" xil_pn:seqID="46"/> </file> <file xil_pn:name="../../../common/core_selector/src/rtl/rng_selector.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/> - <association xil_pn:name="Implementation" xil_pn:seqID="46"/> + <association xil_pn:name="Implementation" xil_pn:seqID="44"/> </file> <file xil_pn:name="../../../../comm/eim/src/rtl/cdc_bus_pulse.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/> - <association xil_pn:name="Implementation" xil_pn:seqID="32"/> + <association xil_pn:name="Implementation" xil_pn:seqID="33"/> </file> <file xil_pn:name="../../../../comm/eim/src/rtl/eim_arbiter_cdc.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/> - <association xil_pn:name="Implementation" xil_pn:seqID="42"/> + <association xil_pn:name="Implementation" xil_pn:seqID="41"/> </file> <file xil_pn:name="../../../../comm/eim/src/rtl/eim_arbiter.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/> - <association xil_pn:name="Implementation" xil_pn:seqID="52"/> + <association xil_pn:name="Implementation" xil_pn:seqID="50"/> </file> <file xil_pn:name="../../../../comm/eim/src/rtl/eim_da_phy.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/> - <association xil_pn:name="Implementation" xil_pn:seqID="41"/> + <association xil_pn:name="Implementation" xil_pn:seqID="40"/> </file> <file xil_pn:name="../../../../comm/eim/src/rtl/eim_indicator.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/> - <association xil_pn:name="Implementation" xil_pn:seqID="51"/> + <association xil_pn:name="Implementation" xil_pn:seqID="49"/> </file> <file xil_pn:name="../../../../comm/eim/src/rtl/eim.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/> - <association xil_pn:name="Implementation" xil_pn:seqID="55"/> - </file> - <file xil_pn:name="../../../../hash/sha1/src/rtl/sha1_core.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/> - <association xil_pn:name="Implementation" xil_pn:seqID="31"/> - </file> - <file xil_pn:name="../../../../hash/sha1/src/rtl/sha1_w_mem.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/> - <association xil_pn:name="Implementation" xil_pn:seqID="17"/> - </file> - <file xil_pn:name="../../../../hash/sha1/src/rtl/sha1.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/> - <association xil_pn:name="Implementation" xil_pn:seqID="39"/> + <association xil_pn:name="Implementation" xil_pn:seqID="53"/> </file> <file xil_pn:name="../../../../hash/sha256/src/rtl/sha256_core.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/> - <association xil_pn:name="Implementation" xil_pn:seqID="30"/> + <association xil_pn:name="Implementation" xil_pn:seqID="32"/> </file> <file xil_pn:name="../../../../hash/sha256/src/rtl/sha256_k_constants.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/> - <association xil_pn:name="Implementation" xil_pn:seqID="16"/> + <association xil_pn:name="Implementation" xil_pn:seqID="21"/> </file> <file xil_pn:name="../../../../hash/sha256/src/rtl/sha256_w_mem.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/> - <association xil_pn:name="Implementation" xil_pn:seqID="15"/> + <association xil_pn:name="Implementation" xil_pn:seqID="20"/> </file> <file xil_pn:name="../../../../hash/sha256/src/rtl/sha256.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/> @@ -105,146 +89,160 @@ </file> <file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_core.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/> - <association xil_pn:name="Implementation" xil_pn:seqID="14"/> + <association xil_pn:name="Implementation" xil_pn:seqID="19"/> </file> <file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_h_constants.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/> - <association xil_pn:name="Implementation" xil_pn:seqID="4"/> + <association xil_pn:name="Implementation" xil_pn:seqID="8"/> </file> <file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_k_constants.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/> - <association xil_pn:name="Implementation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="7"/> </file> <file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_w_mem.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/> - <association xil_pn:name="Implementation" xil_pn:seqID="2"/> - </file> - <file xil_pn:name="../../../../hash/sha512/src/rtl/sha512.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/> - <association xil_pn:name="Implementation" xil_pn:seqID="37"/> + <association xil_pn:name="Implementation" xil_pn:seqID="6"/> </file> <file xil_pn:name="../ucf/novena_eim.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> <file xil_pn:name="../../../../comm/eim/src/rtl/eim_regs.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/> - <association xil_pn:name="Implementation" xil_pn:seqID="40"/> + <association xil_pn:name="Implementation" xil_pn:seqID="39"/> </file> <file xil_pn:name="../../../../rng/trng/src/rtl/trng.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/> - <association xil_pn:name="Implementation" xil_pn:seqID="34"/> + <association xil_pn:name="Implementation" xil_pn:seqID="35"/> </file> <file xil_pn:name="../../../../rng/trng/src/rtl/trng_mixer.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/> - <association xil_pn:name="Implementation" xil_pn:seqID="23"/> + <association xil_pn:name="Implementation" xil_pn:seqID="27"/> </file> <file xil_pn:name="../../../../rng/trng/src/rtl/trng_csprng.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/> - <association xil_pn:name="Implementation" xil_pn:seqID="24"/> + <association xil_pn:name="Implementation" xil_pn:seqID="28"/> </file> <file xil_pn:name="../../../../rng/trng/src/rtl/trng_csprng_fifo.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/> - <association xil_pn:name="Implementation" xil_pn:seqID="7"/> + <association xil_pn:name="Implementation" xil_pn:seqID="11"/> </file> <file xil_pn:name="../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/> - <association xil_pn:name="Implementation" xil_pn:seqID="26"/> + <association xil_pn:name="Implementation" xil_pn:seqID="30"/> </file> <file xil_pn:name="../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/> - <association xil_pn:name="Implementation" xil_pn:seqID="9"/> + <association xil_pn:name="Implementation" xil_pn:seqID="13"/> </file> <file xil_pn:name="../../../../rng/rosc_entropy/src/rtl/rosc_entropy_core.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/> - <association xil_pn:name="Implementation" xil_pn:seqID="8"/> + <association xil_pn:name="Implementation" xil_pn:seqID="12"/> </file> <file xil_pn:name="../../../../rng/rosc_entropy/src/rtl/rosc_entropy.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/> - <association xil_pn:name="Implementation" xil_pn:seqID="25"/> + <association xil_pn:name="Implementation" xil_pn:seqID="29"/> </file> <file xil_pn:name="../../../../rng/rosc_entropy/src/rtl/rosc.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/> - <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + <association xil_pn:name="Implementation" xil_pn:seqID="2"/> </file> <file xil_pn:name="../../../../cipher/chacha/src/rtl/chacha_core.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/> - <association xil_pn:name="Implementation" xil_pn:seqID="18"/> + <association xil_pn:name="Implementation" xil_pn:seqID="22"/> </file> <file xil_pn:name="../../../../cipher/chacha/src/rtl/chacha_qr.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/> - <association xil_pn:name="Implementation" xil_pn:seqID="5"/> + <association xil_pn:name="Implementation" xil_pn:seqID="9"/> </file> <file xil_pn:name="../../../common/core_selector/src/rtl/math_selector.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/> - <association xil_pn:name="Implementation" xil_pn:seqID="47"/> + <association xil_pn:name="Implementation" xil_pn:seqID="45"/> </file> <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_core.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/> - <association xil_pn:name="Implementation" xil_pn:seqID="33"/> + <association xil_pn:name="Implementation" xil_pn:seqID="34"/> </file> <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_decipher_block.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/> - <association xil_pn:name="Implementation" xil_pn:seqID="22"/> + <association xil_pn:name="Implementation" xil_pn:seqID="26"/> </file> <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_encipher_block.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/> - <association xil_pn:name="Implementation" xil_pn:seqID="21"/> + <association xil_pn:name="Implementation" xil_pn:seqID="25"/> </file> <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_inv_sbox.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="100"/> - <association xil_pn:name="Implementation" xil_pn:seqID="6"/> + <association xil_pn:name="Implementation" xil_pn:seqID="10"/> </file> <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_key_mem.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="101"/> - <association xil_pn:name="Implementation" xil_pn:seqID="20"/> + <association xil_pn:name="Implementation" xil_pn:seqID="24"/> </file> <file xil_pn:name="../../../../cipher/aes/src/rtl/aes_sbox.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="102"/> - <association xil_pn:name="Implementation" xil_pn:seqID="19"/> + <association xil_pn:name="Implementation" xil_pn:seqID="23"/> </file> <file xil_pn:name="../../../../cipher/aes/src/rtl/aes.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="103"/> - <association xil_pn:name="Implementation" xil_pn:seqID="44"/> - </file> - <file xil_pn:name="../../../../cipher/chacha/src/rtl/chacha.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="104"/> - <association xil_pn:name="Implementation" xil_pn:seqID="43"/> - </file> - <file xil_pn:name="../../../../math/modexp/src/rtl/adder32.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="105"/> - <association xil_pn:name="Implementation" xil_pn:seqID="13"/> - </file> - <file xil_pn:name="../../../../math/modexp/src/rtl/blockmem1r1w.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/> - <association xil_pn:name="Implementation" xil_pn:seqID="12"/> - </file> - <file xil_pn:name="../../../../math/modexp/src/rtl/blockmem2r1w.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/> - <association xil_pn:name="Implementation" xil_pn:seqID="29"/> + <association xil_pn:name="Implementation" xil_pn:seqID="42"/> </file> - <file xil_pn:name="../../../../math/modexp/src/rtl/modexp.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../math/modexps6/src/rtl/modexps6_adder64_carry32.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="108"/> - <association xil_pn:name="Implementation" xil_pn:seqID="36"/> + <association xil_pn:name="Implementation" xil_pn:seqID="4"/> </file> - <file xil_pn:name="../../../../math/modexp/src/rtl/montprod.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../math/modexps6/src/rtl/modexps6_buffer_core.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="109"/> - <association xil_pn:name="Implementation" xil_pn:seqID="28"/> + <association xil_pn:name="Implementation" xil_pn:seqID="18"/> </file> - <file xil_pn:name="../../../../math/modexp/src/rtl/residue.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../math/modexps6/src/rtl/modexps6_buffer_user.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="110"/> - <association xil_pn:name="Implementation" xil_pn:seqID="27"/> + <association xil_pn:name="Implementation" xil_pn:seqID="17"/> </file> - <file xil_pn:name="../../../../math/modexp/src/rtl/shl32.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../math/modexps6/src/rtl/modexps6_modinv32.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="111"/> - <association xil_pn:name="Implementation" xil_pn:seqID="11"/> + <association xil_pn:name="Implementation" xil_pn:seqID="16"/> </file> - <file xil_pn:name="../../../../math/modexp/src/rtl/shr32.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../math/modexps6/src/rtl/modexps6_montgomery_coeff.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="112"/> - <association xil_pn:name="Implementation" xil_pn:seqID="10"/> + <association xil_pn:name="Implementation" xil_pn:seqID="15"/> </file> - <file xil_pn:name="../../common/rtl/ipcore/clkmgr_dcm.xise" xil_pn:type="FILE_COREGENISE"> + <file xil_pn:name="../../../../math/modexps6/src/rtl/modexps6_montgomery_multiplier.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="113"/> + <association xil_pn:name="Implementation" xil_pn:seqID="14"/> + </file> + <file xil_pn:name="../../../../math/modexps6/src/rtl/modexps6_top.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="114"/> + <association xil_pn:name="Implementation" xil_pn:seqID="31"/> + </file> + <file xil_pn:name="../../../../math/modexps6/src/rtl/modexps6_wrapper.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/> + <association xil_pn:name="Implementation" xil_pn:seqID="37"/> + </file> + <file xil_pn:name="../../../../math/modexps6/src/rtl/ram_1rw_1ro_readfirst.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/> + <association xil_pn:name="Implementation" xil_pn:seqID="3"/> + </file> + <file xil_pn:name="../../../../math/modexps6/src/rtl/ipcore/multiplier_s6.xco" xil_pn:type="FILE_COREGEN"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="111"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="../../../../math/modexps6/src/rtl/ipcore/subtractor_s6.xco" xil_pn:type="FILE_COREGEN"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="118"/> + <association xil_pn:name="Implementation" xil_pn:seqID="5"/> + </file> + <file xil_pn:name="../../common/rtl/ipcore/clkmgr_dcm.xco" xil_pn:type="FILE_COREGEN"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/> + <association xil_pn:name="Implementation" xil_pn:seqID="125"/> + </file> + <file xil_pn:name="../../../../math/modexps6/src/rtl/ipcore/multiplier_s6.xise" xil_pn:type="FILE_COREGENISE"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> + <file xil_pn:name="../../../../math/modexps6/src/rtl/ipcore/subtractor_s6.xise" xil_pn:type="FILE_COREGENISE"> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + </file> + <file xil_pn:name="../../common/rtl/ipcore/clkmgr_dcm.xise" xil_pn:type="FILE_COREGENISE"> + <association xil_pn:name="Implementation" xil_pn:seqID="126"/> + </file> </files> <properties> @@ -272,7 +270,7 @@ <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/> <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> @@ -450,6 +448,7 @@ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/> <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> diff --git a/eim/rtl/novena_eim.v b/eim/rtl/novena_eim.v index 0d8c8d0..1a1b1f6 100644 --- a/eim/rtl/novena_eim.v +++ b/eim/rtl/novena_eim.v @@ -142,14 +142,8 @@ module novena_top // hashes, RNGs and ciphers to different regions (segments) of memory. //---------------------------------------------------------------- - // register read data for one clock cycle for EIM - wire [31 : 0] tmp_read_data; - reg [31 : 0] tmp_read_data_reg; - assign sys_eim_din = tmp_read_data_reg; - always @(posedge sys_clk) - begin - tmp_read_data_reg <= tmp_read_data; - end + wire [31 : 0] tmp_read_data; + assign sys_eim_din = tmp_read_data; core_selector cores ( diff --git a/i2c/build/Makefile b/i2c/build/Makefile index d881820..1859da3 100644 --- a/i2c/build/Makefile +++ b/i2c/build/Makefile @@ -14,9 +14,10 @@ vfiles = \ ../../common/rtl/ipcore/clkmgr_dcm.v \ ../../../common/core_selector/src/rtl/core_selector.v \ ../../../common/core_selector/src/rtl/global_selector.v \ - ../../../common/core_selector/src/rtl/cipher_selector.v \ ../../../common/core_selector/src/rtl/hash_selector.v \ ../../../common/core_selector/src/rtl/rng_selector.v \ + ../../../common/core_selector/src/rtl/cipher_selector.v \ + ../../../common/core_selector/src/rtl/math_selector.v \ ../../../../comm/i2c/src/rtl/i2c_regs.v \ ../../../../comm/i2c/src/rtl/i2c_core.v \ ../../../../comm/coretest/src/rtl/coretest.v \ @@ -41,8 +42,29 @@ vfiles = \ ../../../../rng/trng/src/rtl/trng_csprng.v \ ../../../../rng/trng/src/rtl/trng_csprng_fifo.v \ ../../../../rng/trng/src/rtl/trng_mixer.v \ + ../../../../cipher/aes/src/rtl/aes.v \ + ../../../../cipher/aes/src/rtl/aes_core.v \ + ../../../../cipher/aes/src/rtl/aes_decipher_block.v \ + ../../../../cipher/aes/src/rtl/aes_encipher_block.v \ + ../../../../cipher/aes/src/rtl/aes_inv_sbox.v \ + ../../../../cipher/aes/src/rtl/aes_key_mem.v \ + ../../../../cipher/aes/src/rtl/aes_sbox.v \ ../../../../cipher/chacha/src/rtl/chacha.v \ ../../../../cipher/chacha/src/rtl/chacha_core.v \ - ../../../../cipher/chacha/src/rtl/chacha_qr.v + ../../../../cipher/chacha/src/rtl/chacha_qr.v \ + ../../../../math/modexp/src/rtl/adder32.v \ + ../../../../math/modexp/src/rtl/blockmem1r1w.v \ + ../../../../math/modexp/src/rtl/blockmem2r1wptr.v \ + ../../../../math/modexp/src/rtl/blockmem2r1w.v \ + ../../../../math/modexp/src/rtl/blockmem2rptr1w.v \ + ../../../../math/modexp/src/rtl/modexp.v \ + ../../../../math/modexp/src/rtl/modexp_core.v \ + ../../../../math/modexp/src/rtl/montprod.v \ + ../../../../math/modexp/src/rtl/residue.v \ + ../../../../math/modexp/src/rtl/shl32.v \ + ../../../../math/modexp/src/rtl/shr32.v include xilinx.mk + +lint: + verilator --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME $(vfiles) ../../common/rtl/lint-dummy.v diff --git a/sw/Makefile b/sw/Makefile index d1f33f2..015f6f0 100755 --- a/sw/Makefile +++ b/sw/Makefile @@ -1,8 +1,9 @@ CC = gcc +AR = ar CFLAGS = -Wall -fPIC LIB = libcryptech.a -BIN = hash hash_tester trng_extractor trng_tester aes_tester modexp_tester +BIN = hash hash_tester trng_extractor trng_tester aes_tester modexp_tester modexps6_tester devmem3 INC = cryptech.h PREFIX = /usr/local @@ -16,7 +17,7 @@ all: $(LIB) $(BIN) $(CC) $(CFLAGS) -c -o $@ $< libcryptech.a: tc_eim.o novena-eim.o capability.o - ar rcs $@ $^ + $(AR) rcs $@ $^ hash_tester: hash_tester.o $(LIB) $(CC) -o $@ $^ @@ -30,20 +31,26 @@ aes_tester: aes_tester.o $(LIB) modexp_tester: modexp_tester.o $(LIB) $(CC) -o $@ $^ +modexps6_tester: modexps6_tester.o $(LIB) + $(CC) -o $@ $^ + hash: hash.o $(LIB) $(CC) -o $@ $^ trng_extractor: trng_extractor.o $(LIB) $(CC) -o $@ $^ +devmem3: devmem3.o $(LIB) + $(CC) -o $@ $^ + install: $(LIB) $(BIN) $(INC) install $(LIB) $(LIB_DIR) - install $(BIN) $(BIN_DIR) + install $(BIN) configure-fpga.sh $(BIN_DIR) install $(INC) $(INC_DIR) uninstall: rm -f $(LIB_DIR)/$(LIB) - rm -f $(foreach bin,$(BIN),$(BIN_DIR)/$(bin)) + rm -f $(foreach bin,$(BIN) configure-fpga.sh,$(BIN_DIR)/$(bin)) rm -f $(INC_DIR)/$(INC) clean: diff --git a/sw/Makefile.i2c b/sw/Makefile.i2c index 1294360..5c69069 100755 --- a/sw/Makefile.i2c +++ b/sw/Makefile.i2c @@ -1,8 +1,9 @@ CC = gcc +AR = AR CFLAGS = -Wall -fPIC LIB = libcryptech_i2c.a -BIN = hash_i2c hash_tester_i2c trng_extractor_i2c trng_tester_i2c +BIN = hash_i2c hash_tester_i2c trng_extractor_i2c trng_tester_i2c aes_tester_i2c modexp_tester_i2c INC = cryptech.h PREFIX = /usr/local @@ -16,7 +17,7 @@ all: $(LIB) $(BIN) $(CC) $(CFLAGS) -c -o $@ $< libcryptech_i2c.a: tc_i2c.o capability.o - ar rcs $@ $^ + $(AR) rcs $@ $^ hash_tester_i2c: hash_tester.o $(LIB) $(CC) -o $@ $^ @@ -24,6 +25,12 @@ hash_tester_i2c: hash_tester.o $(LIB) trng_tester_i2c: trng_tester.o $(LIB) $(CC) -o $@ $^ +aes_tester_i2c: aes_tester.o $(LIB) + $(CC) -o $@ $^ + +modexp_tester_i2c: modexp_tester.o $(LIB) + $(CC) -o $@ $^ + hash_i2c: hash.o $(LIB) $(CC) -o $@ $^ diff --git a/sw/configure-fpga.sh b/sw/configure-fpga.sh new file mode 100644 index 0000000..7ebfb6b --- /dev/null +++ b/sw/configure-fpga.sh @@ -0,0 +1,13 @@ +#!/bin/sh - +bitfile="${1-novena_eim.bit}" +echo "Setting export of reset pin" +echo 135 > /sys/class/gpio/export +echo "setting reset pin to out" +echo out > /sys/class/gpio/gpio135/direction +echo "flipping reset" +echo 0 > /sys/class/gpio/gpio135/value +echo 1 > /sys/class/gpio/gpio135/value +echo "configuring FPGA" +dd if=${bitfile} of=/dev/spidev2.0 bs=128 +echo "turning on clock to FPGA" +devmem3 0x020c8160 w 0x00000D2B diff --git a/sw/cryptech.h b/sw/cryptech.h index 9535061..8a7361f 100644 --- a/sw/cryptech.h +++ b/sw/cryptech.h @@ -400,6 +400,37 @@ in order to map it into a 16-bit address space. #define MODEXP_NAME1 "xp " #define MODEXP_VERSION "0.51" +// Experimental ModexpS6 core. +// XXX AT THE SAME CORE PREFIX - YOU CAN'T HAVE BOTH AT THE SAME TIME +#define MODEXPS6_ADDR_BASE SEGMENT_OFFSET_MATH + (0x00 * CORE_SIZE) +#define MODEXPS6_ADDR_NAME0 MODEXPS6_ADDR_BASE + ADDR_NAME0 +#define MODEXPS6_ADDR_NAME1 MODEXPS6_ADDR_BASE + ADDR_NAME1 +#define MODEXPS6_ADDR_VERSION MODEXPS6_ADDR_BASE + ADDR_VERSION +#define MODEXPS6_ADDR_CTRL MODEXPS6_ADDR_BASE + ADDR_CTRL +#define MODEXPS6_CTRL_INIT_BIT 1 +#define MODEXPS6_CTRL_NEXT_BIT 2 +#define MODEXPS6_ADDR_STATUS MODEXPS6_ADDR_BASE + ADDR_STATUS + +/* 4096-bit operands are stored as 128 words of 32 bits */ +#define MODEXPS6_OPERAND_SIZE 4096/32 + +#define MODEXPS6_ADDR_REGISTERS MODEXPS6_ADDR_BASE + 0*MODEXPS6_OPERAND_SIZE +#define MODEXPS6_ADDR_OPERANDS MODEXPS6_ADDR_BASE + 4*MODEXPS6_OPERAND_SIZE + +#define MODEXPS6_ADDR_MODE MODEXPS6_ADDR_REGISTERS + 0x10 +#define MODEXPS6_ADDR_MODULUS_WIDTH MODEXPS6_ADDR_REGISTERS + 0x11 +#define MODEXPS6_ADDR_EXPONENT_WIDTH MODEXPS6_ADDR_REGISTERS + 0x12 + +/* addresses of block memories for operands */ +#define MODEXPS6_ADDR_MODULUS MODEXPS6_ADDR_OPERANDS + 0*MODEXPS6_OPERAND_SIZE +#define MODEXPS6_ADDR_MESSAGE MODEXPS6_ADDR_OPERANDS + 1*MODEXPS6_OPERAND_SIZE +#define MODEXPS6_ADDR_EXPONENT MODEXPS6_ADDR_OPERANDS + 2*MODEXPS6_OPERAND_SIZE +#define MODEXPS6_ADDR_RESULT MODEXPS6_ADDR_OPERANDS + 3*MODEXPS6_OPERAND_SIZE + +#define MODEXPS6_NAME0 "mode" +#define MODEXPS6_NAME1 "xps6" +#define MODEXPS6_VERSION "0.10" + //------------------------------------------------------------------ // Test case public functions diff --git a/sw/devmem3.c b/sw/devmem3.c new file mode 100644 index 0000000..3c3fa16 --- /dev/null +++ b/sw/devmem3.c @@ -0,0 +1,40 @@ +#include <stdio.h> +#include <stdlib.h> + +#include "novena-eim.h" + +int +main(int argc, char *argv[]) +{ + off_t offset; + uint32_t value, result; + + if (argc < 3 || argc > 4) { + usage: + fprintf(stderr, "usage: %s offset r\n", argv[0]); + fprintf(stderr, "usage: %s offset w value\n", argv[0]); + exit(EXIT_FAILURE); + } + + if (eim_setup() != 0) { + fprintf(stderr, "EIM setup failed\n"); + exit(EXIT_FAILURE); + } + + offset = (off_t)strtoul(argv[1], NULL, 0); + if (argv[2][0] == 'r') { + eim_read_32(offset, &result); + printf("%08x\n", result); + } + else if (argv[2][0] == 'w') { + value = strtoul(argv[3], NULL, 0); + eim_write_32(offset, &value); + } + else { + fprintf(stderr, "unknown command '%s'\n", argv[2]); + goto usage; + } + + exit(EXIT_SUCCESS); +} + diff --git a/sw/modexps6_tester.c b/sw/modexps6_tester.c new file mode 100644 index 0000000..a9e3b74 --- /dev/null +++ b/sw/modexps6_tester.c @@ -0,0 +1,650 @@ +#include <string.h> +#include <stdio.h> +#include <stdlib.h> +#include <errno.h> +#include <sys/mman.h> +#include <fcntl.h> +#include <unistd.h> +#include <time.h> +#include <sys/time.h> +#include <sys/ioctl.h> +#include <arpa/inet.h> +#include <ctype.h> +#include <signal.h> +#include <assert.h> + +#include "cryptech.h" +#include "test-rsa.h" +#include "test-modexp-for-pavel.h" + +int quiet = 0; +int repeat = 0; + +int tc_width(off_t offset, uint32_t length) +{ + length = htonl(length); // ! + + uint8_t width[4]; + memcpy(width, &length, 4); + + return tc_write(offset, width, sizeof(width)); +} + +/* + * Utility to madly swap 32-bit words within an operand so that the + * first word becomes the last word and so forth. + */ + +static void two_card_monty(void *output, const void * const input, const size_t byte_count) +{ + const size_t word_count = byte_count / 4; + const uint32_t * const i32 = input; + uint32_t * const o32 = output; + int i; + + assert(byte_count % 4 == 0); + + for (i = 0; i < word_count; i++) + o32[i] = i32[word_count - i - 1]; +} + +/* + * Clone operand into a reversed buffer. Necessary lack of curly + * braces makes this unsuitable for use in library code, but it + * simplifies test setup here. + */ + +#define clone_reversed(_clone, _orig) \ + uint8_t _clone[sizeof(_orig)]; \ + two_card_monty(_clone, _orig, sizeof(_orig)) + + +/* TC0: Read name and version from ModExpS6 core. */ +int TC0(void) +{ + uint8_t name0[4] = { 'm', 'o', 'd', 'e'}; + uint8_t name1[4] = { 'x', 'p', 's', '6'}; + uint8_t version[4] = { '0', '.', '1', '0'}; + + if (!quiet) + printf("TC0: Reading name and version words from ModExpS6 core.\n"); + + return + tc_expected(MODEXPS6_ADDR_NAME0, name0, sizeof(name0)) || + tc_expected(MODEXPS6_ADDR_NAME1, name1, sizeof(name1)) || + tc_expected(MODEXPS6_ADDR_VERSION, version, sizeof(version)); +} + +/* TC1: Fast single 1024-bit message. */ +int TC1(void) +{ + int ret; + + if (!quiet) + printf("TC1: Sign 1024-bit message (fast & unsafe public mode).\n"); + + /* Change order of 32-bit words for all the operands (first word becomes last word, and so on...) */ + clone_reversed(modulus, n_1024); + clone_reversed(message, m_1024); + clone_reversed(exponent, d_1024); + clone_reversed(result, s_1024); + + /* Set fast mode */ + /*uint8_t mode_slow_secure[] = {0, 0, 0, 0};*/ + uint8_t mode_fast_unsafe[] = {0, 0, 0, 1}; + tc_write(MODEXPS6_ADDR_MODE, mode_fast_unsafe, sizeof(mode_fast_unsafe)); + + /* Set new modulus size */ + tc_width(MODEXPS6_ADDR_MODULUS_WIDTH, sizeof(modulus) * 8); // number of bits + + /* Write new modulus */ + tc_write(MODEXPS6_ADDR_MODULUS, modulus, sizeof(modulus)); + + /* Pre-calculate speed-up coefficient */ + tc_init(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_ready(MODEXPS6_ADDR_STATUS); + + /* Write new message */ + tc_write(MODEXPS6_ADDR_MESSAGE, message, sizeof(message)); + + /* Set new exponent length */ + tc_width(MODEXPS6_ADDR_EXPONENT_WIDTH, sizeof(exponent) * 8); // number of bits + + /* Write new exponent */ + tc_write(MODEXPS6_ADDR_EXPONENT, exponent, sizeof(exponent)); + + /* Start calculation */ + tc_next(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_valid(MODEXPS6_ADDR_STATUS); + + /* Compare actual result with expected value */ + ret = tc_expected(MODEXPS6_ADDR_RESULT, result, sizeof(result)); + + return ret; +} + +/* TC2: Slow single 1024-bit message. */ +int TC2(void) +{ + int ret; + + if (!quiet) + printf("TC2: Sign 1024-bit message (slow & secure private mode).\n"); + + /* Change order of 32-bit words for all the operands (first word becomes last word, and so on...) */ + clone_reversed(modulus, n_1024); + clone_reversed(message, m_1024); + clone_reversed(exponent, d_1024); + clone_reversed(result, s_1024); + + /* Set slow mode */ + uint8_t mode_slow_secure[] = {0, 0, 0, 0}; + /*uint8_t mode_fast_unsafe[] = {0, 0, 0, 1};*/ + tc_write(MODEXPS6_ADDR_MODE, mode_slow_secure, sizeof(mode_slow_secure)); + + /* Set new modulus size */ + tc_width(MODEXPS6_ADDR_MODULUS_WIDTH, sizeof(modulus) * 8); // number of bits + + /* Write new modulus */ + tc_write(MODEXPS6_ADDR_MODULUS, modulus, sizeof(modulus)); + + /* Pre-calculate speed-up coefficient */ + tc_init(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_ready(MODEXPS6_ADDR_STATUS); + + /* Write new message */ + tc_write(MODEXPS6_ADDR_MESSAGE, message, sizeof(message)); + + /* Set new exponent length */ + tc_width(MODEXPS6_ADDR_EXPONENT_WIDTH, sizeof(exponent) * 8); // number of bits + + /* Write new exponent */ + tc_write(MODEXPS6_ADDR_EXPONENT, exponent, sizeof(exponent)); + + /* Start calculation */ + tc_next(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_valid(MODEXPS6_ADDR_STATUS); + + /* Compare actual result with expected value */ + ret = tc_expected(MODEXPS6_ADDR_RESULT, result, sizeof(result)); + + return ret; +} + +/* TC3: Fast single 2048-bit message. */ +int TC3(void) +{ + int ret; + + if (!quiet) + printf("TC3: Sign 2048-bit message (fast & unsafe public mode).\n"); + + /* Change order of 32-bit words for all the operands (first word becomes last word, and so on...) */ + clone_reversed(modulus, n_2048); + clone_reversed(message, m_2048); + clone_reversed(exponent, d_2048); + clone_reversed(result, s_2048); + + /* Set fast mode */ + /*uint8_t mode_slow_secure[] = {0, 0, 0, 0};*/ + uint8_t mode_fast_unsafe[] = {0, 0, 0, 1}; + tc_write(MODEXPS6_ADDR_MODE, mode_fast_unsafe, sizeof(mode_fast_unsafe)); + + /* Set new modulus size */ + tc_width(MODEXPS6_ADDR_MODULUS_WIDTH, sizeof(modulus) * 8); // number of bits + + /* Write new modulus */ + tc_write(MODEXPS6_ADDR_MODULUS, modulus, sizeof(modulus)); + + /* Pre-calculate speed-up coefficient */ + tc_init(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_ready(MODEXPS6_ADDR_STATUS); + + /* Write new message */ + tc_write(MODEXPS6_ADDR_MESSAGE, message, sizeof(message)); + + /* Set new exponent length */ + tc_width(MODEXPS6_ADDR_EXPONENT_WIDTH, sizeof(exponent) * 8); // number of bits + + /* Write new exponent */ + tc_write(MODEXPS6_ADDR_EXPONENT, exponent, sizeof(exponent)); + + /* Start calculation */ + tc_next(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_valid(MODEXPS6_ADDR_STATUS); + + /* Compare actual result with expected value */ + ret = tc_expected(MODEXPS6_ADDR_RESULT, result, sizeof(result)); + + return ret; +} + +/* TC4: Slow single 2048-bit message. */ +int TC4(void) +{ + int ret; + + if (!quiet) + printf("TC4: Sign 2048-bit message (slow & secure private mode).\n"); + + /* Change order of 32-bit words for all the operands (first word becomes last word, and so on...) */ + clone_reversed(modulus, n_2048); + clone_reversed(message, m_2048); + clone_reversed(exponent, d_2048); + clone_reversed(result, s_2048); + + /* Set slow mode */ + uint8_t mode_slow_secure[] = {0, 0, 0, 0}; + /*uint8_t mode_fast_unsafe[] = {0, 0, 0, 1};*/ + tc_write(MODEXPS6_ADDR_MODE, mode_slow_secure, sizeof(mode_slow_secure)); + + /* Set new modulus size */ + tc_width(MODEXPS6_ADDR_MODULUS_WIDTH, sizeof(modulus) * 8); // number of bits + + /* Write new modulus */ + tc_write(MODEXPS6_ADDR_MODULUS, modulus, sizeof(modulus)); + + /* Pre-calculate speed-up coefficient */ + tc_init(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_ready(MODEXPS6_ADDR_STATUS); + + /* Write new message */ + tc_write(MODEXPS6_ADDR_MESSAGE, message, sizeof(message)); + + /* Set new exponent length */ + tc_width(MODEXPS6_ADDR_EXPONENT_WIDTH, sizeof(exponent) * 8); // number of bits + + /* Write new exponent */ + tc_write(MODEXPS6_ADDR_EXPONENT, exponent, sizeof(exponent)); + + /* Start calculation */ + tc_next(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_valid(MODEXPS6_ADDR_STATUS); + + /* Compare actual result with expected value */ + ret = tc_expected(MODEXPS6_ADDR_RESULT, result, sizeof(result)); + + return ret; +} + +/* TC5: Fast single 4096-bit message. */ +int TC5(void) +{ + int ret; + + if (!quiet) + printf("TC5: Sign 4096-bit message (fast & unsafe public mode).\n"); + + /* Change order of 32-bit words for all the operands (first word becomes last word, and so on...) */ + clone_reversed(modulus, n_4096); + clone_reversed(message, m_4096); + clone_reversed(exponent, d_4096); + clone_reversed(result, s_4096); + + /* Set fast mode */ + /*uint8_t mode_slow_secure[] = {0, 0, 0, 0};*/ + uint8_t mode_fast_unsafe[] = {0, 0, 0, 1}; + tc_write(MODEXPS6_ADDR_MODE, mode_fast_unsafe, sizeof(mode_fast_unsafe)); + + /* Set new modulus size */ + tc_width(MODEXPS6_ADDR_MODULUS_WIDTH, sizeof(modulus) * 8); // number of bits + + /* Write new modulus */ + tc_write(MODEXPS6_ADDR_MODULUS, modulus, sizeof(modulus)); + + /* Pre-calculate speed-up coefficient */ + tc_init(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_ready(MODEXPS6_ADDR_STATUS); + + /* Write new message */ + tc_write(MODEXPS6_ADDR_MESSAGE, message, sizeof(message)); + + /* Set new exponent length */ + tc_width(MODEXPS6_ADDR_EXPONENT_WIDTH, sizeof(exponent) * 8); // number of bits + + /* Write new exponent */ + tc_write(MODEXPS6_ADDR_EXPONENT, exponent, sizeof(exponent)); + + /* Start calculation */ + tc_next(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_valid(MODEXPS6_ADDR_STATUS); + + /* Compare actual result with expected value */ + ret = tc_expected(MODEXPS6_ADDR_RESULT, result, sizeof(result)); + + return ret; +} + +/* TC6: Slow single 4096-bit message. */ +int TC6(void) +{ + int ret; + + if (!quiet) + printf("TC6: Sign 4096-bit message (slow & secure private mode).\n"); + + /* Change order of 32-bit words for all the operands (first word becomes last word, and so on...) */ + clone_reversed(modulus, n_4096); + clone_reversed(message, m_4096); + clone_reversed(exponent, d_4096); + clone_reversed(result, s_4096); + + /* Set slow mode */ + uint8_t mode_slow_secure[] = {0, 0, 0, 0}; + /*uint8_t mode_fast_unsafe[] = {0, 0, 0, 1};*/ + tc_write(MODEXPS6_ADDR_MODE, mode_slow_secure, sizeof(mode_slow_secure)); + + /* Set new modulus size */ + tc_width(MODEXPS6_ADDR_MODULUS_WIDTH, sizeof(modulus) * 8); // number of bits + + /* Write new modulus */ + tc_write(MODEXPS6_ADDR_MODULUS, modulus, sizeof(modulus)); + + /* Pre-calculate speed-up coefficient */ + tc_init(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_ready(MODEXPS6_ADDR_STATUS); + + /* Write new message */ + tc_write(MODEXPS6_ADDR_MESSAGE, message, sizeof(message)); + + /* Set new exponent length */ + tc_width(MODEXPS6_ADDR_EXPONENT_WIDTH, sizeof(exponent) * 8); // number of bits + + /* Write new exponent */ + tc_write(MODEXPS6_ADDR_EXPONENT, exponent, sizeof(exponent)); + + /* Start calculation */ + tc_next(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_valid(MODEXPS6_ADDR_STATUS); + + /* Compare actual result with expected value */ + ret = tc_expected(MODEXPS6_ADDR_RESULT, result, sizeof(result)); + + return ret; +} + +/* TC7: Signing of multiple 1024-bit messages with same key. */ +int TC7(void) +{ + int ret; + + if (!quiet) + printf("TC7: Sign several 1024-bit messages (without pre-calculation every time).\n"); + + /* Change order of 32-bit words for all the operands (first word becomes last word, and so on...) */ + clone_reversed(modulus, n_1024); + clone_reversed(exponent, d_1024); + clone_reversed(message_0, m_1024_0); + clone_reversed(message_1, m_1024_1); + clone_reversed(message_2, m_1024_2); + clone_reversed(message_3, m_1024_3); + clone_reversed(result_0, s_1024_0); + clone_reversed(result_1, s_1024_1); + clone_reversed(result_2, s_1024_2); + clone_reversed(result_3, s_1024_3); + + /* Set fast mode */ + /*uint8_t mode_slow_secure[] = {0, 0, 0, 0};*/ + uint8_t mode_fast_unsafe[] = {0, 0, 0, 1}; + tc_write(MODEXPS6_ADDR_MODE, mode_fast_unsafe, sizeof(mode_fast_unsafe)); + + /* Set new modulus size */ + tc_width(MODEXPS6_ADDR_MODULUS_WIDTH, sizeof(modulus) * 8); // number of bits + + /* Write new modulus */ + tc_write(MODEXPS6_ADDR_MODULUS, modulus, sizeof(modulus)); + + /* Pre-calculate speed-up coefficient */ + tc_init(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_ready(MODEXPS6_ADDR_STATUS); + + /* Set new exponent length */ + tc_width(MODEXPS6_ADDR_EXPONENT_WIDTH, sizeof(exponent) * 8); // number of bits + + /* Write new exponent */ + tc_write(MODEXPS6_ADDR_EXPONENT, exponent, sizeof(exponent)); + + { + /* Write new message #0 */ + tc_write(MODEXPS6_ADDR_MESSAGE, message_0, sizeof(message_0)); + + /* Start calculation */ + tc_next(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_valid(MODEXPS6_ADDR_STATUS); + + /* Compare actual result with expected value */ + ret = tc_expected(MODEXPS6_ADDR_RESULT, result_0, sizeof(result_0)); + if (ret) return 1; + } + { + /* Write new message #1 */ + tc_write(MODEXPS6_ADDR_MESSAGE, message_1, sizeof(message_1)); + + /* Start calculation */ + tc_next(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_valid(MODEXPS6_ADDR_STATUS); + + /* Compare actual result with expected value */ + ret = tc_expected(MODEXPS6_ADDR_RESULT, result_1, sizeof(result_1)); + if (ret) return 1; + } + { + /* Write new message #2 */ + tc_write(MODEXPS6_ADDR_MESSAGE, message_2, sizeof(message_2)); + + /* Start calculation */ + tc_next(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_valid(MODEXPS6_ADDR_STATUS); + + /* Compare actual result with expected value */ + ret = tc_expected(MODEXPS6_ADDR_RESULT, result_2, sizeof(result_2)); + if (ret) return 1; + } + { + /* Write new message #3 */ + tc_write(MODEXPS6_ADDR_MESSAGE, message_3, sizeof(message_3)); + + /* Start calculation */ + tc_next(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_valid(MODEXPS6_ADDR_STATUS); + + /* Compare actual result with expected value */ + ret = tc_expected(MODEXPS6_ADDR_RESULT, result_3, sizeof(result_3)); + if (ret) return 1; + } + + return 0; +} + +/* TC8: Fast 4096-bit message verification. */ +int TC8(void) +{ + int ret; + + if (!quiet) + printf("TC8: Verify 4096-bit message (fast mode using public exponent).\n"); + + /* Change order of 32-bit words for all the operands (first word becomes last word, and so on...) */ + clone_reversed(modulus, n_4096); + clone_reversed(message, s_4096); + clone_reversed(exponent, e_4096); + clone_reversed(result, m_4096); + + /* Set fast mode */ + /*uint8_t mode_slow_secure[] = {0, 0, 0, 0};*/ + uint8_t mode_fast_unsafe[] = {0, 0, 0, 1}; + tc_write(MODEXPS6_ADDR_MODE, mode_fast_unsafe, sizeof(mode_fast_unsafe)); + + /* Set new modulus size */ + tc_width(MODEXPS6_ADDR_MODULUS_WIDTH, sizeof(modulus) * 8); // number of bits + + /* Write new modulus */ + tc_write(MODEXPS6_ADDR_MODULUS, modulus, sizeof(modulus)); + + /* Pre-calculate speed-up coefficient */ + tc_init(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_ready(MODEXPS6_ADDR_STATUS); + + /* Write new message */ + tc_write(MODEXPS6_ADDR_MESSAGE, message, sizeof(message)); + + /* Set new exponent length */ +#if 1 + tc_width(MODEXPS6_ADDR_EXPONENT_WIDTH, 18); // number of bits +#else + tc_width(MODEXPS6_ADDR_EXPONENT_WIDTH, 24); // number of bits +#endif + + /* Write new exponent */ + tc_write(MODEXPS6_ADDR_EXPONENT, exponent, sizeof(exponent)); + + /* Start calculation */ + tc_next(MODEXPS6_ADDR_CTRL); + + /* Wait while core is calculating */ + tc_wait_valid(MODEXPS6_ADDR_STATUS); + + /* Compare actual result with expected value */ + ret = tc_expected(MODEXPS6_ADDR_RESULT, result, sizeof(result)); + + return ret; +} + + +/* signal handler for ctrl-c to end repeat testing */ +unsigned long iter = 0; +struct timeval tv_start, tv_end; +void sighandler(int unused) +{ + double tv_diff; + + gettimeofday(&tv_end, NULL); + tv_diff = (double)(tv_end.tv_sec - tv_start.tv_sec) + + (double)(tv_end.tv_usec - tv_start.tv_usec)/1000000; + printf("\n%lu iterations in %.3f seconds (%.3f iterations/sec)\n", + iter, tv_diff, (double)iter/tv_diff); + exit(EXIT_SUCCESS); +} + +int main(int argc, char *argv[]) +{ + typedef int (*tcfp)(void); + tcfp all_tests[] = { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7, TC8 }; + + char *usage = "Usage: %s [-h] [-d] [-q] [-r] tc...\n"; + int i, j, opt; + + while ((opt = getopt(argc, argv, "h?dqr")) != -1) { + switch (opt) { + case 'h': + case '?': + printf(usage, argv[0]); + return EXIT_SUCCESS; + case 'd': + tc_set_debug(1); + break; + case 'q': + quiet = 1; + break; + case 'r': + repeat = 1; + break; + default: + fprintf(stderr, usage, argv[0]); + return EXIT_FAILURE; + } + } + + /* repeat one test until interrupted */ + if (repeat) { + tcfp tc; + if (optind != argc - 1) { + fprintf(stderr, "only one test case can be repeated\n"); + return EXIT_FAILURE; + } + j = atoi(argv[optind]); + if (j < 0 || j >= sizeof(all_tests)/sizeof(all_tests[0])) { + fprintf(stderr, "invalid test number %s\n", argv[optind]); + return EXIT_FAILURE; + } + tc = (all_tests[j]); + srand(time(NULL)); + signal(SIGINT, sighandler); + gettimeofday(&tv_start, NULL); + while (1) { + ++iter; + if ((iter & 0xffff) == 0) { + printf("."); + fflush(stdout); + } + if (tc() != 0) + sighandler(0); + } + return EXIT_SUCCESS; /*NOTREACHED*/ + } + + /* no args == run all tests */ + if (optind >= argc) { + for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) + if (all_tests[j]() != 0) + return EXIT_FAILURE; + return EXIT_SUCCESS; + } + + /* run one or more tests (by number) or groups of tests (by name) */ + for (i = optind; i < argc; ++i) { + if (strcmp(argv[i], "all") == 0) { + for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) + if (all_tests[j]() != 0) + return EXIT_FAILURE; + } + else if (isdigit(argv[i][0]) && + (((j = atoi(argv[i])) >= 0) && + (j < sizeof(all_tests)/sizeof(all_tests[0])))) { + if (all_tests[j]() != 0) + return EXIT_FAILURE; + } + else { + fprintf(stderr, "unknown test case %s\n", argv[i]); + return EXIT_FAILURE; + } + } + + return EXIT_SUCCESS; +} diff --git a/sw/test-modexp-for-pavel.h b/sw/test-modexp-for-pavel.h new file mode 100644 index 0000000..79889ee --- /dev/null +++ b/sw/test-modexp-for-pavel.h @@ -0,0 +1,140 @@ +/* + * Test vectors. First should be same as in test-rsa.h, for check. + */ + +/* + * Message #0 + * Plaintext: "You can hack anything you want with TECO and DDT." + * SHA-256: 8e36fc9aa31724c32416263c0366a175fabbb92b741ca6496107074d0343b597 + */ + +static const uint8_t m_1024_0[] = { /* message to be signed, 128 bytes */ + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, + 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20, + 0x8e, 0x36, 0xfc, 0x9a, 0xa3, 0x17, 0x24, 0xc3, 0x24, 0x16, 0x26, 0x3c, + 0x03, 0x66, 0xa1, 0x75, 0xfa, 0xbb, 0xb9, 0x2b, 0x74, 0x1c, 0xa6, 0x49, + 0x61, 0x07, 0x07, 0x4d, 0x03, 0x43, 0xb5, 0x97 +}; + +static const uint8_t s_1024_0[] = { /* signed message, 128 bytes */ + 0x3b, 0x09, 0xcc, 0x3d, 0x2f, 0xa1, 0x68, 0x1c, 0xa9, 0x29, 0x1b, 0xb7, + 0xcf, 0xc9, 0xe7, 0xb4, 0xfd, 0x3e, 0x5a, 0x22, 0x1c, 0x29, 0xdf, 0x4a, + 0x32, 0xcf, 0xa5, 0xae, 0x30, 0xd4, 0xee, 0x8f, 0x3a, 0xc8, 0xc1, 0xee, + 0x79, 0x40, 0xb2, 0xbf, 0xc7, 0x12, 0x82, 0x73, 0x3c, 0x6b, 0x8a, 0xd1, + 0xa4, 0x4a, 0x6d, 0x60, 0x9f, 0x00, 0xb4, 0x51, 0x8b, 0x6c, 0xcd, 0xae, + 0xad, 0xf4, 0x0a, 0x48, 0xd5, 0xb9, 0x4b, 0x9e, 0xca, 0x77, 0x10, 0xc2, + 0x9b, 0x26, 0x8c, 0x65, 0x17, 0x96, 0xd0, 0xc7, 0x5e, 0x55, 0x20, 0x17, + 0x06, 0x74, 0x2d, 0x94, 0xe0, 0xfc, 0x09, 0xa2, 0xb1, 0x94, 0xe4, 0x83, + 0x0d, 0x8d, 0x9e, 0x26, 0x0a, 0x25, 0x93, 0xfb, 0xef, 0x4f, 0xb3, 0x0e, + 0x7a, 0x9b, 0x2f, 0x17, 0x94, 0xd8, 0xca, 0x64, 0x1e, 0xa6, 0x2e, 0xc9, + 0xf3, 0x54, 0x87, 0x34, 0xed, 0xf7, 0xa5, 0x00 +}; + +/* + * Message #1 + * Plaintext: "$U in and begin to hack." + * SHA-256: 6592ba987edef196b98beed2f618198b109ad93d9a32939e2134863f4f7aff4a + */ + +static const uint8_t m_1024_1[] = { /* message to be signed, 128 bytes */ + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, + 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20, + 0x65, 0x92, 0xba, 0x98, 0x7e, 0xde, 0xf1, 0x96, 0xb9, 0x8b, 0xee, 0xd2, + 0xf6, 0x18, 0x19, 0x8b, 0x10, 0x9a, 0xd9, 0x3d, 0x9a, 0x32, 0x93, 0x9e, + 0x21, 0x34, 0x86, 0x3f, 0x4f, 0x7a, 0xff, 0x4a +}; + +static const uint8_t s_1024_1[] = { /* signed message, 128 bytes */ + 0x30, 0x23, 0x3d, 0x81, 0xa0, 0xa5, 0xc3, 0xcc, 0x48, 0xb2, 0x69, 0xe6, + 0xe8, 0xb1, 0xc7, 0x34, 0xed, 0x56, 0xc6, 0x3b, 0xfb, 0xfe, 0x2f, 0xba, + 0x1d, 0xa5, 0x3f, 0x18, 0xa8, 0xb9, 0xd6, 0x80, 0x2f, 0x30, 0x39, 0x54, + 0x00, 0xed, 0x1b, 0x54, 0x4e, 0x28, 0x90, 0xc6, 0xe6, 0x58, 0x43, 0x1b, + 0x84, 0x94, 0x59, 0x46, 0xc2, 0xb3, 0x22, 0x38, 0x49, 0xf9, 0x2a, 0x7f, + 0xfc, 0xef, 0xe7, 0xb4, 0x6e, 0x77, 0xf9, 0x9c, 0x41, 0x79, 0x65, 0x72, + 0x18, 0xa4, 0xb6, 0x98, 0x28, 0x98, 0xba, 0xfe, 0xdc, 0x71, 0x8f, 0x58, + 0x2f, 0x6d, 0x25, 0x67, 0x35, 0x23, 0x6a, 0x98, 0xbb, 0xfa, 0x3b, 0x13, + 0x3b, 0x6f, 0x4b, 0x2a, 0x1e, 0x59, 0x7b, 0x0b, 0x62, 0x45, 0xe2, 0x4e, + 0xc1, 0x9d, 0x66, 0x38, 0x71, 0xca, 0xcf, 0x91, 0x66, 0x7d, 0x81, 0xf4, + 0x78, 0x68, 0x41, 0x08, 0xd1, 0xad, 0xda, 0xf0 +}; + +/* + * Message #2 + * Plaintext: "Twiddle bits in a core dump and write 'em back." + * SHA-256: 0633b9805544473dd4169773ff708f3868eb7f0ecbda0349012ea6ff7798b7b4 + */ + +static const uint8_t m_1024_2[] = { /* message to be signed, 128 bytes */ + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, + 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20, + 0x06, 0x33, 0xb9, 0x80, 0x55, 0x44, 0x47, 0x3d, 0xd4, 0x16, 0x97, 0x73, + 0xff, 0x70, 0x8f, 0x38, 0x68, 0xeb, 0x7f, 0x0e, 0xcb, 0xda, 0x03, 0x49, + 0x01, 0x2e, 0xa6, 0xff, 0x77, 0x98, 0xb7, 0xb4 +}; + +static const uint8_t s_1024_2[] = { /* signed message, 128 bytes */ + 0x6b, 0x29, 0x54, 0xa3, 0x05, 0x5a, 0x92, 0xa5, 0x65, 0x00, 0x72, 0x3a, + 0xdf, 0x85, 0x11, 0x47, 0x96, 0x7f, 0x67, 0x38, 0xf0, 0xae, 0x06, 0xe4, + 0x7e, 0x99, 0xc3, 0x17, 0x85, 0x7d, 0x03, 0xbe, 0xf8, 0xae, 0x1e, 0x89, + 0x99, 0x9e, 0x03, 0xb3, 0xe0, 0xfb, 0x15, 0xce, 0xed, 0x11, 0x21, 0xc4, + 0x20, 0x0d, 0x35, 0x84, 0xcc, 0xba, 0x53, 0xe0, 0x88, 0x5b, 0xa6, 0x25, + 0xdb, 0xa5, 0x6e, 0x4f, 0x06, 0xce, 0x81, 0xf7, 0x15, 0x15, 0x54, 0x15, + 0x11, 0x0d, 0x67, 0x73, 0x08, 0xd0, 0x15, 0x22, 0x8d, 0xef, 0x46, 0xda, + 0x61, 0x29, 0xc6, 0xe7, 0x37, 0x63, 0x2d, 0x0a, 0x82, 0x79, 0x17, 0xed, + 0xf4, 0x07, 0x79, 0xa2, 0x56, 0xb2, 0xbb, 0xf5, 0x4a, 0x40, 0x34, 0xec, + 0x9a, 0x92, 0x8f, 0xd4, 0x66, 0xc1, 0x83, 0xe0, 0x45, 0xa8, 0xe6, 0x4e, + 0x52, 0xb1, 0x11, 0xe9, 0x17, 0xc0, 0xcb, 0x5c +}; + +/* + * Message #3 + * Plaintext: "(But be careful typing <RET>)" + * SHA-256: 524bb716e35f7ca6e54fa59c75e395d4e6a9a567e2c928aa34c7ef7b09ed7b45 + */ + +static const uint8_t m_1024_3[] = { /* message to be signed, 128 bytes */ + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, + 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20, + 0x52, 0x4b, 0xb7, 0x16, 0xe3, 0x5f, 0x7c, 0xa6, 0xe5, 0x4f, 0xa5, 0x9c, + 0x75, 0xe3, 0x95, 0xd4, 0xe6, 0xa9, 0xa5, 0x67, 0xe2, 0xc9, 0x28, 0xaa, + 0x34, 0xc7, 0xef, 0x7b, 0x09, 0xed, 0x7b, 0x45 +}; + +static const uint8_t s_1024_3[] = { /* signed message, 128 bytes */ + 0x56, 0x20, 0xa9, 0xd5, 0x0e, 0x61, 0xa4, 0xb6, 0xfc, 0x8a, 0xf6, 0x27, + 0x40, 0x3c, 0x8c, 0x7a, 0x3f, 0x27, 0xdb, 0x1e, 0xb8, 0xf7, 0xf1, 0x35, + 0x21, 0xbc, 0xcd, 0x0d, 0xd9, 0x39, 0x98, 0x40, 0x1c, 0x48, 0x19, 0x85, + 0x57, 0xed, 0xa2, 0x59, 0x9d, 0xef, 0x13, 0x4c, 0xe7, 0x9e, 0x8b, 0x15, + 0x66, 0xce, 0xbf, 0x57, 0xcf, 0x43, 0x00, 0xf4, 0xb3, 0xf4, 0x6b, 0xcd, + 0x77, 0x34, 0xdd, 0xbd, 0x13, 0xdf, 0xe7, 0xf5, 0xb1, 0xe7, 0xa0, 0x2c, + 0xfc, 0x03, 0x00, 0x33, 0x78, 0x51, 0x28, 0x0c, 0x7c, 0x8a, 0x8b, 0xaa, + 0x8d, 0xb2, 0x72, 0x43, 0x54, 0x19, 0xf2, 0xf2, 0x53, 0xba, 0x16, 0x64, + 0x65, 0x69, 0xbd, 0xc4, 0x26, 0x08, 0xa2, 0x12, 0x4d, 0xbd, 0x6f, 0x9d, + 0x2f, 0x9d, 0x34, 0x41, 0xa8, 0x5f, 0x92, 0xa1, 0xc8, 0xa4, 0x27, 0xa8, + 0x34, 0x26, 0x3d, 0x4e, 0x6d, 0xc4, 0x0e, 0x66 +}; + diff --git a/sw/test-rsa.h b/sw/test-rsa.h new file mode 100644 index 0000000..400ffd0 --- /dev/null +++ b/sw/test-rsa.h @@ -0,0 +1,746 @@ +/* + * RSA signature test data for Cryptech project, automatically generated by + * test-rsa.py using PyCrypto version 2.6.1. Do not edit. + * + * Plaintext: "You can hack anything you want with TECO and DDT." + * SHA-256: 8e36fc9aa31724c32416263c0366a175fabbb92b741ca6496107074d0343b597 + */ + +/* 1024-bit RSA private key (PKCS #8) +-----BEGIN PRIVATE KEY----- +MIICdQIBADANBgkqhkiG9w0BAQEFAASCAl8wggJbAgEAAoGBAIwSaEpCTVJvbd4Z +B1P8H9EgFlZqats7PeBIOlC2Q1zla7wBmNJkX5Jkez8tF3l22Sn99c6c6PuhyhzB +dZtifQbZniKCJEzyby5MXZeSr20rPdrqiB9FX13mmtLN7ii4nLyAYFAQ4R8ZvdH2 +dRIWtxwhS7d4AyrWYhJkemIvSApfAgMBAAECgYAmL1Zy+AQwNuRSqawPvynFTuQI +Bta+kTXbEJWlLyrKBlkKVb0djfNn6zCWFmrR2A53nh4Gh0wUXRTGJg8znvPKJPcp +45znc7aGQFmDivvl5m/UkbqET6SB6JyCOCKzYa1Rtn3YFMkf/3MgzrWIhFv+UNH/ +I5lSjzJcCrN4mgI+AQJBALcTNa0mOWRXX+6jssbf65Cx6wmHsrrptXiP9gKfwdkx +697EzyvPDL8xwL20O+xBFehj866O/f8nOPP47imOPoECQQDD3gU8wD8MeWLqYcXI +AdERIuuk1VnL36QOzn9NoPF01DLJcrcbN24i5/9tcza3Kdec8fexJTh/PMBvR8Zr +w5jfAkAnFgrXtNl7+suYf4qjuxroAZRUrIwUK+F6pAG5/bG9VVMudIZmrAXkrBKi +beB9SEgNHYnhMtY3q4AVVohChwQBAkAR1I5Jf3691fcJOylUEcZEdxdYhAuOoac/ +qdCw8mvIpOCSshy1H5CpINGB1zEt72MvaF+SAr9n5dHmz3Pir4WlAkB/ZccJ5QBH +uBP0/flXdmhG5lC3MTMiiE7Rls/3L2t6S4xVDnQ81RYf7Car53WN7qSVSZnhDGsn +BJpghq2nYUH1 +-----END PRIVATE KEY----- +*/ + +static const uint8_t n_1024[] = { /* key component n, 128 bytes */ + 0x8c, 0x12, 0x68, 0x4a, 0x42, 0x4d, 0x52, 0x6f, 0x6d, 0xde, 0x19, 0x07, + 0x53, 0xfc, 0x1f, 0xd1, 0x20, 0x16, 0x56, 0x6a, 0x6a, 0xdb, 0x3b, 0x3d, + 0xe0, 0x48, 0x3a, 0x50, 0xb6, 0x43, 0x5c, 0xe5, 0x6b, 0xbc, 0x01, 0x98, + 0xd2, 0x64, 0x5f, 0x92, 0x64, 0x7b, 0x3f, 0x2d, 0x17, 0x79, 0x76, 0xd9, + 0x29, 0xfd, 0xf5, 0xce, 0x9c, 0xe8, 0xfb, 0xa1, 0xca, 0x1c, 0xc1, 0x75, + 0x9b, 0x62, 0x7d, 0x06, 0xd9, 0x9e, 0x22, 0x82, 0x24, 0x4c, 0xf2, 0x6f, + 0x2e, 0x4c, 0x5d, 0x97, 0x92, 0xaf, 0x6d, 0x2b, 0x3d, 0xda, 0xea, 0x88, + 0x1f, 0x45, 0x5f, 0x5d, 0xe6, 0x9a, 0xd2, 0xcd, 0xee, 0x28, 0xb8, 0x9c, + 0xbc, 0x80, 0x60, 0x50, 0x10, 0xe1, 0x1f, 0x19, 0xbd, 0xd1, 0xf6, 0x75, + 0x12, 0x16, 0xb7, 0x1c, 0x21, 0x4b, 0xb7, 0x78, 0x03, 0x2a, 0xd6, 0x62, + 0x12, 0x64, 0x7a, 0x62, 0x2f, 0x48, 0x0a, 0x5f +}; + +static const uint8_t e_1024[] = { /* key component e, 4 bytes */ + 0x00, 0x01, 0x00, 0x01 +}; + +static const uint8_t d_1024[] = { /* key component d, 128 bytes */ + 0x26, 0x2f, 0x56, 0x72, 0xf8, 0x04, 0x30, 0x36, 0xe4, 0x52, 0xa9, 0xac, + 0x0f, 0xbf, 0x29, 0xc5, 0x4e, 0xe4, 0x08, 0x06, 0xd6, 0xbe, 0x91, 0x35, + 0xdb, 0x10, 0x95, 0xa5, 0x2f, 0x2a, 0xca, 0x06, 0x59, 0x0a, 0x55, 0xbd, + 0x1d, 0x8d, 0xf3, 0x67, 0xeb, 0x30, 0x96, 0x16, 0x6a, 0xd1, 0xd8, 0x0e, + 0x77, 0x9e, 0x1e, 0x06, 0x87, 0x4c, 0x14, 0x5d, 0x14, 0xc6, 0x26, 0x0f, + 0x33, 0x9e, 0xf3, 0xca, 0x24, 0xf7, 0x29, 0xe3, 0x9c, 0xe7, 0x73, 0xb6, + 0x86, 0x40, 0x59, 0x83, 0x8a, 0xfb, 0xe5, 0xe6, 0x6f, 0xd4, 0x91, 0xba, + 0x84, 0x4f, 0xa4, 0x81, 0xe8, 0x9c, 0x82, 0x38, 0x22, 0xb3, 0x61, 0xad, + 0x51, 0xb6, 0x7d, 0xd8, 0x14, 0xc9, 0x1f, 0xff, 0x73, 0x20, 0xce, 0xb5, + 0x88, 0x84, 0x5b, 0xfe, 0x50, 0xd1, 0xff, 0x23, 0x99, 0x52, 0x8f, 0x32, + 0x5c, 0x0a, 0xb3, 0x78, 0x9a, 0x02, 0x3e, 0x01 +}; + +static const uint8_t p_1024[] = { /* key component p, 64 bytes */ + 0xb7, 0x13, 0x35, 0xad, 0x26, 0x39, 0x64, 0x57, 0x5f, 0xee, 0xa3, 0xb2, + 0xc6, 0xdf, 0xeb, 0x90, 0xb1, 0xeb, 0x09, 0x87, 0xb2, 0xba, 0xe9, 0xb5, + 0x78, 0x8f, 0xf6, 0x02, 0x9f, 0xc1, 0xd9, 0x31, 0xeb, 0xde, 0xc4, 0xcf, + 0x2b, 0xcf, 0x0c, 0xbf, 0x31, 0xc0, 0xbd, 0xb4, 0x3b, 0xec, 0x41, 0x15, + 0xe8, 0x63, 0xf3, 0xae, 0x8e, 0xfd, 0xff, 0x27, 0x38, 0xf3, 0xf8, 0xee, + 0x29, 0x8e, 0x3e, 0x81 +}; + +static const uint8_t q_1024[] = { /* key component q, 64 bytes */ + 0xc3, 0xde, 0x05, 0x3c, 0xc0, 0x3f, 0x0c, 0x79, 0x62, 0xea, 0x61, 0xc5, + 0xc8, 0x01, 0xd1, 0x11, 0x22, 0xeb, 0xa4, 0xd5, 0x59, 0xcb, 0xdf, 0xa4, + 0x0e, 0xce, 0x7f, 0x4d, 0xa0, 0xf1, 0x74, 0xd4, 0x32, 0xc9, 0x72, 0xb7, + 0x1b, 0x37, 0x6e, 0x22, 0xe7, 0xff, 0x6d, 0x73, 0x36, 0xb7, 0x29, 0xd7, + 0x9c, 0xf1, 0xf7, 0xb1, 0x25, 0x38, 0x7f, 0x3c, 0xc0, 0x6f, 0x47, 0xc6, + 0x6b, 0xc3, 0x98, 0xdf +}; + +static const uint8_t dP_1024[] = { /* key component dP, 64 bytes */ + 0x27, 0x16, 0x0a, 0xd7, 0xb4, 0xd9, 0x7b, 0xfa, 0xcb, 0x98, 0x7f, 0x8a, + 0xa3, 0xbb, 0x1a, 0xe8, 0x01, 0x94, 0x54, 0xac, 0x8c, 0x14, 0x2b, 0xe1, + 0x7a, 0xa4, 0x01, 0xb9, 0xfd, 0xb1, 0xbd, 0x55, 0x53, 0x2e, 0x74, 0x86, + 0x66, 0xac, 0x05, 0xe4, 0xac, 0x12, 0xa2, 0x6d, 0xe0, 0x7d, 0x48, 0x48, + 0x0d, 0x1d, 0x89, 0xe1, 0x32, 0xd6, 0x37, 0xab, 0x80, 0x15, 0x56, 0x88, + 0x42, 0x87, 0x04, 0x01 +}; + +static const uint8_t dQ_1024[] = { /* key component dQ, 64 bytes */ + 0x11, 0xd4, 0x8e, 0x49, 0x7f, 0x7e, 0xbd, 0xd5, 0xf7, 0x09, 0x3b, 0x29, + 0x54, 0x11, 0xc6, 0x44, 0x77, 0x17, 0x58, 0x84, 0x0b, 0x8e, 0xa1, 0xa7, + 0x3f, 0xa9, 0xd0, 0xb0, 0xf2, 0x6b, 0xc8, 0xa4, 0xe0, 0x92, 0xb2, 0x1c, + 0xb5, 0x1f, 0x90, 0xa9, 0x20, 0xd1, 0x81, 0xd7, 0x31, 0x2d, 0xef, 0x63, + 0x2f, 0x68, 0x5f, 0x92, 0x02, 0xbf, 0x67, 0xe5, 0xd1, 0xe6, 0xcf, 0x73, + 0xe2, 0xaf, 0x85, 0xa5 +}; + +static const uint8_t u_1024[] = { /* key component u, 64 bytes */ + 0x7f, 0x65, 0xc7, 0x09, 0xe5, 0x00, 0x47, 0xb8, 0x13, 0xf4, 0xfd, 0xf9, + 0x57, 0x76, 0x68, 0x46, 0xe6, 0x50, 0xb7, 0x31, 0x33, 0x22, 0x88, 0x4e, + 0xd1, 0x96, 0xcf, 0xf7, 0x2f, 0x6b, 0x7a, 0x4b, 0x8c, 0x55, 0x0e, 0x74, + 0x3c, 0xd5, 0x16, 0x1f, 0xec, 0x26, 0xab, 0xe7, 0x75, 0x8d, 0xee, 0xa4, + 0x95, 0x49, 0x99, 0xe1, 0x0c, 0x6b, 0x27, 0x04, 0x9a, 0x60, 0x86, 0xad, + 0xa7, 0x61, 0x41, 0xf5 +}; + +static const uint8_t m_1024[] = { /* message to be signed, 128 bytes */ + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, + 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20, + 0x8e, 0x36, 0xfc, 0x9a, 0xa3, 0x17, 0x24, 0xc3, 0x24, 0x16, 0x26, 0x3c, + 0x03, 0x66, 0xa1, 0x75, 0xfa, 0xbb, 0xb9, 0x2b, 0x74, 0x1c, 0xa6, 0x49, + 0x61, 0x07, 0x07, 0x4d, 0x03, 0x43, 0xb5, 0x97 +}; + +static const uint8_t s_1024[] = { /* signed message, 128 bytes */ + 0x3b, 0x09, 0xcc, 0x3d, 0x2f, 0xa1, 0x68, 0x1c, 0xa9, 0x29, 0x1b, 0xb7, + 0xcf, 0xc9, 0xe7, 0xb4, 0xfd, 0x3e, 0x5a, 0x22, 0x1c, 0x29, 0xdf, 0x4a, + 0x32, 0xcf, 0xa5, 0xae, 0x30, 0xd4, 0xee, 0x8f, 0x3a, 0xc8, 0xc1, 0xee, + 0x79, 0x40, 0xb2, 0xbf, 0xc7, 0x12, 0x82, 0x73, 0x3c, 0x6b, 0x8a, 0xd1, + 0xa4, 0x4a, 0x6d, 0x60, 0x9f, 0x00, 0xb4, 0x51, 0x8b, 0x6c, 0xcd, 0xae, + 0xad, 0xf4, 0x0a, 0x48, 0xd5, 0xb9, 0x4b, 0x9e, 0xca, 0x77, 0x10, 0xc2, + 0x9b, 0x26, 0x8c, 0x65, 0x17, 0x96, 0xd0, 0xc7, 0x5e, 0x55, 0x20, 0x17, + 0x06, 0x74, 0x2d, 0x94, 0xe0, 0xfc, 0x09, 0xa2, 0xb1, 0x94, 0xe4, 0x83, + 0x0d, 0x8d, 0x9e, 0x26, 0x0a, 0x25, 0x93, 0xfb, 0xef, 0x4f, 0xb3, 0x0e, + 0x7a, 0x9b, 0x2f, 0x17, 0x94, 0xd8, 0xca, 0x64, 0x1e, 0xa6, 0x2e, 0xc9, + 0xf3, 0x54, 0x87, 0x34, 0xed, 0xf7, 0xa5, 0x00 +}; + +/* 2048-bit RSA private key (PKCS #8) +-----BEGIN PRIVATE KEY----- +MIIEvgIBADANBgkqhkiG9w0BAQEFAASCBKgwggSkAgEAAoIBAQCzvgb90hKxeDJy +zeWz/F4JGZ3Acl1i3url3VPXHyoldyhuNC+8jf4iM7TGBYGLH+sYkBXWu9GD0erl +KBMJMTBO8OdXulSAJh8r1Z8qNPSVNguvNgGQlRDGc7tZJ6gWFlzM2g5flED24bN9 +6Ir9O1cZi7xMc0Nzkn9Rms5IwPW8OB4IZZlbFC6Ih9vUSp06Tm3rQ/eQJkhLFbzM +ejc9OH1LSpYtji44ohmy/jPJsmSlzwK5JSchZqbxl/msVw1t/nZS3loqKUMvzn9F +iARLiaIrUKNCmSmL8HqEt2qKt0ESHG0vX07h5W5iHIJOuKhqcX3li8nFcwsOV3AB +RsCRgeppAgMBAAECggEANEeTVQRjN4dUdRv6Me23lEIFJlKdYwKfpBhKKIoCAj+0 +XMmFEPzj7CLJ88bqNQMlqFFQaNLcT9Eg12Jelw/dkzhysYuaxGNSMbfCwc4BTd0Y +bO/yaJFS/cXvujDUrQf4GgVapOZENwrS4E5hDuLRpLaGIF5uQhFcQuoaEgM99m6H +TzOIhtu3DjdbfSsmkGVQ7xUVFcvaCrMVoq06dvUH4HpYTKeeqgcVv++XjIe83Nzv ++oN5U2oFOzrYpGGHN6jrekmmbEaxy8UHOySC6Y+UyRrPEy9q1ZgkkC9VCrM7E28/ +4PETw8MI7uNoosuFXofctKjtRvC5Sn9zW3dyv9NkAQKBgQDSkdDy4+xN2kA7gdry +4eLKUzKRNSbnoPrCu2TENUR8oTjbJ52LQEbGa9HIKaM33701hJsc34C6adJgoY9c +PoBcJgxOI7N40A/rI3c8krKS5X/ViBY3TzJsP3LaBKDdfioaTDVTjhYD6v2eu7Lt +4eIqa8sVA4PhLSVGRW53ZSYjwQKBgQDahY6cR8WgPseQJTkCbKyfKCSuz6nioZpC +stkpKhJepzE6AKZTLLWvNIPNT/khl40aby5seLNkY3Tb9cYBX2iShGv4cguPMiAl +hb7Uljz19i6YaX74gkTjsYpv44ddLSZp+/FTOl0C0I8WocQpb8B2d4BgvfxgHrHb +KCHnyihQqQKBgQC7PKPixt7hnzdMcrxhCpDiPbaSPgQZJSC1NXJ1sbPzalynKwPA +xefpGgiRBs02qsGRLBfNRcQuflhuSlqyuHTk+4Qnm0FEJSZyfLfS6dLWIjJYikjO +56I7dPPIfyMXsM75UVh9srNKypK4qciCFEBKXk1XoyeKe91QLf77NbsDQQKBgDnY +CLwNs56Lf8AEWmbt5XPr6GntxoabSH5HYXyoClzL3RgBfAWgXCeYuxrqBISD3XIV +5DAKc1IrkY94K4XJf6DpNLt7VNv+5MuJ783ORyzEkej+ZAHcWef74y1jCT386aI8 +ctEZLe3Ez1uqToa5cjTpxS3WnKvE9EeTBAabWLihAoGBAKft+PG+j+QhZeHSGxRz +mY6AQHH4z7IU94fmXiT2kTsG8/svhPNfsmVt7UCSJbCaYsrcuR2NonVV8wn/U793 +LcnLAV+WObeduMTBCasJw8IniFwFhhfkxOtmlevExE1I3ENwkRlJ7NdROky4pnd5 +LGmN2EOOlFijEGxBfw+Wb1rQ +-----END PRIVATE KEY----- +*/ + +static const uint8_t n_2048[] = { /* key component n, 256 bytes */ + 0xb3, 0xbe, 0x06, 0xfd, 0xd2, 0x12, 0xb1, 0x78, 0x32, 0x72, 0xcd, 0xe5, + 0xb3, 0xfc, 0x5e, 0x09, 0x19, 0x9d, 0xc0, 0x72, 0x5d, 0x62, 0xde, 0xea, + 0xe5, 0xdd, 0x53, 0xd7, 0x1f, 0x2a, 0x25, 0x77, 0x28, 0x6e, 0x34, 0x2f, + 0xbc, 0x8d, 0xfe, 0x22, 0x33, 0xb4, 0xc6, 0x05, 0x81, 0x8b, 0x1f, 0xeb, + 0x18, 0x90, 0x15, 0xd6, 0xbb, 0xd1, 0x83, 0xd1, 0xea, 0xe5, 0x28, 0x13, + 0x09, 0x31, 0x30, 0x4e, 0xf0, 0xe7, 0x57, 0xba, 0x54, 0x80, 0x26, 0x1f, + 0x2b, 0xd5, 0x9f, 0x2a, 0x34, 0xf4, 0x95, 0x36, 0x0b, 0xaf, 0x36, 0x01, + 0x90, 0x95, 0x10, 0xc6, 0x73, 0xbb, 0x59, 0x27, 0xa8, 0x16, 0x16, 0x5c, + 0xcc, 0xda, 0x0e, 0x5f, 0x94, 0x40, 0xf6, 0xe1, 0xb3, 0x7d, 0xe8, 0x8a, + 0xfd, 0x3b, 0x57, 0x19, 0x8b, 0xbc, 0x4c, 0x73, 0x43, 0x73, 0x92, 0x7f, + 0x51, 0x9a, 0xce, 0x48, 0xc0, 0xf5, 0xbc, 0x38, 0x1e, 0x08, 0x65, 0x99, + 0x5b, 0x14, 0x2e, 0x88, 0x87, 0xdb, 0xd4, 0x4a, 0x9d, 0x3a, 0x4e, 0x6d, + 0xeb, 0x43, 0xf7, 0x90, 0x26, 0x48, 0x4b, 0x15, 0xbc, 0xcc, 0x7a, 0x37, + 0x3d, 0x38, 0x7d, 0x4b, 0x4a, 0x96, 0x2d, 0x8e, 0x2e, 0x38, 0xa2, 0x19, + 0xb2, 0xfe, 0x33, 0xc9, 0xb2, 0x64, 0xa5, 0xcf, 0x02, 0xb9, 0x25, 0x27, + 0x21, 0x66, 0xa6, 0xf1, 0x97, 0xf9, 0xac, 0x57, 0x0d, 0x6d, 0xfe, 0x76, + 0x52, 0xde, 0x5a, 0x2a, 0x29, 0x43, 0x2f, 0xce, 0x7f, 0x45, 0x88, 0x04, + 0x4b, 0x89, 0xa2, 0x2b, 0x50, 0xa3, 0x42, 0x99, 0x29, 0x8b, 0xf0, 0x7a, + 0x84, 0xb7, 0x6a, 0x8a, 0xb7, 0x41, 0x12, 0x1c, 0x6d, 0x2f, 0x5f, 0x4e, + 0xe1, 0xe5, 0x6e, 0x62, 0x1c, 0x82, 0x4e, 0xb8, 0xa8, 0x6a, 0x71, 0x7d, + 0xe5, 0x8b, 0xc9, 0xc5, 0x73, 0x0b, 0x0e, 0x57, 0x70, 0x01, 0x46, 0xc0, + 0x91, 0x81, 0xea, 0x69 +}; + +static const uint8_t e_2048[] = { /* key component e, 4 bytes */ + 0x00, 0x01, 0x00, 0x01 +}; + +static const uint8_t d_2048[] = { /* key component d, 256 bytes */ + 0x34, 0x47, 0x93, 0x55, 0x04, 0x63, 0x37, 0x87, 0x54, 0x75, 0x1b, 0xfa, + 0x31, 0xed, 0xb7, 0x94, 0x42, 0x05, 0x26, 0x52, 0x9d, 0x63, 0x02, 0x9f, + 0xa4, 0x18, 0x4a, 0x28, 0x8a, 0x02, 0x02, 0x3f, 0xb4, 0x5c, 0xc9, 0x85, + 0x10, 0xfc, 0xe3, 0xec, 0x22, 0xc9, 0xf3, 0xc6, 0xea, 0x35, 0x03, 0x25, + 0xa8, 0x51, 0x50, 0x68, 0xd2, 0xdc, 0x4f, 0xd1, 0x20, 0xd7, 0x62, 0x5e, + 0x97, 0x0f, 0xdd, 0x93, 0x38, 0x72, 0xb1, 0x8b, 0x9a, 0xc4, 0x63, 0x52, + 0x31, 0xb7, 0xc2, 0xc1, 0xce, 0x01, 0x4d, 0xdd, 0x18, 0x6c, 0xef, 0xf2, + 0x68, 0x91, 0x52, 0xfd, 0xc5, 0xef, 0xba, 0x30, 0xd4, 0xad, 0x07, 0xf8, + 0x1a, 0x05, 0x5a, 0xa4, 0xe6, 0x44, 0x37, 0x0a, 0xd2, 0xe0, 0x4e, 0x61, + 0x0e, 0xe2, 0xd1, 0xa4, 0xb6, 0x86, 0x20, 0x5e, 0x6e, 0x42, 0x11, 0x5c, + 0x42, 0xea, 0x1a, 0x12, 0x03, 0x3d, 0xf6, 0x6e, 0x87, 0x4f, 0x33, 0x88, + 0x86, 0xdb, 0xb7, 0x0e, 0x37, 0x5b, 0x7d, 0x2b, 0x26, 0x90, 0x65, 0x50, + 0xef, 0x15, 0x15, 0x15, 0xcb, 0xda, 0x0a, 0xb3, 0x15, 0xa2, 0xad, 0x3a, + 0x76, 0xf5, 0x07, 0xe0, 0x7a, 0x58, 0x4c, 0xa7, 0x9e, 0xaa, 0x07, 0x15, + 0xbf, 0xef, 0x97, 0x8c, 0x87, 0xbc, 0xdc, 0xdc, 0xef, 0xfa, 0x83, 0x79, + 0x53, 0x6a, 0x05, 0x3b, 0x3a, 0xd8, 0xa4, 0x61, 0x87, 0x37, 0xa8, 0xeb, + 0x7a, 0x49, 0xa6, 0x6c, 0x46, 0xb1, 0xcb, 0xc5, 0x07, 0x3b, 0x24, 0x82, + 0xe9, 0x8f, 0x94, 0xc9, 0x1a, 0xcf, 0x13, 0x2f, 0x6a, 0xd5, 0x98, 0x24, + 0x90, 0x2f, 0x55, 0x0a, 0xb3, 0x3b, 0x13, 0x6f, 0x3f, 0xe0, 0xf1, 0x13, + 0xc3, 0xc3, 0x08, 0xee, 0xe3, 0x68, 0xa2, 0xcb, 0x85, 0x5e, 0x87, 0xdc, + 0xb4, 0xa8, 0xed, 0x46, 0xf0, 0xb9, 0x4a, 0x7f, 0x73, 0x5b, 0x77, 0x72, + 0xbf, 0xd3, 0x64, 0x01 +}; + +static const uint8_t p_2048[] = { /* key component p, 128 bytes */ + 0xd2, 0x91, 0xd0, 0xf2, 0xe3, 0xec, 0x4d, 0xda, 0x40, 0x3b, 0x81, 0xda, + 0xf2, 0xe1, 0xe2, 0xca, 0x53, 0x32, 0x91, 0x35, 0x26, 0xe7, 0xa0, 0xfa, + 0xc2, 0xbb, 0x64, 0xc4, 0x35, 0x44, 0x7c, 0xa1, 0x38, 0xdb, 0x27, 0x9d, + 0x8b, 0x40, 0x46, 0xc6, 0x6b, 0xd1, 0xc8, 0x29, 0xa3, 0x37, 0xdf, 0xbd, + 0x35, 0x84, 0x9b, 0x1c, 0xdf, 0x80, 0xba, 0x69, 0xd2, 0x60, 0xa1, 0x8f, + 0x5c, 0x3e, 0x80, 0x5c, 0x26, 0x0c, 0x4e, 0x23, 0xb3, 0x78, 0xd0, 0x0f, + 0xeb, 0x23, 0x77, 0x3c, 0x92, 0xb2, 0x92, 0xe5, 0x7f, 0xd5, 0x88, 0x16, + 0x37, 0x4f, 0x32, 0x6c, 0x3f, 0x72, 0xda, 0x04, 0xa0, 0xdd, 0x7e, 0x2a, + 0x1a, 0x4c, 0x35, 0x53, 0x8e, 0x16, 0x03, 0xea, 0xfd, 0x9e, 0xbb, 0xb2, + 0xed, 0xe1, 0xe2, 0x2a, 0x6b, 0xcb, 0x15, 0x03, 0x83, 0xe1, 0x2d, 0x25, + 0x46, 0x45, 0x6e, 0x77, 0x65, 0x26, 0x23, 0xc1 +}; + +static const uint8_t q_2048[] = { /* key component q, 128 bytes */ + 0xda, 0x85, 0x8e, 0x9c, 0x47, 0xc5, 0xa0, 0x3e, 0xc7, 0x90, 0x25, 0x39, + 0x02, 0x6c, 0xac, 0x9f, 0x28, 0x24, 0xae, 0xcf, 0xa9, 0xe2, 0xa1, 0x9a, + 0x42, 0xb2, 0xd9, 0x29, 0x2a, 0x12, 0x5e, 0xa7, 0x31, 0x3a, 0x00, 0xa6, + 0x53, 0x2c, 0xb5, 0xaf, 0x34, 0x83, 0xcd, 0x4f, 0xf9, 0x21, 0x97, 0x8d, + 0x1a, 0x6f, 0x2e, 0x6c, 0x78, 0xb3, 0x64, 0x63, 0x74, 0xdb, 0xf5, 0xc6, + 0x01, 0x5f, 0x68, 0x92, 0x84, 0x6b, 0xf8, 0x72, 0x0b, 0x8f, 0x32, 0x20, + 0x25, 0x85, 0xbe, 0xd4, 0x96, 0x3c, 0xf5, 0xf6, 0x2e, 0x98, 0x69, 0x7e, + 0xf8, 0x82, 0x44, 0xe3, 0xb1, 0x8a, 0x6f, 0xe3, 0x87, 0x5d, 0x2d, 0x26, + 0x69, 0xfb, 0xf1, 0x53, 0x3a, 0x5d, 0x02, 0xd0, 0x8f, 0x16, 0xa1, 0xc4, + 0x29, 0x6f, 0xc0, 0x76, 0x77, 0x80, 0x60, 0xbd, 0xfc, 0x60, 0x1e, 0xb1, + 0xdb, 0x28, 0x21, 0xe7, 0xca, 0x28, 0x50, 0xa9 +}; + +static const uint8_t dP_2048[] = { /* key component dP, 128 bytes */ + 0xbb, 0x3c, 0xa3, 0xe2, 0xc6, 0xde, 0xe1, 0x9f, 0x37, 0x4c, 0x72, 0xbc, + 0x61, 0x0a, 0x90, 0xe2, 0x3d, 0xb6, 0x92, 0x3e, 0x04, 0x19, 0x25, 0x20, + 0xb5, 0x35, 0x72, 0x75, 0xb1, 0xb3, 0xf3, 0x6a, 0x5c, 0xa7, 0x2b, 0x03, + 0xc0, 0xc5, 0xe7, 0xe9, 0x1a, 0x08, 0x91, 0x06, 0xcd, 0x36, 0xaa, 0xc1, + 0x91, 0x2c, 0x17, 0xcd, 0x45, 0xc4, 0x2e, 0x7e, 0x58, 0x6e, 0x4a, 0x5a, + 0xb2, 0xb8, 0x74, 0xe4, 0xfb, 0x84, 0x27, 0x9b, 0x41, 0x44, 0x25, 0x26, + 0x72, 0x7c, 0xb7, 0xd2, 0xe9, 0xd2, 0xd6, 0x22, 0x32, 0x58, 0x8a, 0x48, + 0xce, 0xe7, 0xa2, 0x3b, 0x74, 0xf3, 0xc8, 0x7f, 0x23, 0x17, 0xb0, 0xce, + 0xf9, 0x51, 0x58, 0x7d, 0xb2, 0xb3, 0x4a, 0xca, 0x92, 0xb8, 0xa9, 0xc8, + 0x82, 0x14, 0x40, 0x4a, 0x5e, 0x4d, 0x57, 0xa3, 0x27, 0x8a, 0x7b, 0xdd, + 0x50, 0x2d, 0xfe, 0xfb, 0x35, 0xbb, 0x03, 0x41 +}; + +static const uint8_t dQ_2048[] = { /* key component dQ, 128 bytes */ + 0x39, 0xd8, 0x08, 0xbc, 0x0d, 0xb3, 0x9e, 0x8b, 0x7f, 0xc0, 0x04, 0x5a, + 0x66, 0xed, 0xe5, 0x73, 0xeb, 0xe8, 0x69, 0xed, 0xc6, 0x86, 0x9b, 0x48, + 0x7e, 0x47, 0x61, 0x7c, 0xa8, 0x0a, 0x5c, 0xcb, 0xdd, 0x18, 0x01, 0x7c, + 0x05, 0xa0, 0x5c, 0x27, 0x98, 0xbb, 0x1a, 0xea, 0x04, 0x84, 0x83, 0xdd, + 0x72, 0x15, 0xe4, 0x30, 0x0a, 0x73, 0x52, 0x2b, 0x91, 0x8f, 0x78, 0x2b, + 0x85, 0xc9, 0x7f, 0xa0, 0xe9, 0x34, 0xbb, 0x7b, 0x54, 0xdb, 0xfe, 0xe4, + 0xcb, 0x89, 0xef, 0xcd, 0xce, 0x47, 0x2c, 0xc4, 0x91, 0xe8, 0xfe, 0x64, + 0x01, 0xdc, 0x59, 0xe7, 0xfb, 0xe3, 0x2d, 0x63, 0x09, 0x3d, 0xfc, 0xe9, + 0xa2, 0x3c, 0x72, 0xd1, 0x19, 0x2d, 0xed, 0xc4, 0xcf, 0x5b, 0xaa, 0x4e, + 0x86, 0xb9, 0x72, 0x34, 0xe9, 0xc5, 0x2d, 0xd6, 0x9c, 0xab, 0xc4, 0xf4, + 0x47, 0x93, 0x04, 0x06, 0x9b, 0x58, 0xb8, 0xa1 +}; + +static const uint8_t u_2048[] = { /* key component u, 128 bytes */ + 0xa7, 0xed, 0xf8, 0xf1, 0xbe, 0x8f, 0xe4, 0x21, 0x65, 0xe1, 0xd2, 0x1b, + 0x14, 0x73, 0x99, 0x8e, 0x80, 0x40, 0x71, 0xf8, 0xcf, 0xb2, 0x14, 0xf7, + 0x87, 0xe6, 0x5e, 0x24, 0xf6, 0x91, 0x3b, 0x06, 0xf3, 0xfb, 0x2f, 0x84, + 0xf3, 0x5f, 0xb2, 0x65, 0x6d, 0xed, 0x40, 0x92, 0x25, 0xb0, 0x9a, 0x62, + 0xca, 0xdc, 0xb9, 0x1d, 0x8d, 0xa2, 0x75, 0x55, 0xf3, 0x09, 0xff, 0x53, + 0xbf, 0x77, 0x2d, 0xc9, 0xcb, 0x01, 0x5f, 0x96, 0x39, 0xb7, 0x9d, 0xb8, + 0xc4, 0xc1, 0x09, 0xab, 0x09, 0xc3, 0xc2, 0x27, 0x88, 0x5c, 0x05, 0x86, + 0x17, 0xe4, 0xc4, 0xeb, 0x66, 0x95, 0xeb, 0xc4, 0xc4, 0x4d, 0x48, 0xdc, + 0x43, 0x70, 0x91, 0x19, 0x49, 0xec, 0xd7, 0x51, 0x3a, 0x4c, 0xb8, 0xa6, + 0x77, 0x79, 0x2c, 0x69, 0x8d, 0xd8, 0x43, 0x8e, 0x94, 0x58, 0xa3, 0x10, + 0x6c, 0x41, 0x7f, 0x0f, 0x96, 0x6f, 0x5a, 0xd0 +}; + +static const uint8_t m_2048[] = { /* message to be signed, 256 bytes */ + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, + 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20, 0x8e, 0x36, 0xfc, 0x9a, + 0xa3, 0x17, 0x24, 0xc3, 0x24, 0x16, 0x26, 0x3c, 0x03, 0x66, 0xa1, 0x75, + 0xfa, 0xbb, 0xb9, 0x2b, 0x74, 0x1c, 0xa6, 0x49, 0x61, 0x07, 0x07, 0x4d, + 0x03, 0x43, 0xb5, 0x97 +}; + +static const uint8_t s_2048[] = { /* signed message, 256 bytes */ + 0x4a, 0xf7, 0x47, 0xbb, 0xf2, 0x11, 0xd4, 0x4a, 0x03, 0xe5, 0xce, 0xbb, + 0x07, 0xae, 0xc9, 0x74, 0xf9, 0xc5, 0x05, 0xa2, 0xbc, 0xe8, 0x8f, 0x38, + 0x8c, 0xde, 0x7e, 0xdf, 0x29, 0xab, 0xd6, 0x0c, 0x9a, 0x3f, 0xdf, 0x4d, + 0xd1, 0xe4, 0x19, 0x51, 0x46, 0x94, 0xb6, 0x3b, 0xc3, 0xf1, 0x45, 0xba, + 0x30, 0x34, 0x18, 0x03, 0xf6, 0x86, 0xaf, 0x45, 0xe3, 0x1d, 0x33, 0x4e, + 0x08, 0x09, 0x95, 0xf5, 0x52, 0xad, 0xbe, 0x56, 0xb9, 0xb4, 0x5a, 0xed, + 0xd5, 0xd1, 0xff, 0x52, 0x59, 0x75, 0x7b, 0x95, 0xfa, 0x8f, 0x29, 0x87, + 0x48, 0x50, 0x37, 0xf6, 0x62, 0x7d, 0x4b, 0x4c, 0xdc, 0xe4, 0xee, 0xc2, + 0xaa, 0x93, 0x2f, 0x94, 0x97, 0x8a, 0xfe, 0xa8, 0x12, 0x31, 0x09, 0x4f, + 0x8a, 0xe7, 0x49, 0x69, 0xc8, 0xa0, 0xf0, 0xb6, 0xb8, 0x64, 0x53, 0x5b, + 0xce, 0xe2, 0xc7, 0xac, 0xa1, 0x20, 0x24, 0x90, 0xd3, 0xcd, 0xee, 0x08, + 0xfb, 0xa0, 0xa0, 0xf7, 0x5f, 0xaa, 0x3b, 0x4f, 0xa2, 0x3b, 0xb6, 0xe9, + 0x20, 0x79, 0xca, 0x8f, 0xb3, 0x68, 0x07, 0x4b, 0x79, 0x42, 0x60, 0xf3, + 0x18, 0xd1, 0x6f, 0xff, 0xdd, 0xe2, 0x96, 0x44, 0xea, 0x5c, 0x36, 0x43, + 0x07, 0xdc, 0xaa, 0xae, 0xba, 0x6b, 0xe9, 0x10, 0x0e, 0xf2, 0x12, 0xf3, + 0xb4, 0x6c, 0xeb, 0x8a, 0x1e, 0xf7, 0xfd, 0x23, 0x2c, 0x56, 0x30, 0xf4, + 0x29, 0xf3, 0x75, 0x7b, 0xd8, 0xfb, 0x80, 0xb9, 0x26, 0x01, 0x69, 0xa5, + 0x92, 0x7c, 0x56, 0x56, 0x2d, 0x0d, 0x91, 0x54, 0x81, 0x76, 0x21, 0xe5, + 0x70, 0x1f, 0x1e, 0x8f, 0xc3, 0xc8, 0x9f, 0x2a, 0xa5, 0xfa, 0x96, 0xf2, + 0x62, 0x99, 0xb8, 0x6e, 0xf0, 0x5f, 0x83, 0x15, 0x8f, 0x33, 0xe4, 0xe7, + 0xaf, 0xe2, 0xac, 0x23, 0x2e, 0x38, 0x5f, 0x45, 0x41, 0x9b, 0xe9, 0xb4, + 0x79, 0xd0, 0xf8, 0xcf +}; + +/* 4096-bit RSA private key (PKCS #8) +-----BEGIN PRIVATE KEY----- +MIIJQwIBADANBgkqhkiG9w0BAQEFAASCCS0wggkpAgEAAoICAQCuW+hI3vfWBlm/ +CiwGlQLLG/6WCAB5eNWfgWpjxBTKcGG+nKniAYrLtskG4fu0zJl5zf1HvGhJXW65 +6id3lcE4dCmtIDciebLexvkVcHGj+3dsh0i/RZ2hfNJQJa9BpzZ3DtsuDK4f5Tkj +1B5DScDEVfInSHDAU2rDxuDXBMnVXd08CDTLUiNU/BFQz0XEZJZ0Y4BeCmTm0cGE +V3LhahNgFh+1Lpi4cBwSt+EoFYWisPr9KXjAbHVCAYUHfvXvE1wXql0YexNTRHEf +EQG24EeEdj2XR72Ms36xrHhykIsSxuMjodsJlqG/JO/SAdeLMj4j68SD28F1fInW +2Szi1teXGDYBaMyT0Gw5kQ4TFlq8XED5hB5I8pOCtwuoQlw7vVjp1t90WL/bbA7Y +cwv9I4V3rOCkOkkCJe/mVB9Z0XmY7CnDYUXm211+oIcJyzTnk0iLV1cRiTAMEExK +S7wGJ1ZAh4CMTpk2FBx0tGb948Bny+gxjGLsYgNYUbp9GkOD8tYxo77k4Wjj7YgU +TA2A41zxA0LH/apfHRo8bSnIkLYw2NyzZ+OOGa7tW3oZ27yMlWnQGEErH6EcKNvB +2d4gUslWEjOn9XzqFnXRD2RUPfDPesMJ4Xlll2r7w4hMB9/VNkPtebE+rh5NB+cW +kvwrZWqlwXMCG/6o3a5Dden/b5387QIDAQABAoICAAlPxzv9DGdVt31IYcmIM7n9 +KL+CdeQG3AHEu5XQZvvYvJ+dZkU3p93xSRMhBnxFYPzsT1aBbWBdqQgsxSbRzJvj +OEaSrd8deLwFDFBkzOzhBSO6pdvxL9XsAJ9fI9jxwSrilDoFW1dAuqh7L5KQYcca +f/AxIjRjQBRsjp1tGApZFPObzJX/MPvc6l/ScftnE9HrbnOXQoRBN4CF2xDGxXog +NFlMv8M52YX2ZAPsAlMJ+J2ElXpRUIHR6vTXhvLZqdVpt8cS65lK0m/CTMEjgS5F +0kw9/JWDEIUUnOohZgv+qyq//h6o+MJoipZAmu5IJKFuefRAzDgmCoZ62rbSmnjU +m3N2DceHaAAw78Zf9RdT0w08fp/hXVO39HMnME5sFQGnlJsbNv74qfBIH6+8fDU7 +6rWWCq67E0gQkAnuYXczFSOPwZJn8E4Nce67UeyQq6CQEuC1XTrW34ZBUHy5pua9 +UuFymGYSNRBOUC3kurTYZmhpcAs9j8tVYSb62vNDZbvkYXRyPjpvRThpttCoa6Ds +3fiMfsN/AbpQqiSDxR2MX0okhHlrar2ucbNMJoxHf5iUo0Pj9LIRtmyIK/hh1uAI +eOks8M63wAmiuuHeDkXAMjuT3j59aS1jRSuJLZmxgnqttNbeYPqr74epMsFje7gy +0AXh5QS3BinxH7s4KONRAoIBAQDAPeQp+kSsYVR0SuiaSCn+O+9ytPUevVjt/Wcl +nx9XNTeaoj2rBwlqua50x1BPVXfOIXrQL2AV0xY+7aLmhVBQJ+FfA5hMFo0s6h+F +EeJdjBS1wd3uH40OUKbsIepnd7zxjbXgJzmChmaiVRUxwqi1mqWhMGgrvt42zwMZ +UAkXXbsyk1J3j+mlwsyLN887fHjW8tZPNr2f0uVs8ctmvSEIlDmMsaItu3DBN/Jz +6eOL6YBO1YGiinQHZk0aEbOd0uJ274wmQ24pAmrhH2btvuQ05/d+aSssJQBzoSqZ +3I81nSlZAjCigi6syj8Z9O90d2zdLQx4I6w46Rrat/Y3mWirAoIBAQDoL7Kjqv0i +Uk/VFbixpvUwf0GwlJnAuyrcpUlUqM5BBk/jbLTKPXzkTTIIzZvY32qmSNpdf/n/ +lNR7li07dJtd9RvfXDAFkf0GxwhRNOAn+KSWNqTQK7C8w2HGrdqkZRF3ZxQOWMbW +Z1ovSqcXwx3yFCSm/q6EdGSpXdiA9MmuDI5HO+U7t94VeTwg2slo8/kpLLtgF8OX +Ol65rO5lPuPRr0b2gVv8B+Lqd9wUThgQiDSPgLBGVbQ+GEERGL7JfzzxgW2YE3mL +0q0Susoi1hDVgnBw+TwzH74hyDSRVLDbMI2yIIfP77eYrygrUfF23eNGj6L+ogmD +f7+gC/oDWODHAoIBABt//waePXqnRayJFrMTRaaPrlYrWrE2BuWsjTfNhm80NqsR +MF8p14gD3dfoty1SHZxIH8huLoGQu6ru1ZHCWlXNDqlH215vD2zwZOflQgt9wWyq +ufOZYdU9ZlN7GowIjefEDNNu6QQp876fCzQeE4I/CBiB0zUGzcTrYhcZ4uMLzn6S +ooZl+Nd0gUwdBLEOwj6FaHDWdNPLGHS4Ng+RWItgoMbmljuSh7OsLCu2to1KLseY +NT4qLiTs1nS3OYmHJEw9QkAq/zQwm1du5Yt29jA3SqkzpDBhbqob0PtHmNjjjYml +DY4Br2maWOJ+rk5r0w/kpNb+y2Esv2GwVTFo6ZcCggEBAIg282ZxefAYuh0YkTIn +8NBy1+bwRwN6yrqHfW3dWqNrQJL7w1SinhKR9ziS50tkRv0m4HTaD6CRf9bBU+f9 +kOieU6vGOaYK75Z6TbbWfmr0xBocFLTL7PPQ7BvTAuJPKOAT6QBBtOUz3QTBlyWp +onfSuW3/HAM5BZUXKVz+PxOM6iuASAuw4ulWJqBfuqmH+DTfuU22o1ilNc1YVsOv +EZiCa+9SFNTXC5jimIqRBi0suyk1JjUdMpD7SbDuA3/S1b4ZYGJHipctEbxbORsW +2ulnjO+6SEb16GWJPs3EEb2Fzpsh2oty5xL8L2S6vh4uLpfGzKj2Bv7Og20xmYs9 +KSECggEBAKi6ccRd9c439uxW4+QRijrRl9nSMmHWR640EEwC6AgqaFgmQgxKf4e9 +2Hz84KVYFAipPDYAgFM6kY7j/S0rmbPrYGATyXmV+ugwfkH7ecc9BIWCjdvVWyb4 +fY6+qSRw5wtvcf2D9QsmsS15L4HTMn+GlnYN31Zda5Fg7TLIruADJniZeFYdI10F +RCCTi1YcQ4fsB+b+hsS7hgPHJ/ovQ8+6/Tt882cW4zCYIRSNPpxlaohH46rFiSkL +VQdslQAtvbuzCJ9CgHFPNLTlquSJ+DbXCq6AKFEiik73kw74VGHj34E8ZWa02GuD +470vqgm1JXKXNFHU9dkUZd/51e1fzso= +-----END PRIVATE KEY----- +*/ + +static const uint8_t n_4096[] = { /* key component n, 512 bytes */ + 0xae, 0x5b, 0xe8, 0x48, 0xde, 0xf7, 0xd6, 0x06, 0x59, 0xbf, 0x0a, 0x2c, + 0x06, 0x95, 0x02, 0xcb, 0x1b, 0xfe, 0x96, 0x08, 0x00, 0x79, 0x78, 0xd5, + 0x9f, 0x81, 0x6a, 0x63, 0xc4, 0x14, 0xca, 0x70, 0x61, 0xbe, 0x9c, 0xa9, + 0xe2, 0x01, 0x8a, 0xcb, 0xb6, 0xc9, 0x06, 0xe1, 0xfb, 0xb4, 0xcc, 0x99, + 0x79, 0xcd, 0xfd, 0x47, 0xbc, 0x68, 0x49, 0x5d, 0x6e, 0xb9, 0xea, 0x27, + 0x77, 0x95, 0xc1, 0x38, 0x74, 0x29, 0xad, 0x20, 0x37, 0x22, 0x79, 0xb2, + 0xde, 0xc6, 0xf9, 0x15, 0x70, 0x71, 0xa3, 0xfb, 0x77, 0x6c, 0x87, 0x48, + 0xbf, 0x45, 0x9d, 0xa1, 0x7c, 0xd2, 0x50, 0x25, 0xaf, 0x41, 0xa7, 0x36, + 0x77, 0x0e, 0xdb, 0x2e, 0x0c, 0xae, 0x1f, 0xe5, 0x39, 0x23, 0xd4, 0x1e, + 0x43, 0x49, 0xc0, 0xc4, 0x55, 0xf2, 0x27, 0x48, 0x70, 0xc0, 0x53, 0x6a, + 0xc3, 0xc6, 0xe0, 0xd7, 0x04, 0xc9, 0xd5, 0x5d, 0xdd, 0x3c, 0x08, 0x34, + 0xcb, 0x52, 0x23, 0x54, 0xfc, 0x11, 0x50, 0xcf, 0x45, 0xc4, 0x64, 0x96, + 0x74, 0x63, 0x80, 0x5e, 0x0a, 0x64, 0xe6, 0xd1, 0xc1, 0x84, 0x57, 0x72, + 0xe1, 0x6a, 0x13, 0x60, 0x16, 0x1f, 0xb5, 0x2e, 0x98, 0xb8, 0x70, 0x1c, + 0x12, 0xb7, 0xe1, 0x28, 0x15, 0x85, 0xa2, 0xb0, 0xfa, 0xfd, 0x29, 0x78, + 0xc0, 0x6c, 0x75, 0x42, 0x01, 0x85, 0x07, 0x7e, 0xf5, 0xef, 0x13, 0x5c, + 0x17, 0xaa, 0x5d, 0x18, 0x7b, 0x13, 0x53, 0x44, 0x71, 0x1f, 0x11, 0x01, + 0xb6, 0xe0, 0x47, 0x84, 0x76, 0x3d, 0x97, 0x47, 0xbd, 0x8c, 0xb3, 0x7e, + 0xb1, 0xac, 0x78, 0x72, 0x90, 0x8b, 0x12, 0xc6, 0xe3, 0x23, 0xa1, 0xdb, + 0x09, 0x96, 0xa1, 0xbf, 0x24, 0xef, 0xd2, 0x01, 0xd7, 0x8b, 0x32, 0x3e, + 0x23, 0xeb, 0xc4, 0x83, 0xdb, 0xc1, 0x75, 0x7c, 0x89, 0xd6, 0xd9, 0x2c, + 0xe2, 0xd6, 0xd7, 0x97, 0x18, 0x36, 0x01, 0x68, 0xcc, 0x93, 0xd0, 0x6c, + 0x39, 0x91, 0x0e, 0x13, 0x16, 0x5a, 0xbc, 0x5c, 0x40, 0xf9, 0x84, 0x1e, + 0x48, 0xf2, 0x93, 0x82, 0xb7, 0x0b, 0xa8, 0x42, 0x5c, 0x3b, 0xbd, 0x58, + 0xe9, 0xd6, 0xdf, 0x74, 0x58, 0xbf, 0xdb, 0x6c, 0x0e, 0xd8, 0x73, 0x0b, + 0xfd, 0x23, 0x85, 0x77, 0xac, 0xe0, 0xa4, 0x3a, 0x49, 0x02, 0x25, 0xef, + 0xe6, 0x54, 0x1f, 0x59, 0xd1, 0x79, 0x98, 0xec, 0x29, 0xc3, 0x61, 0x45, + 0xe6, 0xdb, 0x5d, 0x7e, 0xa0, 0x87, 0x09, 0xcb, 0x34, 0xe7, 0x93, 0x48, + 0x8b, 0x57, 0x57, 0x11, 0x89, 0x30, 0x0c, 0x10, 0x4c, 0x4a, 0x4b, 0xbc, + 0x06, 0x27, 0x56, 0x40, 0x87, 0x80, 0x8c, 0x4e, 0x99, 0x36, 0x14, 0x1c, + 0x74, 0xb4, 0x66, 0xfd, 0xe3, 0xc0, 0x67, 0xcb, 0xe8, 0x31, 0x8c, 0x62, + 0xec, 0x62, 0x03, 0x58, 0x51, 0xba, 0x7d, 0x1a, 0x43, 0x83, 0xf2, 0xd6, + 0x31, 0xa3, 0xbe, 0xe4, 0xe1, 0x68, 0xe3, 0xed, 0x88, 0x14, 0x4c, 0x0d, + 0x80, 0xe3, 0x5c, 0xf1, 0x03, 0x42, 0xc7, 0xfd, 0xaa, 0x5f, 0x1d, 0x1a, + 0x3c, 0x6d, 0x29, 0xc8, 0x90, 0xb6, 0x30, 0xd8, 0xdc, 0xb3, 0x67, 0xe3, + 0x8e, 0x19, 0xae, 0xed, 0x5b, 0x7a, 0x19, 0xdb, 0xbc, 0x8c, 0x95, 0x69, + 0xd0, 0x18, 0x41, 0x2b, 0x1f, 0xa1, 0x1c, 0x28, 0xdb, 0xc1, 0xd9, 0xde, + 0x20, 0x52, 0xc9, 0x56, 0x12, 0x33, 0xa7, 0xf5, 0x7c, 0xea, 0x16, 0x75, + 0xd1, 0x0f, 0x64, 0x54, 0x3d, 0xf0, 0xcf, 0x7a, 0xc3, 0x09, 0xe1, 0x79, + 0x65, 0x97, 0x6a, 0xfb, 0xc3, 0x88, 0x4c, 0x07, 0xdf, 0xd5, 0x36, 0x43, + 0xed, 0x79, 0xb1, 0x3e, 0xae, 0x1e, 0x4d, 0x07, 0xe7, 0x16, 0x92, 0xfc, + 0x2b, 0x65, 0x6a, 0xa5, 0xc1, 0x73, 0x02, 0x1b, 0xfe, 0xa8, 0xdd, 0xae, + 0x43, 0x75, 0xe9, 0xff, 0x6f, 0x9d, 0xfc, 0xed +}; + +static const uint8_t e_4096[] = { /* key component e, 4 bytes */ + 0x00, 0x01, 0x00, 0x01 +}; + +static const uint8_t d_4096[] = { /* key component d, 512 bytes */ + 0x09, 0x4f, 0xc7, 0x3b, 0xfd, 0x0c, 0x67, 0x55, 0xb7, 0x7d, 0x48, 0x61, + 0xc9, 0x88, 0x33, 0xb9, 0xfd, 0x28, 0xbf, 0x82, 0x75, 0xe4, 0x06, 0xdc, + 0x01, 0xc4, 0xbb, 0x95, 0xd0, 0x66, 0xfb, 0xd8, 0xbc, 0x9f, 0x9d, 0x66, + 0x45, 0x37, 0xa7, 0xdd, 0xf1, 0x49, 0x13, 0x21, 0x06, 0x7c, 0x45, 0x60, + 0xfc, 0xec, 0x4f, 0x56, 0x81, 0x6d, 0x60, 0x5d, 0xa9, 0x08, 0x2c, 0xc5, + 0x26, 0xd1, 0xcc, 0x9b, 0xe3, 0x38, 0x46, 0x92, 0xad, 0xdf, 0x1d, 0x78, + 0xbc, 0x05, 0x0c, 0x50, 0x64, 0xcc, 0xec, 0xe1, 0x05, 0x23, 0xba, 0xa5, + 0xdb, 0xf1, 0x2f, 0xd5, 0xec, 0x00, 0x9f, 0x5f, 0x23, 0xd8, 0xf1, 0xc1, + 0x2a, 0xe2, 0x94, 0x3a, 0x05, 0x5b, 0x57, 0x40, 0xba, 0xa8, 0x7b, 0x2f, + 0x92, 0x90, 0x61, 0xc7, 0x1a, 0x7f, 0xf0, 0x31, 0x22, 0x34, 0x63, 0x40, + 0x14, 0x6c, 0x8e, 0x9d, 0x6d, 0x18, 0x0a, 0x59, 0x14, 0xf3, 0x9b, 0xcc, + 0x95, 0xff, 0x30, 0xfb, 0xdc, 0xea, 0x5f, 0xd2, 0x71, 0xfb, 0x67, 0x13, + 0xd1, 0xeb, 0x6e, 0x73, 0x97, 0x42, 0x84, 0x41, 0x37, 0x80, 0x85, 0xdb, + 0x10, 0xc6, 0xc5, 0x7a, 0x20, 0x34, 0x59, 0x4c, 0xbf, 0xc3, 0x39, 0xd9, + 0x85, 0xf6, 0x64, 0x03, 0xec, 0x02, 0x53, 0x09, 0xf8, 0x9d, 0x84, 0x95, + 0x7a, 0x51, 0x50, 0x81, 0xd1, 0xea, 0xf4, 0xd7, 0x86, 0xf2, 0xd9, 0xa9, + 0xd5, 0x69, 0xb7, 0xc7, 0x12, 0xeb, 0x99, 0x4a, 0xd2, 0x6f, 0xc2, 0x4c, + 0xc1, 0x23, 0x81, 0x2e, 0x45, 0xd2, 0x4c, 0x3d, 0xfc, 0x95, 0x83, 0x10, + 0x85, 0x14, 0x9c, 0xea, 0x21, 0x66, 0x0b, 0xfe, 0xab, 0x2a, 0xbf, 0xfe, + 0x1e, 0xa8, 0xf8, 0xc2, 0x68, 0x8a, 0x96, 0x40, 0x9a, 0xee, 0x48, 0x24, + 0xa1, 0x6e, 0x79, 0xf4, 0x40, 0xcc, 0x38, 0x26, 0x0a, 0x86, 0x7a, 0xda, + 0xb6, 0xd2, 0x9a, 0x78, 0xd4, 0x9b, 0x73, 0x76, 0x0d, 0xc7, 0x87, 0x68, + 0x00, 0x30, 0xef, 0xc6, 0x5f, 0xf5, 0x17, 0x53, 0xd3, 0x0d, 0x3c, 0x7e, + 0x9f, 0xe1, 0x5d, 0x53, 0xb7, 0xf4, 0x73, 0x27, 0x30, 0x4e, 0x6c, 0x15, + 0x01, 0xa7, 0x94, 0x9b, 0x1b, 0x36, 0xfe, 0xf8, 0xa9, 0xf0, 0x48, 0x1f, + 0xaf, 0xbc, 0x7c, 0x35, 0x3b, 0xea, 0xb5, 0x96, 0x0a, 0xae, 0xbb, 0x13, + 0x48, 0x10, 0x90, 0x09, 0xee, 0x61, 0x77, 0x33, 0x15, 0x23, 0x8f, 0xc1, + 0x92, 0x67, 0xf0, 0x4e, 0x0d, 0x71, 0xee, 0xbb, 0x51, 0xec, 0x90, 0xab, + 0xa0, 0x90, 0x12, 0xe0, 0xb5, 0x5d, 0x3a, 0xd6, 0xdf, 0x86, 0x41, 0x50, + 0x7c, 0xb9, 0xa6, 0xe6, 0xbd, 0x52, 0xe1, 0x72, 0x98, 0x66, 0x12, 0x35, + 0x10, 0x4e, 0x50, 0x2d, 0xe4, 0xba, 0xb4, 0xd8, 0x66, 0x68, 0x69, 0x70, + 0x0b, 0x3d, 0x8f, 0xcb, 0x55, 0x61, 0x26, 0xfa, 0xda, 0xf3, 0x43, 0x65, + 0xbb, 0xe4, 0x61, 0x74, 0x72, 0x3e, 0x3a, 0x6f, 0x45, 0x38, 0x69, 0xb6, + 0xd0, 0xa8, 0x6b, 0xa0, 0xec, 0xdd, 0xf8, 0x8c, 0x7e, 0xc3, 0x7f, 0x01, + 0xba, 0x50, 0xaa, 0x24, 0x83, 0xc5, 0x1d, 0x8c, 0x5f, 0x4a, 0x24, 0x84, + 0x79, 0x6b, 0x6a, 0xbd, 0xae, 0x71, 0xb3, 0x4c, 0x26, 0x8c, 0x47, 0x7f, + 0x98, 0x94, 0xa3, 0x43, 0xe3, 0xf4, 0xb2, 0x11, 0xb6, 0x6c, 0x88, 0x2b, + 0xf8, 0x61, 0xd6, 0xe0, 0x08, 0x78, 0xe9, 0x2c, 0xf0, 0xce, 0xb7, 0xc0, + 0x09, 0xa2, 0xba, 0xe1, 0xde, 0x0e, 0x45, 0xc0, 0x32, 0x3b, 0x93, 0xde, + 0x3e, 0x7d, 0x69, 0x2d, 0x63, 0x45, 0x2b, 0x89, 0x2d, 0x99, 0xb1, 0x82, + 0x7a, 0xad, 0xb4, 0xd6, 0xde, 0x60, 0xfa, 0xab, 0xef, 0x87, 0xa9, 0x32, + 0xc1, 0x63, 0x7b, 0xb8, 0x32, 0xd0, 0x05, 0xe1, 0xe5, 0x04, 0xb7, 0x06, + 0x29, 0xf1, 0x1f, 0xbb, 0x38, 0x28, 0xe3, 0x51 +}; + +static const uint8_t p_4096[] = { /* key component p, 256 bytes */ + 0xc0, 0x3d, 0xe4, 0x29, 0xfa, 0x44, 0xac, 0x61, 0x54, 0x74, 0x4a, 0xe8, + 0x9a, 0x48, 0x29, 0xfe, 0x3b, 0xef, 0x72, 0xb4, 0xf5, 0x1e, 0xbd, 0x58, + 0xed, 0xfd, 0x67, 0x25, 0x9f, 0x1f, 0x57, 0x35, 0x37, 0x9a, 0xa2, 0x3d, + 0xab, 0x07, 0x09, 0x6a, 0xb9, 0xae, 0x74, 0xc7, 0x50, 0x4f, 0x55, 0x77, + 0xce, 0x21, 0x7a, 0xd0, 0x2f, 0x60, 0x15, 0xd3, 0x16, 0x3e, 0xed, 0xa2, + 0xe6, 0x85, 0x50, 0x50, 0x27, 0xe1, 0x5f, 0x03, 0x98, 0x4c, 0x16, 0x8d, + 0x2c, 0xea, 0x1f, 0x85, 0x11, 0xe2, 0x5d, 0x8c, 0x14, 0xb5, 0xc1, 0xdd, + 0xee, 0x1f, 0x8d, 0x0e, 0x50, 0xa6, 0xec, 0x21, 0xea, 0x67, 0x77, 0xbc, + 0xf1, 0x8d, 0xb5, 0xe0, 0x27, 0x39, 0x82, 0x86, 0x66, 0xa2, 0x55, 0x15, + 0x31, 0xc2, 0xa8, 0xb5, 0x9a, 0xa5, 0xa1, 0x30, 0x68, 0x2b, 0xbe, 0xde, + 0x36, 0xcf, 0x03, 0x19, 0x50, 0x09, 0x17, 0x5d, 0xbb, 0x32, 0x93, 0x52, + 0x77, 0x8f, 0xe9, 0xa5, 0xc2, 0xcc, 0x8b, 0x37, 0xcf, 0x3b, 0x7c, 0x78, + 0xd6, 0xf2, 0xd6, 0x4f, 0x36, 0xbd, 0x9f, 0xd2, 0xe5, 0x6c, 0xf1, 0xcb, + 0x66, 0xbd, 0x21, 0x08, 0x94, 0x39, 0x8c, 0xb1, 0xa2, 0x2d, 0xbb, 0x70, + 0xc1, 0x37, 0xf2, 0x73, 0xe9, 0xe3, 0x8b, 0xe9, 0x80, 0x4e, 0xd5, 0x81, + 0xa2, 0x8a, 0x74, 0x07, 0x66, 0x4d, 0x1a, 0x11, 0xb3, 0x9d, 0xd2, 0xe2, + 0x76, 0xef, 0x8c, 0x26, 0x43, 0x6e, 0x29, 0x02, 0x6a, 0xe1, 0x1f, 0x66, + 0xed, 0xbe, 0xe4, 0x34, 0xe7, 0xf7, 0x7e, 0x69, 0x2b, 0x2c, 0x25, 0x00, + 0x73, 0xa1, 0x2a, 0x99, 0xdc, 0x8f, 0x35, 0x9d, 0x29, 0x59, 0x02, 0x30, + 0xa2, 0x82, 0x2e, 0xac, 0xca, 0x3f, 0x19, 0xf4, 0xef, 0x74, 0x77, 0x6c, + 0xdd, 0x2d, 0x0c, 0x78, 0x23, 0xac, 0x38, 0xe9, 0x1a, 0xda, 0xb7, 0xf6, + 0x37, 0x99, 0x68, 0xab +}; + +static const uint8_t q_4096[] = { /* key component q, 256 bytes */ + 0xe8, 0x2f, 0xb2, 0xa3, 0xaa, 0xfd, 0x22, 0x52, 0x4f, 0xd5, 0x15, 0xb8, + 0xb1, 0xa6, 0xf5, 0x30, 0x7f, 0x41, 0xb0, 0x94, 0x99, 0xc0, 0xbb, 0x2a, + 0xdc, 0xa5, 0x49, 0x54, 0xa8, 0xce, 0x41, 0x06, 0x4f, 0xe3, 0x6c, 0xb4, + 0xca, 0x3d, 0x7c, 0xe4, 0x4d, 0x32, 0x08, 0xcd, 0x9b, 0xd8, 0xdf, 0x6a, + 0xa6, 0x48, 0xda, 0x5d, 0x7f, 0xf9, 0xff, 0x94, 0xd4, 0x7b, 0x96, 0x2d, + 0x3b, 0x74, 0x9b, 0x5d, 0xf5, 0x1b, 0xdf, 0x5c, 0x30, 0x05, 0x91, 0xfd, + 0x06, 0xc7, 0x08, 0x51, 0x34, 0xe0, 0x27, 0xf8, 0xa4, 0x96, 0x36, 0xa4, + 0xd0, 0x2b, 0xb0, 0xbc, 0xc3, 0x61, 0xc6, 0xad, 0xda, 0xa4, 0x65, 0x11, + 0x77, 0x67, 0x14, 0x0e, 0x58, 0xc6, 0xd6, 0x67, 0x5a, 0x2f, 0x4a, 0xa7, + 0x17, 0xc3, 0x1d, 0xf2, 0x14, 0x24, 0xa6, 0xfe, 0xae, 0x84, 0x74, 0x64, + 0xa9, 0x5d, 0xd8, 0x80, 0xf4, 0xc9, 0xae, 0x0c, 0x8e, 0x47, 0x3b, 0xe5, + 0x3b, 0xb7, 0xde, 0x15, 0x79, 0x3c, 0x20, 0xda, 0xc9, 0x68, 0xf3, 0xf9, + 0x29, 0x2c, 0xbb, 0x60, 0x17, 0xc3, 0x97, 0x3a, 0x5e, 0xb9, 0xac, 0xee, + 0x65, 0x3e, 0xe3, 0xd1, 0xaf, 0x46, 0xf6, 0x81, 0x5b, 0xfc, 0x07, 0xe2, + 0xea, 0x77, 0xdc, 0x14, 0x4e, 0x18, 0x10, 0x88, 0x34, 0x8f, 0x80, 0xb0, + 0x46, 0x55, 0xb4, 0x3e, 0x18, 0x41, 0x11, 0x18, 0xbe, 0xc9, 0x7f, 0x3c, + 0xf1, 0x81, 0x6d, 0x98, 0x13, 0x79, 0x8b, 0xd2, 0xad, 0x12, 0xba, 0xca, + 0x22, 0xd6, 0x10, 0xd5, 0x82, 0x70, 0x70, 0xf9, 0x3c, 0x33, 0x1f, 0xbe, + 0x21, 0xc8, 0x34, 0x91, 0x54, 0xb0, 0xdb, 0x30, 0x8d, 0xb2, 0x20, 0x87, + 0xcf, 0xef, 0xb7, 0x98, 0xaf, 0x28, 0x2b, 0x51, 0xf1, 0x76, 0xdd, 0xe3, + 0x46, 0x8f, 0xa2, 0xfe, 0xa2, 0x09, 0x83, 0x7f, 0xbf, 0xa0, 0x0b, 0xfa, + 0x03, 0x58, 0xe0, 0xc7 +}; + +static const uint8_t dP_4096[] = { /* key component dP, 256 bytes */ + 0x1b, 0x7f, 0xff, 0x06, 0x9e, 0x3d, 0x7a, 0xa7, 0x45, 0xac, 0x89, 0x16, + 0xb3, 0x13, 0x45, 0xa6, 0x8f, 0xae, 0x56, 0x2b, 0x5a, 0xb1, 0x36, 0x06, + 0xe5, 0xac, 0x8d, 0x37, 0xcd, 0x86, 0x6f, 0x34, 0x36, 0xab, 0x11, 0x30, + 0x5f, 0x29, 0xd7, 0x88, 0x03, 0xdd, 0xd7, 0xe8, 0xb7, 0x2d, 0x52, 0x1d, + 0x9c, 0x48, 0x1f, 0xc8, 0x6e, 0x2e, 0x81, 0x90, 0xbb, 0xaa, 0xee, 0xd5, + 0x91, 0xc2, 0x5a, 0x55, 0xcd, 0x0e, 0xa9, 0x47, 0xdb, 0x5e, 0x6f, 0x0f, + 0x6c, 0xf0, 0x64, 0xe7, 0xe5, 0x42, 0x0b, 0x7d, 0xc1, 0x6c, 0xaa, 0xb9, + 0xf3, 0x99, 0x61, 0xd5, 0x3d, 0x66, 0x53, 0x7b, 0x1a, 0x8c, 0x08, 0x8d, + 0xe7, 0xc4, 0x0c, 0xd3, 0x6e, 0xe9, 0x04, 0x29, 0xf3, 0xbe, 0x9f, 0x0b, + 0x34, 0x1e, 0x13, 0x82, 0x3f, 0x08, 0x18, 0x81, 0xd3, 0x35, 0x06, 0xcd, + 0xc4, 0xeb, 0x62, 0x17, 0x19, 0xe2, 0xe3, 0x0b, 0xce, 0x7e, 0x92, 0xa2, + 0x86, 0x65, 0xf8, 0xd7, 0x74, 0x81, 0x4c, 0x1d, 0x04, 0xb1, 0x0e, 0xc2, + 0x3e, 0x85, 0x68, 0x70, 0xd6, 0x74, 0xd3, 0xcb, 0x18, 0x74, 0xb8, 0x36, + 0x0f, 0x91, 0x58, 0x8b, 0x60, 0xa0, 0xc6, 0xe6, 0x96, 0x3b, 0x92, 0x87, + 0xb3, 0xac, 0x2c, 0x2b, 0xb6, 0xb6, 0x8d, 0x4a, 0x2e, 0xc7, 0x98, 0x35, + 0x3e, 0x2a, 0x2e, 0x24, 0xec, 0xd6, 0x74, 0xb7, 0x39, 0x89, 0x87, 0x24, + 0x4c, 0x3d, 0x42, 0x40, 0x2a, 0xff, 0x34, 0x30, 0x9b, 0x57, 0x6e, 0xe5, + 0x8b, 0x76, 0xf6, 0x30, 0x37, 0x4a, 0xa9, 0x33, 0xa4, 0x30, 0x61, 0x6e, + 0xaa, 0x1b, 0xd0, 0xfb, 0x47, 0x98, 0xd8, 0xe3, 0x8d, 0x89, 0xa5, 0x0d, + 0x8e, 0x01, 0xaf, 0x69, 0x9a, 0x58, 0xe2, 0x7e, 0xae, 0x4e, 0x6b, 0xd3, + 0x0f, 0xe4, 0xa4, 0xd6, 0xfe, 0xcb, 0x61, 0x2c, 0xbf, 0x61, 0xb0, 0x55, + 0x31, 0x68, 0xe9, 0x97 +}; + +static const uint8_t dQ_4096[] = { /* key component dQ, 256 bytes */ + 0x88, 0x36, 0xf3, 0x66, 0x71, 0x79, 0xf0, 0x18, 0xba, 0x1d, 0x18, 0x91, + 0x32, 0x27, 0xf0, 0xd0, 0x72, 0xd7, 0xe6, 0xf0, 0x47, 0x03, 0x7a, 0xca, + 0xba, 0x87, 0x7d, 0x6d, 0xdd, 0x5a, 0xa3, 0x6b, 0x40, 0x92, 0xfb, 0xc3, + 0x54, 0xa2, 0x9e, 0x12, 0x91, 0xf7, 0x38, 0x92, 0xe7, 0x4b, 0x64, 0x46, + 0xfd, 0x26, 0xe0, 0x74, 0xda, 0x0f, 0xa0, 0x91, 0x7f, 0xd6, 0xc1, 0x53, + 0xe7, 0xfd, 0x90, 0xe8, 0x9e, 0x53, 0xab, 0xc6, 0x39, 0xa6, 0x0a, 0xef, + 0x96, 0x7a, 0x4d, 0xb6, 0xd6, 0x7e, 0x6a, 0xf4, 0xc4, 0x1a, 0x1c, 0x14, + 0xb4, 0xcb, 0xec, 0xf3, 0xd0, 0xec, 0x1b, 0xd3, 0x02, 0xe2, 0x4f, 0x28, + 0xe0, 0x13, 0xe9, 0x00, 0x41, 0xb4, 0xe5, 0x33, 0xdd, 0x04, 0xc1, 0x97, + 0x25, 0xa9, 0xa2, 0x77, 0xd2, 0xb9, 0x6d, 0xff, 0x1c, 0x03, 0x39, 0x05, + 0x95, 0x17, 0x29, 0x5c, 0xfe, 0x3f, 0x13, 0x8c, 0xea, 0x2b, 0x80, 0x48, + 0x0b, 0xb0, 0xe2, 0xe9, 0x56, 0x26, 0xa0, 0x5f, 0xba, 0xa9, 0x87, 0xf8, + 0x34, 0xdf, 0xb9, 0x4d, 0xb6, 0xa3, 0x58, 0xa5, 0x35, 0xcd, 0x58, 0x56, + 0xc3, 0xaf, 0x11, 0x98, 0x82, 0x6b, 0xef, 0x52, 0x14, 0xd4, 0xd7, 0x0b, + 0x98, 0xe2, 0x98, 0x8a, 0x91, 0x06, 0x2d, 0x2c, 0xbb, 0x29, 0x35, 0x26, + 0x35, 0x1d, 0x32, 0x90, 0xfb, 0x49, 0xb0, 0xee, 0x03, 0x7f, 0xd2, 0xd5, + 0xbe, 0x19, 0x60, 0x62, 0x47, 0x8a, 0x97, 0x2d, 0x11, 0xbc, 0x5b, 0x39, + 0x1b, 0x16, 0xda, 0xe9, 0x67, 0x8c, 0xef, 0xba, 0x48, 0x46, 0xf5, 0xe8, + 0x65, 0x89, 0x3e, 0xcd, 0xc4, 0x11, 0xbd, 0x85, 0xce, 0x9b, 0x21, 0xda, + 0x8b, 0x72, 0xe7, 0x12, 0xfc, 0x2f, 0x64, 0xba, 0xbe, 0x1e, 0x2e, 0x2e, + 0x97, 0xc6, 0xcc, 0xa8, 0xf6, 0x06, 0xfe, 0xce, 0x83, 0x6d, 0x31, 0x99, + 0x8b, 0x3d, 0x29, 0x21 +}; + +static const uint8_t u_4096[] = { /* key component u, 256 bytes */ + 0xa8, 0xba, 0x71, 0xc4, 0x5d, 0xf5, 0xce, 0x37, 0xf6, 0xec, 0x56, 0xe3, + 0xe4, 0x11, 0x8a, 0x3a, 0xd1, 0x97, 0xd9, 0xd2, 0x32, 0x61, 0xd6, 0x47, + 0xae, 0x34, 0x10, 0x4c, 0x02, 0xe8, 0x08, 0x2a, 0x68, 0x58, 0x26, 0x42, + 0x0c, 0x4a, 0x7f, 0x87, 0xbd, 0xd8, 0x7c, 0xfc, 0xe0, 0xa5, 0x58, 0x14, + 0x08, 0xa9, 0x3c, 0x36, 0x00, 0x80, 0x53, 0x3a, 0x91, 0x8e, 0xe3, 0xfd, + 0x2d, 0x2b, 0x99, 0xb3, 0xeb, 0x60, 0x60, 0x13, 0xc9, 0x79, 0x95, 0xfa, + 0xe8, 0x30, 0x7e, 0x41, 0xfb, 0x79, 0xc7, 0x3d, 0x04, 0x85, 0x82, 0x8d, + 0xdb, 0xd5, 0x5b, 0x26, 0xf8, 0x7d, 0x8e, 0xbe, 0xa9, 0x24, 0x70, 0xe7, + 0x0b, 0x6f, 0x71, 0xfd, 0x83, 0xf5, 0x0b, 0x26, 0xb1, 0x2d, 0x79, 0x2f, + 0x81, 0xd3, 0x32, 0x7f, 0x86, 0x96, 0x76, 0x0d, 0xdf, 0x56, 0x5d, 0x6b, + 0x91, 0x60, 0xed, 0x32, 0xc8, 0xae, 0xe0, 0x03, 0x26, 0x78, 0x99, 0x78, + 0x56, 0x1d, 0x23, 0x5d, 0x05, 0x44, 0x20, 0x93, 0x8b, 0x56, 0x1c, 0x43, + 0x87, 0xec, 0x07, 0xe6, 0xfe, 0x86, 0xc4, 0xbb, 0x86, 0x03, 0xc7, 0x27, + 0xfa, 0x2f, 0x43, 0xcf, 0xba, 0xfd, 0x3b, 0x7c, 0xf3, 0x67, 0x16, 0xe3, + 0x30, 0x98, 0x21, 0x14, 0x8d, 0x3e, 0x9c, 0x65, 0x6a, 0x88, 0x47, 0xe3, + 0xaa, 0xc5, 0x89, 0x29, 0x0b, 0x55, 0x07, 0x6c, 0x95, 0x00, 0x2d, 0xbd, + 0xbb, 0xb3, 0x08, 0x9f, 0x42, 0x80, 0x71, 0x4f, 0x34, 0xb4, 0xe5, 0xaa, + 0xe4, 0x89, 0xf8, 0x36, 0xd7, 0x0a, 0xae, 0x80, 0x28, 0x51, 0x22, 0x8a, + 0x4e, 0xf7, 0x93, 0x0e, 0xf8, 0x54, 0x61, 0xe3, 0xdf, 0x81, 0x3c, 0x65, + 0x66, 0xb4, 0xd8, 0x6b, 0x83, 0xe3, 0xbd, 0x2f, 0xaa, 0x09, 0xb5, 0x25, + 0x72, 0x97, 0x34, 0x51, 0xd4, 0xf5, 0xd9, 0x14, 0x65, 0xdf, 0xf9, 0xd5, + 0xed, 0x5f, 0xce, 0xca +}; + +static const uint8_t m_4096[] = { /* message to be signed, 512 bytes */ + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, + 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20, + 0x8e, 0x36, 0xfc, 0x9a, 0xa3, 0x17, 0x24, 0xc3, 0x24, 0x16, 0x26, 0x3c, + 0x03, 0x66, 0xa1, 0x75, 0xfa, 0xbb, 0xb9, 0x2b, 0x74, 0x1c, 0xa6, 0x49, + 0x61, 0x07, 0x07, 0x4d, 0x03, 0x43, 0xb5, 0x97 +}; + +static const uint8_t s_4096[] = { /* signed message, 512 bytes */ + 0xad, 0x46, 0xb3, 0x86, 0xb3, 0x3d, 0x13, 0xb7, 0x56, 0x0c, 0xbf, 0xd8, + 0xfe, 0xf4, 0xf2, 0x0d, 0x2d, 0x5a, 0x28, 0xad, 0xb5, 0x43, 0x7b, 0x88, + 0x5f, 0x01, 0xa4, 0x01, 0xd6, 0x28, 0x3b, 0x10, 0x0e, 0x22, 0x89, 0x11, + 0xc4, 0x3e, 0xcf, 0xbb, 0xaf, 0xd6, 0x82, 0xd9, 0x51, 0xb1, 0x93, 0xd6, + 0xc8, 0x7b, 0x89, 0xd4, 0x7a, 0xd1, 0xd0, 0x08, 0x39, 0x6b, 0x13, 0xb5, + 0x55, 0x75, 0x61, 0xf3, 0xce, 0x47, 0x77, 0x01, 0x29, 0xee, 0x07, 0x5e, + 0x4d, 0xdf, 0x83, 0x80, 0x18, 0x6d, 0xb8, 0x57, 0x14, 0x45, 0x81, 0x27, + 0x1e, 0xe3, 0x2f, 0xdf, 0x0a, 0xba, 0x3b, 0x0f, 0x12, 0x07, 0xff, 0x7f, + 0x35, 0x44, 0x75, 0xe3, 0xa8, 0x39, 0x25, 0x88, 0x3c, 0x32, 0x9e, 0x8a, + 0xd6, 0xfa, 0x3f, 0x89, 0xa4, 0x6d, 0x8a, 0x9d, 0x3d, 0x75, 0x2c, 0x6f, + 0x2a, 0x85, 0xd8, 0x96, 0x47, 0x4b, 0xde, 0x2a, 0x6b, 0x5e, 0xe1, 0x88, + 0xcd, 0x37, 0xfb, 0x17, 0xe2, 0x84, 0x81, 0xe7, 0xa8, 0x7c, 0x47, 0x8e, + 0x69, 0x69, 0x91, 0x37, 0x71, 0x97, 0x3f, 0xd1, 0x1a, 0x3e, 0x34, 0x84, + 0x52, 0xe0, 0x08, 0x2c, 0x4c, 0xdc, 0x02, 0x11, 0x08, 0x30, 0xc9, 0xf5, + 0x85, 0xc6, 0x6b, 0xba, 0x59, 0xc1, 0xf2, 0xc6, 0x7f, 0x8c, 0x4a, 0x57, + 0xe5, 0x29, 0xa5, 0x0d, 0x60, 0x1a, 0x0e, 0xda, 0xd1, 0xac, 0xcc, 0x21, + 0x20, 0x5c, 0xa0, 0x62, 0xf6, 0xc6, 0x4a, 0x92, 0xb2, 0x35, 0x9f, 0x62, + 0x51, 0x4d, 0xcb, 0xd0, 0x35, 0x4e, 0xb2, 0xa3, 0x1b, 0xec, 0xd6, 0x18, + 0xb4, 0x67, 0xb9, 0xf8, 0x5c, 0x80, 0xfc, 0x20, 0x05, 0x85, 0x8a, 0x5a, + 0x35, 0x9a, 0xde, 0x2c, 0xd9, 0xde, 0x21, 0xfe, 0x9f, 0x92, 0x9f, 0xcb, + 0xb8, 0xea, 0x56, 0xf9, 0xb7, 0x4f, 0x61, 0xf9, 0x20, 0x09, 0xfe, 0x78, + 0x4b, 0x92, 0x90, 0x7a, 0xf9, 0xd0, 0x28, 0x95, 0x34, 0xc6, 0x5a, 0x9a, + 0x2a, 0x2a, 0xb8, 0xab, 0x6a, 0x1a, 0xc1, 0xd7, 0x7d, 0x5c, 0xde, 0xd1, + 0xaf, 0xe2, 0x20, 0x8d, 0x62, 0x56, 0x2c, 0x71, 0x78, 0x5b, 0x29, 0x20, + 0x4b, 0xf0, 0xe9, 0xa4, 0xe2, 0x3f, 0xab, 0xa2, 0x77, 0xac, 0xdf, 0x6e, + 0x2e, 0xc3, 0xa1, 0x4f, 0xe0, 0x30, 0xa7, 0xb7, 0x3a, 0x05, 0x13, 0x43, + 0xc1, 0x64, 0xdd, 0xff, 0x96, 0x65, 0x4c, 0x40, 0x62, 0x4a, 0xff, 0xa3, + 0xf0, 0x81, 0x26, 0x5d, 0x5f, 0x55, 0x73, 0xdb, 0x7d, 0xf8, 0x1f, 0x9c, + 0x0a, 0x64, 0x93, 0x74, 0xf3, 0xeb, 0x3d, 0x6f, 0x68, 0xec, 0x85, 0x5a, + 0xaa, 0x91, 0xb8, 0x5a, 0x36, 0x64, 0x89, 0x66, 0xb1, 0x53, 0xc5, 0xb8, + 0x5d, 0x33, 0xf7, 0x60, 0xc2, 0x89, 0x36, 0xef, 0x0d, 0xc5, 0x58, 0x08, + 0x75, 0x40, 0xae, 0x04, 0x87, 0x74, 0x1f, 0x11, 0x65, 0x1c, 0x84, 0xb6, + 0x60, 0xa0, 0xae, 0xe2, 0x2e, 0x70, 0xbe, 0x6a, 0x5d, 0x76, 0x60, 0xaa, + 0x41, 0xc5, 0x35, 0x09, 0xd3, 0x25, 0x5e, 0xd4, 0x7f, 0x22, 0x2b, 0xd7, + 0x09, 0x38, 0xae, 0x59, 0xde, 0x55, 0x88, 0x52, 0xae, 0x30, 0xfc, 0xb8, + 0x61, 0xdd, 0x7e, 0xc7, 0x1b, 0x37, 0xd5, 0x83, 0x28, 0x2a, 0x6e, 0x38, + 0x01, 0xb5, 0xd4, 0x3f, 0x34, 0xb6, 0x37, 0xd5, 0xbf, 0x59, 0x6e, 0xb7, + 0x16, 0x07, 0x96, 0x76, 0xe7, 0x84, 0x1b, 0x24, 0x59, 0x0b, 0x0a, 0x5c, + 0x5b, 0xef, 0xae, 0xc7, 0x7d, 0x18, 0x7e, 0x7c, 0x1a, 0xd5, 0x24, 0x2e, + 0xe9, 0x7f, 0x92, 0x3f, 0x4d, 0xd2, 0x0e, 0x44, 0xd1, 0x60, 0x73, 0xef, + 0x9b, 0xb6, 0x43, 0x87, 0xdd, 0x43, 0x1c, 0xa2, 0x67, 0x3e, 0x80, 0x5f, + 0x50, 0x6d, 0x5c, 0xb6, 0x90, 0xd5, 0x14, 0xce, 0xad, 0xbc, 0x2e, 0x39, + 0x62, 0x96, 0xc3, 0x25, 0xec, 0xa4, 0xd8, 0xf2 +}; + +typedef struct { const uint8_t *val; size_t len; } rsa_tc_bn_t; +typedef struct { size_t size; rsa_tc_bn_t n, e, d, p, q, dP, dQ, u, m, s; } rsa_tc_t; + +static const rsa_tc_t rsa_tc[] = { + { 1024, + { n_1024, sizeof(n_1024) }, + { e_1024, sizeof(e_1024) }, + { d_1024, sizeof(d_1024) }, + { p_1024, sizeof(p_1024) }, + { q_1024, sizeof(q_1024) }, + { dP_1024, sizeof(dP_1024) }, + { dQ_1024, sizeof(dQ_1024) }, + { u_1024, sizeof(u_1024) }, + { m_1024, sizeof(m_1024) }, + { s_1024, sizeof(s_1024) } + }, + { 2048, + { n_2048, sizeof(n_2048) }, + { e_2048, sizeof(e_2048) }, + { d_2048, sizeof(d_2048) }, + { p_2048, sizeof(p_2048) }, + { q_2048, sizeof(q_2048) }, + { dP_2048, sizeof(dP_2048) }, + { dQ_2048, sizeof(dQ_2048) }, + { u_2048, sizeof(u_2048) }, + { m_2048, sizeof(m_2048) }, + { s_2048, sizeof(s_2048) } + }, + { 4096, + { n_4096, sizeof(n_4096) }, + { e_4096, sizeof(e_4096) }, + { d_4096, sizeof(d_4096) }, + { p_4096, sizeof(p_4096) }, + { q_4096, sizeof(q_4096) }, + { dP_4096, sizeof(dP_4096) }, + { dQ_4096, sizeof(dQ_4096) }, + { u_4096, sizeof(u_4096) }, + { m_4096, sizeof(m_4096) }, + { s_4096, sizeof(s_4096) } + } +}; |