diff options
| author | Paul Selkirk <paul@psgd.org> | 2015-03-31 16:36:44 -0400 |
|---|---|---|
| committer | Paul Selkirk <paul@psgd.org> | 2015-03-31 16:36:44 -0400 |
| commit | 3252102d1c9c0e1fffce61391dab4d37f231655c (patch) | |
| tree | 4acb6b55a46fab448c0d9ed1f4ad1270e11fb326 | |
| parent | c61362a96ef83600d2711f794549ab30540615fc (diff) | |
Refactor common code into tc_[eim|i2c].[ch], add general-purpose hash utilities, add trng_tester_i2c.
| -rwxr-xr-x | eim/sw/Makefile | 19 | ||||
| -rw-r--r-- | eim/sw/hash_eim.c | 402 | ||||
| -rw-r--r-- | eim/sw/hash_tester_eim.c | 155 | ||||
| -rw-r--r-- | eim/sw/tc_eim.c | 137 | ||||
| -rw-r--r-- | eim/sw/tc_eim.h | 42 | ||||
| -rw-r--r-- | eim/sw/trng_tester_eim.c | 159 | ||||
| -rwxr-xr-x | i2c/sw/Makefile | 25 | ||||
| -rw-r--r-- | i2c/sw/hash_i2c.c | 409 | ||||
| -rw-r--r-- | i2c/sw/hash_tester_i2c.c | 1353 | ||||
| -rw-r--r-- | i2c/sw/tc_i2c.c | 297 | ||||
| -rw-r--r-- | i2c/sw/tc_i2c.h | 47 | ||||
| -rw-r--r-- | i2c/sw/trng_tester_i2c.c | 421 |
12 files changed, 2377 insertions, 1089 deletions
diff --git a/eim/sw/Makefile b/eim/sw/Makefile index 87cd78f..8e584fa 100755 --- a/eim/sw/Makefile +++ b/eim/sw/Makefile @@ -1,19 +1,26 @@ -all: hash_tester_eim trng_tester_eim +all: hash_tester_eim trng_tester_eim hash_eim .c.o: gcc -c -Wall -o $@ $< -hash_tester_eim: hash_tester_eim.o novena-eim.o +hash_tester_eim: hash_tester_eim.o novena-eim.o tc_eim.o gcc -o $@ $^ -hash_tester_eim.o: hash_tester_eim.c novena-eim.h +hash_tester_eim.o: hash_tester_eim.c tc_eim.h -trng_tester_eim: trng_tester_eim.o novena-eim.o +trng_tester_eim: trng_tester_eim.o novena-eim.o tc_eim.o gcc -o $@ $^ -trng_tester_eim.o: trng_tester_eim.c novena-eim.h +trng_tester_eim.o: trng_tester_eim.c tc_eim.h + +hash_eim: hash_eim.o novena-eim.o tc_eim.o + gcc -o $@ $^ + +hash_eim.o: hash_eim.c tc_eim.h novena-eim.o: novena-eim.c novena-eim.h +tc_eim.o: tc_eim.c tc_eim.h novena-eim.h + clean: - rm -f *.o hash_tester_eim trng_tester_eim + rm -f *.o hash_tester_eim trng_tester_eim hash_eim diff --git a/eim/sw/hash_eim.c b/eim/sw/hash_eim.c new file mode 100644 index 0000000..281914c --- /dev/null +++ b/eim/sw/hash_eim.c @@ -0,0 +1,402 @@ +/* + * hash.c + * ------ + * This program uses the coretest_hashes subsystem to produce a + * cryptographic hash of a file or input stream. It is a generalization + * of the hash_tester.c test program. + * + * Authors: Joachim Strömbergson, Paul Selkirk + * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of the NORDUnet nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <string.h> +#include <stdio.h> +#include <stdlib.h> +#include <errno.h> +#include <sys/mman.h> +#include <fcntl.h> +#include <unistd.h> +#include <time.h> +#include <sys/time.h> +#include <linux/i2c-dev.h> +#include <sys/ioctl.h> +#include <arpa/inet.h> +#include <ctype.h> +#include <assert.h> + +#include "tc_eim.h" + +char *usage = +"Usage: %s [-d] [-v] [-q] [algorithm [file]]\n" +"algorithms: sha-1, sha-256, sha-512/224, sha-512/256, sha-384, sha-512\n"; + +int debug = 0; +int quiet = 0; +int verbose = 0; + +/* memory segments for core families */ +#define SEGMENT_OFFSET_GLOBALS EIM_BASE_ADDR + 0x000000 +#define SEGMENT_OFFSET_HASHES EIM_BASE_ADDR + 0x010000 +#define SEGMENT_OFFSET_RNGS EIM_BASE_ADDR + 0x020000 +#define SEGMENT_OFFSET_CIPHERS EIM_BASE_ADDR + 0x030000 + +#define CORE_SIZE (0x100 << 2) + +/* addresses and codes common to all cores */ +#define ADDR_NAME0 (0x0 << 2) +#define ADDR_NAME1 (0x1 << 2) +#define ADDR_VERSION (0x2 << 2) + +/* At segment 0, we have board-level register and communication channel registers */ +#define BOARD_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0x00 * CORE_SIZE) +#define BOARD_ADDR_NAME0 BOARD_ADDR_BASE + ADDR_NAME0 +#define BOARD_ADDR_NAME1 BOARD_ADDR_BASE + ADDR_NAME1 +#define BOARD_ADDR_VERSION BOARD_ADDR_BASE + ADDR_VERSION +#define BOARD_ADDR_DUMMY BOARD_ADDR_BASE + (0xFF << 2) + +#define COMM_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0x01 * CORE_SIZE) +#define COMM_ADDR_NAME0 COMM_ADDR_BASE + ADDR_NAME0 +#define COMM_ADDR_NAME1 COMM_ADDR_BASE + ADDR_NAME1 +#define COMM_ADDR_VERSION COMM_ADDR_BASE + ADDR_VERSION + +/* addresses and codes common to all hash cores */ +#define ADDR_CTRL (0x8 << 2) +#define CTRL_INIT_CMD 1 +#define CTRL_NEXT_CMD 2 +#define ADDR_STATUS (9 << 2) +#define STATUS_READY_BIT 1 +#define STATUS_VALID_BIT 2 +#define ADDR_BLOCK (0x10 << 2) +#define ADDR_DIGEST (0x20 << 2) + +/* addresses and codes for the specific hash cores */ +#define SHA1_ADDR_BASE SEGMENT_OFFSET_HASHES + (0*CORE_SIZE) +#define SHA1_ADDR_NAME0 SHA1_ADDR_BASE + ADDR_NAME0 +#define SHA1_ADDR_NAME1 SHA1_ADDR_BASE + ADDR_NAME1 +#define SHA1_ADDR_VERSION SHA1_ADDR_BASE + ADDR_VERSION +#define SHA1_ADDR_CTRL SHA1_ADDR_BASE + ADDR_CTRL +#define SHA1_ADDR_STATUS SHA1_ADDR_BASE + ADDR_STATUS +#define SHA1_ADDR_BLOCK SHA1_ADDR_BASE + ADDR_BLOCK +#define SHA1_ADDR_DIGEST SHA1_ADDR_BASE + ADDR_DIGEST +#define SHA1_BLOCK_LEN 512 / 8 +#define SHA1_DIGEST_LEN 160 / 8 + +#define SHA256_ADDR_BASE SEGMENT_OFFSET_HASHES + (1*CORE_SIZE) +#define SHA256_ADDR_NAME0 SHA256_ADDR_BASE + ADDR_NAME0 +#define SHA256_ADDR_NAME1 SHA256_ADDR_BASE + ADDR_NAME1 +#define SHA256_ADDR_VERSION SHA256_ADDR_BASE + ADDR_VERSION +#define SHA256_ADDR_CTRL SHA256_ADDR_BASE + ADDR_CTRL +#define SHA256_ADDR_STATUS SHA256_ADDR_BASE + ADDR_STATUS +#define SHA256_ADDR_BLOCK SHA256_ADDR_BASE + ADDR_BLOCK +#define SHA256_ADDR_DIGEST SHA256_ADDR_BASE + ADDR_DIGEST +#define SHA256_BLOCK_LEN 512 / 8 +#define SHA256_DIGEST_LEN 256 / 8 + +#define SHA512_ADDR_BASE SEGMENT_OFFSET_HASHES + (2*CORE_SIZE) +#define SHA512_ADDR_NAME0 SHA512_ADDR_BASE + ADDR_NAME0 +#define SHA512_ADDR_NAME1 SHA512_ADDR_BASE + ADDR_NAME1 +#define SHA512_ADDR_VERSION SHA512_ADDR_BASE + ADDR_VERSION +#define SHA512_ADDR_CTRL SHA512_ADDR_BASE + ADDR_CTRL +#define SHA512_ADDR_STATUS SHA512_ADDR_BASE + ADDR_STATUS +#define SHA512_ADDR_BLOCK SHA512_ADDR_BASE + ADDR_BLOCK +#define SHA512_ADDR_DIGEST SHA512_ADDR_BASE + (0x40 << 2) +#define SHA512_BLOCK_LEN 1024 / 8 +#define SHA512_224_DIGEST_LEN 224 / 8 +#define SHA512_256_DIGEST_LEN 256 / 8 +#define SHA384_DIGEST_LEN 384 / 8 +#define SHA512_DIGEST_LEN 512 / 8 +#define MODE_SHA_512_224 0 << 2 +#define MODE_SHA_512_256 1 << 2 +#define MODE_SHA_384 2 << 2 +#define MODE_SHA_512 3 << 2 + +/* ---------------- algorithm lookup code ---------------- */ + +struct ctrl { + char *name; + off_t block_addr; + int block_len; + off_t digest_addr; + int digest_len; + int mode; +} ctrl[] = { + { "sha-1", SHA1_ADDR_BLOCK, SHA1_BLOCK_LEN, + SHA1_ADDR_DIGEST, SHA1_DIGEST_LEN, 0 }, + { "sha-256", SHA256_ADDR_BLOCK, SHA256_BLOCK_LEN, + SHA256_ADDR_DIGEST, SHA256_DIGEST_LEN, 0 }, + { "sha-512/224", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, + SHA512_ADDR_DIGEST, SHA512_224_DIGEST_LEN, MODE_SHA_512_224 }, + { "sha-512/256", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, + SHA512_ADDR_DIGEST, SHA512_256_DIGEST_LEN, MODE_SHA_512_256 }, + { "sha-384", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, + SHA512_ADDR_DIGEST, SHA384_DIGEST_LEN, MODE_SHA_384 }, + { "sha-512", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, + SHA512_ADDR_DIGEST, SHA512_DIGEST_LEN, MODE_SHA_512 }, + { NULL, 0, 0, 0 } +}; + +/* return the control structure for the given algorithm */ +struct ctrl *find_algo(char *algo) +{ + int i; + + for (i = 0; ctrl[i].name != NULL; ++i) + if (strcmp(ctrl[i].name, algo) == 0) + return &ctrl[i]; + + fprintf(stderr, "algorithm \"%s\" not found\n\n", algo); + fprintf(stderr, usage, "hash"); + return NULL; +} + +/* ---------------- test-case low-level code ---------------- */ + +int tc_init(off_t offset, int mode) +{ + uint8_t buf[4] = { 0, 0, 0, CTRL_INIT_CMD + mode }; + + return tc_write(offset, buf, 4); +} + +int tc_next(off_t offset, int mode) +{ + uint8_t buf[4] = { 0, 0, 0, CTRL_NEXT_CMD + mode }; + + return tc_write(offset, buf, 4); +} + +int tc_wait_ready(off_t offset) +{ + return tc_wait(offset, STATUS_READY_BIT, NULL); +} + +int tc_wait_valid(off_t offset) +{ + return tc_wait(offset, STATUS_VALID_BIT, NULL); +} + +/* ---------------- hash ---------------- */ + +int transmit(off_t offset, uint8_t *block, int blen, int mode, int first) +{ + off_t base = offset & ~(0xff); + + if (tc_write(offset, block, blen) != 0) + return 1; + + if (first) { + if (tc_init(base + ADDR_CTRL, mode) != 0) + return 1; + } + else { + if (tc_next(base + ADDR_CTRL, mode) != 0) + return 1; + } + + return tc_wait_ready(base + ADDR_STATUS); +} + +int pad_transmit(off_t offset, uint8_t *block, uint8_t flen, uint8_t blen, + uint8_t mode, long long tlen, int first) +{ + assert(flen < blen); + + block[flen++] = 0x80; + memset(block + flen, 0, blen - flen); + + if (blen - flen < ((blen == 64) ? 8 : 16)) { + if (transmit(offset, block, blen, mode, first) != 0) + return 1; + first = 0; + memset(block, 0, blen); + } + + /* properly the length is 128 bits for sha-512, but we can't + * actually count above 64 bits + */ + ((uint32_t *)block)[blen/4 - 2] = htonl((tlen >> 32) & 0xffff); + ((uint32_t *)block)[blen/4 - 1] = htonl(tlen & 0xffff); + + return transmit(offset, block, blen, mode, first); +} + +/* return number of digest bytes read */ +int hash(char *algo, char *file, uint8_t *digest) +{ + uint8_t block[SHA512_BLOCK_LEN]; + struct ctrl *ctrl; + int in_fd = 0; /* stdin */ + off_t baddr, daddr; + int blen, dlen, mode; + int nblk, nread, first; + int ret = -1; + struct timeval start, stop, difftime; + + ctrl = find_algo(algo); + if (ctrl == NULL) + return -1; + baddr = ctrl->block_addr; + blen = ctrl->block_len; + daddr = ctrl->digest_addr; + dlen = ctrl->digest_len; + mode = ctrl->mode; + + if (strcmp(file, "-") != 0) { + in_fd = open(file, O_RDONLY); + if (in_fd < 0) { + perror("open"); + return -1; + } + } + + if (verbose) { + if (gettimeofday(&start, NULL) < 0) { + perror("gettimeofday"); + goto out; + } + } + + for (nblk = 0, first = 1; ; ++nblk, first = 0) { + nread = read(in_fd, block, blen); + if (nread < 0) { + /* read error */ + perror("read"); + goto out; + } + else if (nread < blen) { + /* partial read = last block */ + if (pad_transmit(baddr, block, nread, blen, mode, + (nblk * blen + nread) * 8, first) != 0) + goto out; + break; + } + else { + /* full block read */ + if (transmit(baddr, block, blen, mode, first) != 0) + goto out; + } + } + + /* Strictly speaking we should query "valid" status before reading digest, + * but transmit() waits for "ready" status before returning, and the SHA + * cores always assert valid before ready. + */ + if (tc_read(daddr, digest, dlen) != 0) { + perror("i2c read failed"); + goto out; + } + + if (verbose) { + if (gettimeofday(&stop, NULL) < 0) { + perror("gettimeofday"); + goto out; + } + timersub(&stop, &start, &difftime); + printf("%d blocks written in %d.%03d sec (%.3f blocks/sec)\n", + nblk, (int)difftime.tv_sec, (int)difftime.tv_usec/1000, + (float)nblk / ((float)difftime.tv_sec + ((float)difftime.tv_usec)/1000000)); + } + + ret = dlen; +out: + if (in_fd != 0) + close(in_fd); + return ret; +} + +/* ---------------- main ---------------- */ + +int main(int argc, char *argv[]) +{ + int i, opt; + char *algo = "sha-1"; + char *file = "-"; + uint8_t digest[512/8]; + int dlen; + + while ((opt = getopt(argc, argv, "h?dvq")) != -1) { + switch (opt) { + case 'h': + case '?': + printf(usage, argv[0]); + return EXIT_SUCCESS; + case 'd': + debug = 1; + break; + case 'v': + verbose = 1; + break; + case 'q': + quiet = 1; + break; + default: + fprintf(stderr, usage, argv[0]); + return EXIT_FAILURE; + } + } + + if (optind < argc) { + algo = argv[optind]; + ++optind; + } + else { + if (!quiet) + printf("defaulting to algorithm \"%s\"\n", algo); + } + + if (optind < argc) { + file = argv[optind]; + ++optind; + } + else { + if (!quiet) + printf("reading from stdin\n"); + } + + if (eim_setup() != 0) { + fprintf(stderr, "EIM setup failed\n"); + return EXIT_FAILURE; + } + + dlen = hash(algo, file, digest); + if (dlen < 0) + return EXIT_FAILURE; + + for (i = 0; i < dlen; ++i) { + printf("%02x", digest[i]); + if (i % 16 == 15) + printf("\n"); + else if (i % 4 == 3) + printf(" "); + } + if (dlen % 16 != 0) + printf("\n"); + + return EXIT_SUCCESS; +} diff --git a/eim/sw/hash_tester_eim.c b/eim/sw/hash_tester_eim.c index 74685ee..e0bcc03 100644 --- a/eim/sw/hash_tester_eim.c +++ b/eim/sw/hash_tester_eim.c @@ -45,41 +45,40 @@ #include <string.h> #include <stdio.h> #include <stdlib.h> -#include <errno.h> -#include <sys/mman.h> -#include <fcntl.h> #include <unistd.h> #include <time.h> #include <sys/time.h> -#include <sys/ioctl.h> -#include <arpa/inet.h> +#include <stdint.h> #include <ctype.h> #include <signal.h> -#include "novena-eim.h" +#include "tc_eim.h" int debug = 0; int quiet = 0; int repeat = 0; +/* memory segments for core families */ #define SEGMENT_OFFSET_GLOBALS EIM_BASE_ADDR + 0x000000 #define SEGMENT_OFFSET_HASHES EIM_BASE_ADDR + 0x010000 #define SEGMENT_OFFSET_RNGS EIM_BASE_ADDR + 0x020000 #define SEGMENT_OFFSET_CIPHERS EIM_BASE_ADDR + 0x030000 +#define CORE_SIZE (0x100 << 2) + /* addresses and codes common to all cores */ #define ADDR_NAME0 (0x0 << 2) #define ADDR_NAME1 (0x1 << 2) #define ADDR_VERSION (0x2 << 2) /* At segment 0, we have board-level register and communication channel registers */ -#define BOARD_ADDR_BASE SEGMENT_OFFSET_GLOBALS + 0x0000 +#define BOARD_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0x00 * CORE_SIZE) #define BOARD_ADDR_NAME0 BOARD_ADDR_BASE + ADDR_NAME0 #define BOARD_ADDR_NAME1 BOARD_ADDR_BASE + ADDR_NAME1 #define BOARD_ADDR_VERSION BOARD_ADDR_BASE + ADDR_VERSION #define BOARD_ADDR_DUMMY BOARD_ADDR_BASE + (0xFF << 2) -#define COMM_ADDR_BASE SEGMENT_OFFSET_GLOBALS + 0x0400 +#define COMM_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0x01 * CORE_SIZE) #define COMM_ADDR_NAME0 COMM_ADDR_BASE + ADDR_NAME0 #define COMM_ADDR_NAME1 COMM_ADDR_BASE + ADDR_NAME1 #define COMM_ADDR_VERSION COMM_ADDR_BASE + ADDR_VERSION @@ -94,10 +93,8 @@ int repeat = 0; #define ADDR_BLOCK (0x10 << 2) #define ADDR_DIGEST (0x20 << 2) -#define HASH_CORE_SIZE (0x100 << 2) - /* addresses and codes for the specific hash cores */ -#define SHA1_ADDR_BASE SEGMENT_OFFSET_HASHES + (0*HASH_CORE_SIZE) +#define SHA1_ADDR_BASE SEGMENT_OFFSET_HASHES + (0*CORE_SIZE) #define SHA1_ADDR_NAME0 SHA1_ADDR_BASE + ADDR_NAME0 #define SHA1_ADDR_NAME1 SHA1_ADDR_BASE + ADDR_NAME1 #define SHA1_ADDR_VERSION SHA1_ADDR_BASE + ADDR_VERSION @@ -108,7 +105,7 @@ int repeat = 0; #define SHA1_BLOCK_LEN 512 / 8 #define SHA1_DIGEST_LEN 160 / 8 -#define SHA256_ADDR_BASE SEGMENT_OFFSET_HASHES + (1*HASH_CORE_SIZE) +#define SHA256_ADDR_BASE SEGMENT_OFFSET_HASHES + (1*CORE_SIZE) #define SHA256_ADDR_NAME0 SHA256_ADDR_BASE + ADDR_NAME0 #define SHA256_ADDR_NAME1 SHA256_ADDR_BASE + ADDR_NAME1 #define SHA256_ADDR_VERSION SHA256_ADDR_BASE + ADDR_VERSION @@ -119,14 +116,14 @@ int repeat = 0; #define SHA256_BLOCK_LEN 512 / 8 #define SHA256_DIGEST_LEN 256 / 8 -#define SHA512_ADDR_BASE SEGMENT_OFFSET_HASHES + (2*HASH_CORE_SIZE) +#define SHA512_ADDR_BASE SEGMENT_OFFSET_HASHES + (2*CORE_SIZE) #define SHA512_ADDR_NAME0 SHA512_ADDR_BASE + ADDR_NAME0 #define SHA512_ADDR_NAME1 SHA512_ADDR_BASE + ADDR_NAME1 #define SHA512_ADDR_VERSION SHA512_ADDR_BASE + ADDR_VERSION #define SHA512_ADDR_CTRL SHA512_ADDR_BASE + ADDR_CTRL #define SHA512_ADDR_STATUS SHA512_ADDR_BASE + ADDR_STATUS #define SHA512_ADDR_BLOCK SHA512_ADDR_BASE + ADDR_BLOCK -#define SHA512_ADDR_DIGEST SHA512_ADDR_BASE + 0x100 +#define SHA512_ADDR_DIGEST SHA512_ADDR_BASE + (0x40 << 2) #define SHA512_BLOCK_LEN 1024 / 8 #define SHA512_224_DIGEST_LEN 224 / 8 #define SHA512_256_DIGEST_LEN 256 / 8 @@ -306,75 +303,6 @@ const uint8_t SHA512_DOUBLE_DIGEST[] = /* ---------------- test-case low-level code ---------------- */ -void dump(char *label, const uint8_t *buf, int len) -{ - if (debug) { - int i; - printf("%s [", label); - for (i = 0; i < len; ++i) - printf(" %02x", buf[i]); - printf(" ]\n"); - } -} - -int tc_write(off_t offset, const uint8_t *buf, int len) -{ - dump("write ", buf, len); - - for (; len > 0; offset += 4, buf += 4, len -= 4) { - uint32_t val; - val = htonl(*(uint32_t *)buf); - eim_write_32(offset, &val); - } - - return 0; -} - -int tc_read(off_t offset, uint8_t *buf, int len) -{ - uint8_t *rbuf = buf; - int rlen = len; - - for (; rlen > 0; offset += 4, rbuf += 4, rlen -= 4) { - uint32_t val; - eim_read_32(offset, &val); - *(uint32_t *)rbuf = ntohl(val); - } - - dump("read ", buf, len); - - return 0; -} - -int tc_expected(off_t offset, const uint8_t *expected, int len) -{ - uint8_t *buf; - int i; - - buf = malloc(len); - if (buf == NULL) { - perror("malloc"); - return 1; - } - dump("expect", expected, len); - - if (tc_read(offset, buf, len) != 0) - goto errout; - - for (i = 0; i < len; ++i) - if (buf[i] != expected[i]) { - fprintf(stderr, "response byte %d: expected 0x%02x, got 0x%02x\n", - i, expected[i], buf[i]); - goto errout; - } - - free(buf); - return 0; -errout: - free(buf); - return 1; -} - int tc_init(off_t offset) { uint8_t buf[4] = { 0, 0, 0, CTRL_INIT_CMD }; @@ -389,51 +317,27 @@ int tc_next(off_t offset) return tc_write(offset, buf, 4); } -int tc_wait(off_t offset, uint8_t status) -{ - uint8_t buf[4]; - -#if 0 - do { - if (tc_read(offset, buf, 4) != 0) - return 1; - } while (!(buf[3] & status)); - - return 0; -#else - int i; - for (i = 0; i < 10; ++i) { - if (tc_read(offset, buf, 4) != 0) - return 1; - if (buf[3] & status) - return 0; - } - fprintf(stderr, "tc_wait timed out\n"); - return 1; -#endif -} - int tc_wait_ready(off_t offset) { - return tc_wait(offset, STATUS_READY_BIT); + return tc_wait(offset, STATUS_READY_BIT, NULL); } int tc_wait_valid(off_t offset) { - return tc_wait(offset, STATUS_VALID_BIT); + return tc_wait(offset, STATUS_VALID_BIT, NULL); } /* ---------------- sanity test case ---------------- */ int TC0() { - uint8_t board_name0[4] = { 'P', 'V', 'T', '1'}; - uint8_t board_name1[4] = { ' ', ' ', ' ', ' '}; - uint8_t board_version[4] = { '0', '.', '1', '0'}; + uint8_t board_name0[4] = "PVT1"; + uint8_t board_name1[4] = " "; + uint8_t board_version[4] = "0.10"; - uint8_t comm_name0[4] = { 'e', 'i', 'm', ' '}; - uint8_t comm_name1[4] = { ' ', ' ', ' ', ' '}; - uint8_t comm_version[4] = { '0', '.', '1', '0'}; + uint8_t comm_name0[4] = "eim "; + uint8_t comm_name1[4] = " "; + uint8_t comm_version[4] = "0.10"; uint8_t t[4]; @@ -444,7 +348,8 @@ int TC0() * to make sure that we can actually write something into EIM */ (void)time((time_t *)t); - tc_write(BOARD_ADDR_DUMMY, (void *)&t, 4); + if (tc_write(BOARD_ADDR_DUMMY, (void *)&t, 4) != 0) + return 1; if (tc_expected(BOARD_ADDR_NAME0, board_name0, 4) || tc_expected(BOARD_ADDR_NAME1, board_name1, 4) || @@ -466,9 +371,9 @@ int TC0() /* TC1: Read name and version from SHA-1 core. */ int TC1(void) { - uint8_t name0[4] = { 0x73, 0x68, 0x61, 0x31 }; /* "sha1" */ - uint8_t name1[4] = { 0x20, 0x20, 0x20, 0x20 }; /* " " */ - uint8_t version[4] = { 0x30, 0x2e, 0x35, 0x30 }; /* "0.50" */ + uint8_t name0[4] = "sha1"; + uint8_t name1[4] = " "; + uint8_t version[4] = "0.50"; if (!quiet) printf("TC1: Reading name and version words from SHA-1 core.\n"); @@ -535,9 +440,9 @@ int TC3(void) /* TC4: Read name and version from SHA-256 core. */ int TC4(void) { - uint8_t name0[4] = { 0x73, 0x68, 0x61, 0x32 }; /* "sha2" */ - uint8_t name1[4] = { 0x2d, 0x32, 0x35, 0x36 }; /* "-256" */ - uint8_t version[4] = { 0x30, 0x2e, 0x38, 0x30 }; /* "0.80" */ + uint8_t name0[4] = "sha2"; + uint8_t name1[4] = "-256"; + uint8_t version[4] = "0.80"; if (!quiet) printf("TC4: Reading name, type and version words from SHA-256 core.\n"); @@ -652,9 +557,9 @@ int TC7() /* TC8: Read name and version from SHA-512 core. */ int TC8() { - uint8_t name0[4] = { 0x73, 0x68, 0x61, 0x32 }; /* "sha2" */ - uint8_t name1[4] = { 0x2d, 0x35, 0x31, 0x32 }; /* "-512" */ - uint8_t version[4] = { 0x30, 0x2e, 0x38, 0x30 }; /* "0.80" */ + uint8_t name0[4] = "sha2"; + uint8_t name1[4] = "-512"; + uint8_t version[4] = "0.80"; if (!quiet) printf("TC8: Reading name, type and version words from SHA-512 core.\n"); diff --git a/eim/sw/tc_eim.c b/eim/sw/tc_eim.c new file mode 100644 index 0000000..0d8c83c --- /dev/null +++ b/eim/sw/tc_eim.c @@ -0,0 +1,137 @@ +/* + * tc_eim.c + * -------- + * This module contains common code to talk to the FPGA over the EIM bus. + * + * Author: Paul Selkirk + * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of the NORDUnet nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <stdio.h> +#include <stdlib.h> +#include <fcntl.h> +#include <unistd.h> +#include <sys/ioctl.h> +#include <stdint.h> +#include <arpa/inet.h> + +#include "tc_eim.h" + +extern int debug; + +/* ---------------- test-case low-level code ---------------- */ + +static void dump(char *label, const uint8_t *buf, int len) +{ + if (debug) { + int i; + printf("%s [", label); + for (i = 0; i < len; ++i) + printf(" %02x", buf[i]); + printf(" ]\n"); + } +} + +int tc_write(off_t offset, const uint8_t *buf, int len) +{ + dump("write ", buf, len); + + for (; len > 0; offset += 4, buf += 4, len -= 4) { + uint32_t val; + val = htonl(*(uint32_t *)buf); + eim_write_32(offset, &val); + } + + return 0; +} + +int tc_read(off_t offset, uint8_t *buf, int len) +{ + uint8_t *rbuf = buf; + int rlen = len; + + for (; rlen > 0; offset += 4, rbuf += 4, rlen -= 4) { + uint32_t val; + eim_read_32(offset, &val); + *(uint32_t *)rbuf = ntohl(val); + } + + dump("read ", buf, len); + + return 0; +} + +int tc_expected(off_t offset, const uint8_t *expected, int len) +{ + uint8_t *buf; + int i; + + buf = malloc(len); + if (buf == NULL) { + perror("malloc"); + return 1; + } + dump("expect", expected, len); + + if (tc_read(offset, buf, len) != 0) + goto errout; + + for (i = 0; i < len; ++i) + if (buf[i] != expected[i]) { + fprintf(stderr, "response byte %d: expected 0x%02x, got 0x%02x\n", + i, expected[i], buf[i]); + goto errout; + } + + free(buf); + return 0; +errout: + free(buf); + return 1; +} + +int tc_wait(off_t offset, uint8_t status, int *count) +{ + uint8_t buf[4]; + int i; + + for (i = 1; ; ++i) { + if (count && (*count > 0) && (i >= *count)) { + fprintf(stderr, "tc_wait timed out\n"); + return 1; + } + if (tc_read(offset, buf, 4) != 0) + return -1; + if (buf[3] & status) { + if (count) + *count = i; + return 0; + } + } +} diff --git a/eim/sw/tc_eim.h b/eim/sw/tc_eim.h new file mode 100644 index 0000000..257822d --- /dev/null +++ b/eim/sw/tc_eim.h @@ -0,0 +1,42 @@ +/* + * tc_eim.h + * -------- + * This module contains common code to talk to the FPGA over the EIM bus. + * + * Author: Paul Selkirk + * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of the NORDUnet nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "novena-eim.h" + +/* test case public functions */ +int tc_write(off_t offset, const uint8_t *buf, int len); +int tc_read(off_t offset, uint8_t *buf, int len); +int tc_expected(off_t offset, const uint8_t *expected, int len); +int tc_wait(off_t offset, uint8_t status, int *count); diff --git a/eim/sw/trng_tester_eim.c b/eim/sw/trng_tester_eim.c index 7c452b0..eb30045 100644 --- a/eim/sw/trng_tester_eim.c +++ b/eim/sw/trng_tester_eim.c @@ -40,18 +40,14 @@ #include <string.h> #include <stdio.h> #include <stdlib.h> -#include <errno.h> -#include <sys/mman.h> -#include <fcntl.h> #include <unistd.h> #include <time.h> #include <sys/time.h> -#include <sys/ioctl.h> -#include <arpa/inet.h> +#include <stdint.h> #include <ctype.h> #include <signal.h> -#include "novena-eim.h" +#include "tc_eim.h" #define WAIT_STATS /* report number of status reads before core says "ready" */ @@ -60,32 +56,33 @@ int quiet = 0; int repeat = 0; int num_words = 10; +/* memory segments for core families */ #define SEGMENT_OFFSET_GLOBALS EIM_BASE_ADDR + 0x000000 #define SEGMENT_OFFSET_HASHES EIM_BASE_ADDR + 0x010000 #define SEGMENT_OFFSET_RNGS EIM_BASE_ADDR + 0x020000 #define SEGMENT_OFFSET_CIPHERS EIM_BASE_ADDR + 0x030000 +#define CORE_SIZE (0x100 << 2) + /* addresses and codes common to all cores */ #define ADDR_NAME0 (0x0 << 2) #define ADDR_NAME1 (0x1 << 2) #define ADDR_VERSION (0x2 << 2) /* At segment 0, we have board-level register and communication channel registers */ -#define BOARD_ADDR_BASE SEGMENT_OFFSET_GLOBALS + 0x0000 +#define BOARD_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0x00 * CORE_SIZE) #define BOARD_ADDR_NAME0 BOARD_ADDR_BASE + ADDR_NAME0 #define BOARD_ADDR_NAME1 BOARD_ADDR_BASE + ADDR_NAME1 #define BOARD_ADDR_VERSION BOARD_ADDR_BASE + ADDR_VERSION #define BOARD_ADDR_DUMMY BOARD_ADDR_BASE + (0xFF << 2) -#define COMM_ADDR_BASE SEGMENT_OFFSET_GLOBALS + 0x0400 +#define COMM_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0x01 * CORE_SIZE) #define COMM_ADDR_NAME0 COMM_ADDR_BASE + ADDR_NAME0 #define COMM_ADDR_NAME1 COMM_ADDR_BASE + ADDR_NAME1 #define COMM_ADDR_VERSION COMM_ADDR_BASE + ADDR_VERSION -#define CORE_SIZE (0x100 << 2) - /* addresses and codes for the TRNG cores */ -#define TRNG_ADDR_BASE SEGMENT_OFFSET_RNGS + (0 * CORE_SIZE) +#define TRNG_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x00 * CORE_SIZE) #define TRNG_ADDR_NAME0 TRNG_ADDR_BASE + ADDR_NAME0 #define TRNG_ADDR_NAME1 TRNG_ADDR_BASE + ADDR_NAME1 #define TRNG_ADDR_VERSION TRNG_ADDR_BASE + ADDR_VERSION @@ -96,7 +93,7 @@ int num_words = 10; /* no status bits defined */ #define TRNG_ADDR_DELAY TRNG_ADDR_BASE + (0x13 << 2) -#define ENTROPY1_ADDR_BASE SEGMENT_OFFSET_RNGS + (5 * CORE_SIZE) +#define ENTROPY1_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x05 * CORE_SIZE) #define ENTROPY1_ADDR_NAME0 ENTROPY1_ADDR_BASE + ADDR_NAME0 #define ENTROPY1_ADDR_NAME1 ENTROPY1_ADDR_BASE + ADDR_NAME1 #define ENTROPY1_ADDR_VERSION ENTROPY1_ADDR_BASE + ADDR_VERSION @@ -107,7 +104,7 @@ int num_words = 10; #define ENTROPY1_ADDR_ENTROPY ENTROPY1_ADDR_BASE + (0x20 << 2) #define ENTROPY1_ADDR_DELTA ENTROPY1_ADDR_BASE + (0x30 << 2) -#define ENTROPY2_ADDR_BASE SEGMENT_OFFSET_RNGS + (6 * CORE_SIZE) +#define ENTROPY2_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x06 * CORE_SIZE) #define ENTROPY2_ADDR_NAME0 ENTROPY2_ADDR_BASE + ADDR_NAME0 #define ENTROPY2_ADDR_NAME1 ENTROPY2_ADDR_BASE + ADDR_NAME1 #define ENTROPY2_ADDR_VERSION ENTROPY2_ADDR_BASE + ADDR_VERSION @@ -146,103 +143,6 @@ int num_words = 10; #define CSPRNG_ADDR_NBLOCKS_LO CSPRNG_ADDR_BASE + (0x41 << 2) #define CSPRNG_ADDR_NBLOCKS_HI CSPRNG_ADDR_BASE + (0x42 << 2) -/* ---------------- test-case low-level code ---------------- */ - -void dump(char *label, const uint8_t *buf, int len) -{ - if (debug) { - int i; - printf("%s [", label); - for (i = 0; i < len; ++i) - printf(" %02x", buf[i]); - printf(" ]\n"); - } -} - -int tc_write(off_t offset, const uint8_t *buf, int len) -{ - dump("write ", buf, len); - - for (; len > 0; offset += 4, buf += 4, len -= 4) { - uint32_t val; - val = htonl(*(uint32_t *)buf); - eim_write_32(offset, &val); - } - - return 0; -} - -int tc_read(off_t offset, uint8_t *buf, int len) -{ - uint8_t *rbuf = buf; - int rlen = len; - - for (; rlen > 0; offset += 4, rbuf += 4, rlen -= 4) { - uint32_t val; - eim_read_32(offset, &val); - *(uint32_t *)rbuf = ntohl(val); - } - - dump("read ", buf, len); - - return 0; -} - -int tc_expected(off_t offset, const uint8_t *expected, int len) -{ - uint8_t *buf; - int i; - - buf = malloc(len); - if (buf == NULL) { - perror("malloc"); - return 1; - } - dump("expect", expected, len); - - if (tc_read(offset, buf, len) != 0) - goto errout; - - for (i = 0; i < len; ++i) - if (buf[i] != expected[i]) { - fprintf(stderr, "response byte %d: expected 0x%02x, got 0x%02x\n", - i, expected[i], buf[i]); - goto errout; - } - - free(buf); - return 0; -errout: - free(buf); - return 1; -} - -#ifdef WAIT_STATS -int tc_wait(off_t offset, uint8_t status) -{ - uint8_t buf[4]; - int i; - - for (i = 1; ; ++i) { - if (tc_read(offset, buf, 4) != 0) - return -1; - if (buf[3] & status) - return i; - } -} -#else -int tc_wait(off_t offset, uint8_t status) -{ - uint8_t buf[4]; - do { - if (tc_read(offset, buf, 4) != 0) - return 1; - } while (!(buf[3] & status)); - - return 0; -} -#endif - /* ---------------- sanity test case ---------------- */ int TC0() @@ -264,7 +164,8 @@ int TC0() * to make sure that we can actually write something into EIM */ (void)time((time_t *)t); - tc_write(BOARD_ADDR_DUMMY, (void *)&t, 4); + if (tc_write(BOARD_ADDR_DUMMY, (void *)&t, 4) != 0) + return 1; if (tc_expected(BOARD_ADDR_NAME0, board_name0, 4) || tc_expected(BOARD_ADDR_NAME1, board_name1, 4) || @@ -325,10 +226,7 @@ int TC2(void) /* TC3: Read random data from avalanche_entropy. */ int TC3(void) { - int i; -#ifdef WAIT_STATS - int n; -#endif + int i, n; unsigned long entropy; if (!quiet) @@ -336,11 +234,8 @@ int TC3(void) for (i = 0; i < num_words; ++i) { /* check status */ -#ifdef WAIT_STATS - if ((n = tc_wait(ENTROPY1_ADDR_STATUS, ENTROPY1_STATUS_VALID)) < 0) -#else - if (tc_wait(ENTROPY1_ADDR_STATUS, ENTROPY1_STATUS_VALID) != 0) -#endif + n = 0; + if (tc_wait(ENTROPY1_ADDR_STATUS, ENTROPY1_STATUS_VALID, &n) != 0) return 1; /* read entropy data */ if (tc_read(ENTROPY1_ADDR_ENTROPY, (uint8_t *)&entropy, 4) != 0) @@ -380,10 +275,7 @@ int TC4(void) /* TC5: Read random data from rosc_entropy. */ int TC5(void) { - int i; -#ifdef WAIT_STATS - int n; -#endif + int i, n; unsigned long entropy; if (!quiet) @@ -391,11 +283,8 @@ int TC5(void) for (i = 0; i < num_words; ++i) { /* check status */ -#ifdef WAIT_STATS - if ((n = tc_wait(ENTROPY2_ADDR_STATUS, ENTROPY2_STATUS_VALID)) < 0) -#else - if (tc_wait(ENTROPY2_ADDR_STATUS, ENTROPY2_STATUS_VALID) != 0) -#endif + n = 0; + if (tc_wait(ENTROPY2_ADDR_STATUS, ENTROPY2_STATUS_VALID, &n) != 0) return 1; /* read entropy data */ if (tc_read(ENTROPY2_ADDR_ENTROPY, (uint8_t *)&entropy, 4) != 0) @@ -427,10 +316,7 @@ int TC6(void) /* TC7: Read random data from trng_csprng. */ int TC7(void) { - int i; -#ifdef WAIT_STATS - int n; -#endif + int i, n; unsigned long random; if (!quiet) @@ -438,11 +324,8 @@ int TC7(void) for (i = 0; i < num_words; ++i) { /* check status */ -#ifdef WAIT_STATS - if ((n = tc_wait(CSPRNG_ADDR_STATUS, CSPRNG_STATUS_VALID)) < 0) -#else - if (tc_wait(CSPRNG_ADDR_STATUS, CSPRNG_STATUS_VALID) != 0) -#endif + n = 0; + if (tc_wait(CSPRNG_ADDR_STATUS, CSPRNG_STATUS_VALID, &n) != 0) return 1; /* read random data */ if (tc_read(CSPRNG_ADDR_RANDOM, (uint8_t *)&random, 4) != 0) diff --git a/i2c/sw/Makefile b/i2c/sw/Makefile index 0142c92..02e7e7d 100755 --- a/i2c/sw/Makefile +++ b/i2c/sw/Makefile @@ -1,7 +1,24 @@ -all: hash_tester_i2c +all: hash_tester_i2c trng_tester_i2c hash_i2c -hash_tester_i2c: hash_tester_i2c.c - gcc -Wall -o $@ $^ +.c.o: + gcc -c -Wall -o $@ $< + +hash_tester_i2c: hash_tester_i2c.o tc_i2c.o + gcc -o $@ $^ + +hash_tester_i2c.o: hash_tester_i2c.c tc_i2c.h + +trng_tester_i2c: trng_tester_i2c.o tc_i2c.o + gcc -o $@ $^ + +trng_tester_i2c.o: trng_tester_i2c.c tc_i2c.h + +hash_i2c: hash_i2c.o tc_i2c.o + gcc -o $@ $^ + +hash_i2c.o: hash_i2c.c tc_i2c.h + +tc_i2c.o: tc_i2c.c tc_i2c.h clean: - rm -f hash_tester_i2c + rm -f *.o hash_tester_i2c trng_tester_i2c hash_i2c diff --git a/i2c/sw/hash_i2c.c b/i2c/sw/hash_i2c.c new file mode 100644 index 0000000..c3ca013 --- /dev/null +++ b/i2c/sw/hash_i2c.c @@ -0,0 +1,409 @@ +/* + * hash.c + * ------ + * This program uses the coretest_hashes subsystem to produce a + * cryptographic hash of a file or input stream. It is a generalization + * of the hash_tester.c test program. + * + * Authors: Joachim Strömbergson, Paul Selkirk + * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of the NORDUnet nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <string.h> +#include <stdio.h> +#include <stdlib.h> +#include <fcntl.h> +#include <unistd.h> +#include <sys/time.h> +#include <stdint.h> +#include <arpa/inet.h> +#include <assert.h> + +#include "tc_i2c.h" + +char *usage = +"Usage: %s [-d] [-v] [-q] [-i I2C_device] [-a I2C_addr] [algorithm [file]]\n" +"algorithms: sha-1, sha-256, sha-512/224, sha-512/256, sha-384, sha-512\n"; + +int debug = 0; +int quiet = 0; +int verbose = 0; + +/* memory segments for core families */ +#define SEGMENT_OFFSET_GLOBALS 0x0000 +#define SEGMENT_OFFSET_HASHES 0x2000 +#define SEGMENT_OFFSET_RNGS 0x4000 +#define SEGMENT_OFFSET_CIPHERS 0x6000 + +#define CORE_SIZE 0x100 + +/* addresses and codes common to all cores */ +#define ADDR_NAME0 0x00 +#define ADDR_NAME1 0x01 +#define ADDR_VERSION 0x02 + +/* At segment 0, we have board-level register and communication channel registers */ +#define BOARD_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0x00 * CORE_SIZE) +#define BOARD_ADDR_NAME0 BOARD_ADDR_BASE + ADDR_NAME0 +#define BOARD_ADDR_NAME1 BOARD_ADDR_BASE + ADDR_NAME1 +#define BOARD_ADDR_VERSION BOARD_ADDR_BASE + ADDR_VERSION +#define BOARD_ADDR_DUMMY BOARD_ADDR_BASE + 0xFF + +#define COMM_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0x01 * CORE_SIZE) +#define COMM_ADDR_NAME0 COMM_ADDR_BASE + ADDR_NAME0 +#define COMM_ADDR_NAME1 COMM_ADDR_BASE + ADDR_NAME1 +#define COMM_ADDR_VERSION COMM_ADDR_BASE + ADDR_VERSION + +/* addresses and codes common to all hash cores */ +#define ADDR_CTRL 0x08 +#define CTRL_INIT_CMD 1 +#define CTRL_NEXT_CMD 2 +#define ADDR_STATUS 0x09 +#define STATUS_READY_BIT 1 +#define STATUS_VALID_BIT 2 +#define ADDR_BLOCK 0x10 +#define ADDR_DIGEST 0x20 + +/* addresses and codes for the specific hash cores */ +#define SHA1_ADDR_BASE SEGMENT_OFFSET_HASHES + (0*CORE_SIZE) +#define SHA1_ADDR_NAME0 SHA1_ADDR_BASE + ADDR_NAME0 +#define SHA1_ADDR_NAME1 SHA1_ADDR_BASE + ADDR_NAME1 +#define SHA1_ADDR_VERSION SHA1_ADDR_BASE + ADDR_VERSION +#define SHA1_ADDR_CTRL SHA1_ADDR_BASE + ADDR_CTRL +#define SHA1_ADDR_STATUS SHA1_ADDR_BASE + ADDR_STATUS +#define SHA1_ADDR_BLOCK SHA1_ADDR_BASE + ADDR_BLOCK +#define SHA1_ADDR_DIGEST SHA1_ADDR_BASE + ADDR_DIGEST +#define SHA1_BLOCK_LEN 512 / 8 +#define SHA1_DIGEST_LEN 160 / 8 + +#define SHA256_ADDR_BASE SEGMENT_OFFSET_HASHES + (1*CORE_SIZE) +#define SHA256_ADDR_NAME0 SHA256_ADDR_BASE + ADDR_NAME0 +#define SHA256_ADDR_NAME1 SHA256_ADDR_BASE + ADDR_NAME1 +#define SHA256_ADDR_VERSION SHA256_ADDR_BASE + ADDR_VERSION +#define SHA256_ADDR_CTRL SHA256_ADDR_BASE + ADDR_CTRL +#define SHA256_ADDR_STATUS SHA256_ADDR_BASE + ADDR_STATUS +#define SHA256_ADDR_BLOCK SHA256_ADDR_BASE + ADDR_BLOCK +#define SHA256_ADDR_DIGEST SHA256_ADDR_BASE + ADDR_DIGEST +#define SHA256_BLOCK_LEN 512 / 8 +#define SHA256_DIGEST_LEN 256 / 8 + +#define SHA512_ADDR_BASE SEGMENT_OFFSET_HASHES + (2*CORE_SIZE) +#define SHA512_ADDR_NAME0 SHA512_ADDR_BASE + ADDR_NAME0 +#define SHA512_ADDR_NAME1 SHA512_ADDR_BASE + ADDR_NAME1 +#define SHA512_ADDR_VERSION SHA512_ADDR_BASE + ADDR_VERSION +#define SHA512_ADDR_CTRL SHA512_ADDR_BASE + ADDR_CTRL +#define SHA512_ADDR_STATUS SHA512_ADDR_BASE + ADDR_STATUS +#define SHA512_ADDR_BLOCK SHA512_ADDR_BASE + ADDR_BLOCK +#define SHA512_ADDR_DIGEST SHA512_ADDR_BASE + 0x40 +#define SHA512_BLOCK_LEN 1024 / 8 +#define SHA512_224_DIGEST_LEN 224 / 8 +#define SHA512_256_DIGEST_LEN 256 / 8 +#define SHA384_DIGEST_LEN 384 / 8 +#define SHA512_DIGEST_LEN 512 / 8 +#define MODE_SHA_512_224 0 << 2 +#define MODE_SHA_512_256 1 << 2 +#define MODE_SHA_384 2 << 2 +#define MODE_SHA_512 3 << 2 + +/* ---------------- algorithm lookup code ---------------- */ + +struct ctrl { + char *name; + off_t block_addr; + int block_len; + off_t digest_addr; + int digest_len; + int mode; +} ctrl[] = { + { "sha-1", SHA1_ADDR_BLOCK, SHA1_BLOCK_LEN, + SHA1_ADDR_DIGEST, SHA1_DIGEST_LEN, 0 }, + { "sha-256", SHA256_ADDR_BLOCK, SHA256_BLOCK_LEN, + SHA256_ADDR_DIGEST, SHA256_DIGEST_LEN, 0 }, + { "sha-512/224", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, + SHA512_ADDR_DIGEST, SHA512_224_DIGEST_LEN, MODE_SHA_512_224 }, + { "sha-512/256", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, + SHA512_ADDR_DIGEST, SHA512_256_DIGEST_LEN, MODE_SHA_512_256 }, + { "sha-384", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, + SHA512_ADDR_DIGEST, SHA384_DIGEST_LEN, MODE_SHA_384 }, + { "sha-512", SHA512_ADDR_BLOCK, SHA512_BLOCK_LEN, + SHA512_ADDR_DIGEST, SHA512_DIGEST_LEN, MODE_SHA_512 }, + { NULL, 0, 0, 0 } +}; + +/* return the control structure for the given algorithm */ +struct ctrl *find_algo(char *algo) +{ + int i; + + for (i = 0; ctrl[i].name != NULL; ++i) + if (strcmp(ctrl[i].name, algo) == 0) + return &ctrl[i]; + + fprintf(stderr, "algorithm \"%s\" not found\n\n", algo); + fprintf(stderr, usage, "hash"); + return NULL; +} + +/* ---------------- test-case low-level code ---------------- */ + +int tc_init(off_t offset, int mode) +{ + uint8_t buf[4] = { 0, 0, 0, CTRL_INIT_CMD + mode }; + + return tc_write(offset, buf, 4); +} + +int tc_next(off_t offset, int mode) +{ + uint8_t buf[4] = { 0, 0, 0, CTRL_NEXT_CMD + mode }; + + return tc_write(offset, buf, 4); +} + +int tc_wait_ready(off_t offset) +{ + int limit = 10; + return tc_wait(offset, STATUS_READY_BIT, &limit); +} + +int tc_wait_valid(off_t offset) +{ + int limit = 10; + return tc_wait(offset, STATUS_VALID_BIT, &limit); +} + +/* ---------------- hash ---------------- */ + +int transmit(off_t offset, uint8_t *block, int blen, int mode, int first) +{ + off_t base = offset & ~(0xff); + + if (tc_write(offset, block, blen) != 0) + return EXIT_FAILURE; + + if (first) { + if (tc_init(base + ADDR_CTRL, mode) != 0) + return EXIT_FAILURE; + } + else { + if (tc_next(base + ADDR_CTRL, mode) != 0) + return EXIT_FAILURE; + } + + return tc_wait_ready(base + ADDR_STATUS); +} + +int pad_transmit(off_t offset, uint8_t *block, uint8_t flen, uint8_t blen, + uint8_t mode, long long tlen, int first) +{ + assert(flen < blen); + + block[flen++] = 0x80; + memset(block + flen, 0, blen - flen); + + if (blen - flen < ((blen == 64) ? 8 : 16)) { + if (transmit(offset, block, blen, mode, first) != 0) + return EXIT_FAILURE; + first = 0; + memset(block, 0, blen); + } + + /* properly the length is 128 bits for sha-512, but we can't + * actually count above 64 bits + */ + ((uint32_t *)block)[blen/4 - 2] = htonl((tlen >> 32) & 0xffff); + ((uint32_t *)block)[blen/4 - 1] = htonl(tlen & 0xffff); + + return transmit(offset, block, blen, mode, first); +} + +/* return number of digest bytes read */ +int hash(char *algo, char *file, uint8_t *digest) +{ + uint8_t block[SHA512_BLOCK_LEN]; + struct ctrl *ctrl; + int in_fd = 0; /* stdin */ + off_t baddr, daddr; + int blen, dlen, mode; + int nblk, nread, first; + int ret = -1; + struct timeval start, stop, difftime; + + ctrl = find_algo(algo); + if (ctrl == NULL) + return -1; + baddr = ctrl->block_addr; + blen = ctrl->block_len; + daddr = ctrl->digest_addr; + dlen = ctrl->digest_len; + mode = ctrl->mode; + + if (strcmp(file, "-") != 0) { + in_fd = open(file, O_RDONLY); + if (in_fd < 0) { + perror("open"); + return -1; + } + } + + if (verbose) { + if (gettimeofday(&start, NULL) < 0) { + perror("gettimeofday"); + goto out; + } + } + + for (nblk = 0, first = 1; ; ++nblk, first = 0) { + nread = read(in_fd, block, blen); + if (nread < 0) { + /* read error */ + perror("read"); + goto out; + } + else if (nread < blen) { + /* partial read = last block */ + if (pad_transmit(baddr, block, nread, blen, mode, + (nblk * blen + nread) * 8, first) != 0) + goto out; + break; + } + else { + /* full block read */ + if (transmit(baddr, block, blen, mode, first) != 0) + goto out; + } + } + + /* Strictly speaking we should query "valid" status before reading digest, + * but transmit() waits for "ready" status before returning, and the SHA + * cores always assert valid before ready. + */ + if (tc_read(daddr, digest, dlen) != 0) { + perror("i2c read failed"); + goto out; + } + + if (verbose) { + if (gettimeofday(&stop, NULL) < 0) { + perror("gettimeofday"); + goto out; + } + timersub(&stop, &start, &difftime); + printf("%d blocks written in %d.%03d sec (%.3f blocks/sec)\n", + nblk, (int)difftime.tv_sec, (int)difftime.tv_usec/1000, + (float)nblk / ((float)difftime.tv_sec + ((float)difftime.tv_usec)/1000000)); + } + + ret = dlen; +out: + if (in_fd != 0) + close(in_fd); + return ret; +} + +/* ---------------- main ---------------- */ + +int main(int argc, char *argv[]) +{ + char *dev = I2C_dev; + int addr = I2C_addr; + int i, opt; + char *algo = "sha-1"; + char *file = "-"; + uint8_t digest[512/8]; + int dlen; + + while ((opt = getopt(argc, argv, "h?dvqi:a:")) != -1) { + switch (opt) { + case 'h': + case '?': + printf(usage, argv[0]); + return EXIT_SUCCESS; + case 'd': + debug = 1; + break; + case 'v': + verbose = 1; + break; + case 'q': + quiet = 1; + break; + case 'i': + dev = optarg; + break; + case 'a': + addr = (int)strtol(optarg, NULL, 0); + if ((addr < 0x03) || (addr > 0x77)) { + fprintf(stderr, "addr must be between 0x03 and 0x77\n"); + return EXIT_FAILURE; + } + break; + default: + fprintf(stderr, usage, argv[0]); + return EXIT_FAILURE; + } + } + + if (optind < argc) { + algo = argv[optind]; + ++optind; + } + else { + if (!quiet) + printf("defaulting to algorithm \"%s\"\n", algo); + } + + if (optind < argc) { + file = argv[optind]; + ++optind; + } + else { + if (!quiet) + printf("reading from stdin\n"); + } + + if (i2c_open(dev, addr) != 0) + return EXIT_FAILURE; + + dlen = hash(algo, file, digest); + if (dlen < 0) + return EXIT_FAILURE; + + for (i = 0; i < dlen; ++i) { + printf("%02x", digest[i]); + if (i % 16 == 15) + printf("\n"); + else if (i % 4 == 3) + printf(" "); + } + if (dlen % 16 != 0) + printf("\n"); + + return EXIT_SUCCESS; +} diff --git a/i2c/sw/hash_tester_i2c.c b/i2c/sw/hash_tester_i2c.c index f1c6fb4..dc02691 100644 --- a/i2c/sw/hash_tester_i2c.c +++ b/i2c/sw/hash_tester_i2c.c @@ -13,71 +13,55 @@ * * * Authors: Joachim Strömbergson, Paul Selkirk - * Copyright (c) 2014, SUNET + * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. * - * Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of the NORDUnet nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include <string.h> #include <stdio.h> #include <stdlib.h> -#include <errno.h> -#include <sys/mman.h> -#include <fcntl.h> #include <unistd.h> #include <time.h> -#include <linux/i2c-dev.h> -#include <sys/ioctl.h> -#include <arpa/inet.h> +#include <stdint.h> #include <ctype.h> -/* I2C configuration */ -#define I2C_dev "/dev/i2c-2" -#define I2C_addr 0x0f - -/* command codes */ -#define SOC 0x55 -#define EOC 0xaa -#define READ_CMD 0x10 -#define WRITE_CMD 0x11 -#define RESET_CMD 0x01 - -/* response codes */ -#define SOR 0xaa -#define EOR 0x55 -#define READ_OK 0x7f -#define WRITE_OK 0x7e -#define RESET_OK 0x7d -#define UNKNOWN 0xfe -#define ERROR 0xfd - -#define SEGMENT_OFFSET_GLOBALS 0x00 -#define SEGMENT_OFFSET_HASHES 0x20 -#define SEGMENT_OFFSET_RNGS 0x40 -#define SEGMENT_OFFSET_CIPHERS 0x60 +#include "tc_i2c.h" + +int debug = 0; +int quiet = 0; + +/* memory segments for core families */ +#define SEGMENT_OFFSET_GLOBALS 0x0000 +#define SEGMENT_OFFSET_HASHES 0x2000 +#define SEGMENT_OFFSET_RNGS 0x4000 +#define SEGMENT_OFFSET_CIPHERS 0x6000 + +#define CORE_SIZE 0x100 /* addresses and codes common to all cores */ #define ADDR_NAME0 0x00 @@ -85,10 +69,16 @@ #define ADDR_VERSION 0x02 /* At segment 0, we have board-level register and communication channel registers */ -#define BOARD_ADDR_PREFIX SEGMENT_OFFSET_GLOBALS + 0x00 -#define BOARD_ADDR_DUMMY 0xFF +#define BOARD_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0x00 * CORE_SIZE) +#define BOARD_ADDR_NAME0 BOARD_ADDR_BASE + ADDR_NAME0 +#define BOARD_ADDR_NAME1 BOARD_ADDR_BASE + ADDR_NAME1 +#define BOARD_ADDR_VERSION BOARD_ADDR_BASE + ADDR_VERSION +#define BOARD_ADDR_DUMMY BOARD_ADDR_BASE + 0xFF -#define COMM_ADDR_PREFIX SEGMENT_OFFSET_GLOBALS + 0x01 +#define COMM_ADDR_BASE SEGMENT_OFFSET_GLOBALS + (0x01 * CORE_SIZE) +#define COMM_ADDR_NAME0 COMM_ADDR_BASE + ADDR_NAME0 +#define COMM_ADDR_NAME1 COMM_ADDR_BASE + ADDR_NAME1 +#define COMM_ADDR_VERSION COMM_ADDR_BASE + ADDR_VERSION /* addresses and codes common to all hash cores */ #define ADDR_CTRL 0x08 @@ -97,847 +87,574 @@ #define ADDR_STATUS 0x09 #define STATUS_READY_BIT 1 #define STATUS_VALID_BIT 2 +#define ADDR_BLOCK 0x10 +#define ADDR_DIGEST 0x20 /* addresses and codes for the specific hash cores */ -#define SHA1_ADDR_PREFIX SEGMENT_OFFSET_HASHES + 0x00 -#define SHA1_ADDR_BLOCK 0x10 -#define SHA1_BLOCK_LEN 16 -#define SHA1_ADDR_DIGEST 0x20 -#define SHA1_DIGEST_LEN 5 - -#define SHA256_ADDR_PREFIX SEGMENT_OFFSET_HASHES + 0x01 -#define SHA256_ADDR_BLOCK 0x10 -#define SHA256_BLOCK_LEN 16 -#define SHA256_ADDR_DIGEST 0x20 -#define SHA256_DIGEST_LEN 8 - -#define SHA512_ADDR_PREFIX SEGMENT_OFFSET_HASHES + 0x02 -#define SHA512_CTRL_MODE_LOW 2 -#define SHA512_CTRL_MODE_HIGH 3 -#define SHA512_ADDR_BLOCK 0x10 -#define SHA512_BLOCK_LEN 32 -#define SHA512_ADDR_DIGEST 0x40 -#define SHA512_DIGEST_LEN 16 -#define MODE_SHA_512_224 0 -#define MODE_SHA_512_256 1 -#define MODE_SHA_384 2 -#define MODE_SHA_512 3 - -int i2cfd; -int debug = 0; +#define SHA1_ADDR_BASE SEGMENT_OFFSET_HASHES + (0*CORE_SIZE) +#define SHA1_ADDR_NAME0 SHA1_ADDR_BASE + ADDR_NAME0 +#define SHA1_ADDR_NAME1 SHA1_ADDR_BASE + ADDR_NAME1 +#define SHA1_ADDR_VERSION SHA1_ADDR_BASE + ADDR_VERSION +#define SHA1_ADDR_CTRL SHA1_ADDR_BASE + ADDR_CTRL +#define SHA1_ADDR_STATUS SHA1_ADDR_BASE + ADDR_STATUS +#define SHA1_ADDR_BLOCK SHA1_ADDR_BASE + ADDR_BLOCK +#define SHA1_ADDR_DIGEST SHA1_ADDR_BASE + ADDR_DIGEST +#define SHA1_BLOCK_LEN 512 / 8 +#define SHA1_DIGEST_LEN 160 / 8 + +#define SHA256_ADDR_BASE SEGMENT_OFFSET_HASHES + (1*CORE_SIZE) +#define SHA256_ADDR_NAME0 SHA256_ADDR_BASE + ADDR_NAME0 +#define SHA256_ADDR_NAME1 SHA256_ADDR_BASE + ADDR_NAME1 +#define SHA256_ADDR_VERSION SHA256_ADDR_BASE + ADDR_VERSION +#define SHA256_ADDR_CTRL SHA256_ADDR_BASE + ADDR_CTRL +#define SHA256_ADDR_STATUS SHA256_ADDR_BASE + ADDR_STATUS +#define SHA256_ADDR_BLOCK SHA256_ADDR_BASE + ADDR_BLOCK +#define SHA256_ADDR_DIGEST SHA256_ADDR_BASE + ADDR_DIGEST +#define SHA256_BLOCK_LEN 512 / 8 +#define SHA256_DIGEST_LEN 256 / 8 + +#define SHA512_ADDR_BASE SEGMENT_OFFSET_HASHES + (2*CORE_SIZE) +#define SHA512_ADDR_NAME0 SHA512_ADDR_BASE + ADDR_NAME0 +#define SHA512_ADDR_NAME1 SHA512_ADDR_BASE + ADDR_NAME1 +#define SHA512_ADDR_VERSION SHA512_ADDR_BASE + ADDR_VERSION +#define SHA512_ADDR_CTRL SHA512_ADDR_BASE + ADDR_CTRL +#define SHA512_ADDR_STATUS SHA512_ADDR_BASE + ADDR_STATUS +#define SHA512_ADDR_BLOCK SHA512_ADDR_BASE + ADDR_BLOCK +#define SHA512_ADDR_DIGEST SHA512_ADDR_BASE + 0x0 +#define SHA512_BLOCK_LEN 1024 / 8 +#define SHA512_224_DIGEST_LEN 224 / 8 +#define SHA512_256_DIGEST_LEN 256 / 8 +#define SHA384_DIGEST_LEN 384 / 8 +#define SHA512_DIGEST_LEN 512 / 8 +#define MODE_SHA_512_224 0 << 2 +#define MODE_SHA_512_256 1 << 2 +#define MODE_SHA_384 2 << 2 +#define MODE_SHA_512 3 << 2 /* SHA-1/SHA-256 One Block Message Sample Input Message: "abc" */ -const uint32_t NIST_512_SINGLE[] = -{ 0x61626380, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000018 }; - -const uint32_t SHA1_SINGLE_DIGEST[] = -{ 0xa9993e36, 0x4706816a, 0xba3e2571, 0x7850c26c, - 0x9cd0d89d }; - -const uint32_t SHA256_SINGLE_DIGEST[] = -{ 0xBA7816BF, 0x8F01CFEA, 0x414140DE, 0x5DAE2223, - 0xB00361A3, 0x96177A9C, 0xB410FF61, 0xF20015AD }; +const uint8_t NIST_512_SINGLE[] = +{ 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18 }; + +const uint8_t SHA1_SINGLE_DIGEST[] = +{ 0xa9, 0x99, 0x3e, 0x36, 0x47, 0x06, 0x81, 0x6a, + 0xba, 0x3e, 0x25, 0x71, 0x78, 0x50, 0xc2, 0x6c, + 0x9c, 0xd0, 0xd8, 0x9d }; + +const uint8_t SHA256_SINGLE_DIGEST[] = +{ 0xBA, 0x78, 0x16, 0xBF, 0x8F, 0x01, 0xCF, 0xEA, + 0x41, 0x41, 0x40, 0xDE, 0x5D, 0xAE, 0x22, 0x23, + 0xB0, 0x03, 0x61, 0xA3, 0x96, 0x17, 0x7A, 0x9C, + 0xB4, 0x10, 0xFF, 0x61, 0xF2, 0x00, 0x15, 0xAD }; /* SHA-1/SHA-256 Two Block Message Sample Input Message: "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" */ -const uint32_t NIST_512_DOUBLE0[] = -{ 0x61626364, 0x62636465, 0x63646566, 0x64656667, - 0x65666768, 0x66676869, 0x6768696A, 0x68696A6B, - 0x696A6B6C, 0x6A6B6C6D, 0x6B6C6D6E, 0x6C6D6E6F, - 0x6D6E6F70, 0x6E6F7071, 0x80000000, 0x00000000 }; -const uint32_t NIST_512_DOUBLE1[] = -{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x000001C0 }; - -const uint32_t SHA1_DOUBLE_DIGEST[] = -{ 0x84983E44, 0x1C3BD26E, 0xBAAE4AA1, 0xF95129E5, - 0xE54670F1 }; - -const uint32_t SHA256_DOUBLE_DIGEST[] = -{ 0x248D6A61, 0xD20638B8, 0xE5C02693, 0x0C3E6039, - 0xA33CE459, 0x64FF2167, 0xF6ECEDD4, 0x19DB06C1 }; +const uint8_t NIST_512_DOUBLE0[] = +{ 0x61, 0x62, 0x63, 0x64, 0x62, 0x63, 0x64, 0x65, + 0x63, 0x64, 0x65, 0x66, 0x64, 0x65, 0x66, 0x67, + 0x65, 0x66, 0x67, 0x68, 0x66, 0x67, 0x68, 0x69, + 0x67, 0x68, 0x69, 0x6A, 0x68, 0x69, 0x6A, 0x6B, + 0x69, 0x6A, 0x6B, 0x6C, 0x6A, 0x6B, 0x6C, 0x6D, + 0x6B, 0x6C, 0x6D, 0x6E, 0x6C, 0x6D, 0x6E, 0x6F, + 0x6D, 0x6E, 0x6F, 0x70, 0x6E, 0x6F, 0x70, 0x71, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; +const uint8_t NIST_512_DOUBLE1[] = +{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xC0 }; + +const uint8_t SHA1_DOUBLE_DIGEST[] = +{ 0x84, 0x98, 0x3E, 0x44, 0x1C, 0x3B, 0xD2, 0x6E, + 0xBA, 0xAE, 0x4A, 0xA1, 0xF9, 0x51, 0x29, 0xE5, + 0xE5, 0x46, 0x70, 0xF1 }; + +const uint8_t SHA256_DOUBLE_DIGEST[] = +{ 0x24, 0x8D, 0x6A, 0x61, 0xD2, 0x06, 0x38, 0xB8, + 0xE5, 0xC0, 0x26, 0x93, 0x0C, 0x3E, 0x60, 0x39, + 0xA3, 0x3C, 0xE4, 0x59, 0x64, 0xFF, 0x21, 0x67, + 0xF6, 0xEC, 0xED, 0xD4, 0x19, 0xDB, 0x06, 0xC1 }; /* SHA-512 One Block Message Sample Input Message: "abc" */ -const uint32_t NIST_1024_SINGLE[] = -{ 0x61626380, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000018 }; - -const uint32_t SHA512_224_SINGLE_DIGEST[] = -{ 0x4634270f, 0x707b6a54, 0xdaae7530, 0x460842e2, - 0x0e37ed26, 0x5ceee9a4, 0x3e8924aa }; -const uint32_t SHA512_256_SINGLE_DIGEST[] = -{ 0x53048e26, 0x81941ef9, 0x9b2e29b7, 0x6b4c7dab, - 0xe4c2d0c6, 0x34fc6d46, 0xe0e2f131, 0x07e7af23 }; -const uint32_t SHA384_SINGLE_DIGEST[] = -{ 0xcb00753f, 0x45a35e8b, 0xb5a03d69, 0x9ac65007, - 0x272c32ab, 0x0eded163, 0x1a8b605a, 0x43ff5bed, - 0x8086072b, 0xa1e7cc23, 0x58baeca1, 0x34c825a7 }; -const uint32_t SHA512_SINGLE_DIGEST[] = -{ 0xddaf35a1, 0x93617aba, 0xcc417349, 0xae204131, - 0x12e6fa4e, 0x89a97ea2, 0x0a9eeee6, 0x4b55d39a, - 0x2192992a, 0x274fc1a8, 0x36ba3c23, 0xa3feebbd, - 0x454d4423, 0x643ce80e, 0x2a9ac94f, 0xa54ca49f }; +const uint8_t NIST_1024_SINGLE[] = +{ 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18 }; + +const uint8_t SHA512_224_SINGLE_DIGEST[] = +{ 0x46, 0x34, 0x27, 0x0f, 0x70, 0x7b, 0x6a, 0x54, + 0xda, 0xae, 0x75, 0x30, 0x46, 0x08, 0x42, 0xe2, + 0x0e, 0x37, 0xed, 0x26, 0x5c, 0xee, 0xe9, 0xa4, + 0x3e, 0x89, 0x24, 0xaa }; +const uint8_t SHA512_256_SINGLE_DIGEST[] = +{ 0x53, 0x04, 0x8e, 0x26, 0x81, 0x94, 0x1e, 0xf9, + 0x9b, 0x2e, 0x29, 0xb7, 0x6b, 0x4c, 0x7d, 0xab, + 0xe4, 0xc2, 0xd0, 0xc6, 0x34, 0xfc, 0x6d, 0x46, + 0xe0, 0xe2, 0xf1, 0x31, 0x07, 0xe7, 0xaf, 0x23 }; +const uint8_t SHA384_SINGLE_DIGEST[] = +{ 0xcb, 0x00, 0x75, 0x3f, 0x45, 0xa3, 0x5e, 0x8b, + 0xb5, 0xa0, 0x3d, 0x69, 0x9a, 0xc6, 0x50, 0x07, + 0x27, 0x2c, 0x32, 0xab, 0x0e, 0xde, 0xd1, 0x63, + 0x1a, 0x8b, 0x60, 0x5a, 0x43, 0xff, 0x5b, 0xed, + 0x80, 0x86, 0x07, 0x2b, 0xa1, 0xe7, 0xcc, 0x23, + 0x58, 0xba, 0xec, 0xa1, 0x34, 0xc8, 0x25, 0xa7 }; +const uint8_t SHA512_SINGLE_DIGEST[] = +{ 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, + 0xcc, 0x41, 0x73, 0x49, 0xae, 0x20, 0x41, 0x31, + 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, + 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, + 0x21, 0x92, 0x99, 0x2a, 0x27, 0x4f, 0xc1, 0xa8, + 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, + 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, + 0x2a, 0x9a, 0xc9, 0x4f, 0xa5, 0x4c, 0xa4, 0x9f }; /* SHA-512 Two Block Message Sample Input Message: "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmn" "hijklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu" */ -const uint32_t NIST_1024_DOUBLE0[] = -{ 0x61626364, 0x65666768, 0x62636465, 0x66676869, - 0x63646566, 0x6768696a, 0x64656667, 0x68696a6b, - 0x65666768, 0x696a6b6c, 0x66676869, 0x6a6b6c6d, - 0x6768696a, 0x6b6c6d6e, 0x68696a6b, 0x6c6d6e6f, - 0x696a6b6c, 0x6d6e6f70, 0x6a6b6c6d, 0x6e6f7071, - 0x6b6c6d6e, 0x6f707172, 0x6c6d6e6f, 0x70717273, - 0x6d6e6f70, 0x71727374, 0x6e6f7071, 0x72737475, - 0x80000000, 0x00000000, 0x00000000, 0x00000000 }; -const uint32_t NIST_1024_DOUBLE1[] = -{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000380 }; - -const uint32_t SHA512_224_DOUBLE_DIGEST[] = -{ 0x23fec5bb, 0x94d60b23, 0x30819264, 0x0b0c4533, - 0x35d66473, 0x4fe40e72, 0x68674af9 }; -const uint32_t SHA512_256_DOUBLE_DIGEST[] = -{ 0x3928e184, 0xfb8690f8, 0x40da3988, 0x121d31be, - 0x65cb9d3e, 0xf83ee614, 0x6feac861, 0xe19b563a }; -const uint32_t SHA384_DOUBLE_DIGEST[] = -{ 0x09330c33, 0xf71147e8, 0x3d192fc7, 0x82cd1b47, - 0x53111b17, 0x3b3b05d2, 0x2fa08086, 0xe3b0f712, - 0xfcc7c71a, 0x557e2db9, 0x66c3e9fa, 0x91746039 }; -const uint32_t SHA512_DOUBLE_DIGEST[] = -{ 0x8e959b75, 0xdae313da, 0x8cf4f728, 0x14fc143f, - 0x8f7779c6, 0xeb9f7fa1, 0x7299aead, 0xb6889018, - 0x501d289e, 0x4900f7e4, 0x331b99de, 0xc4b5433a, - 0xc7d329ee, 0xb6dd2654, 0x5e96e55b, 0x874be909 }; - -/* ---------------- I2C low-level code ---------------- */ -int i2c_setup(char *dev, int addr) -{ - i2cfd = open(dev, O_RDWR); - if (i2cfd < 0) { - fprintf(stderr, "Unable to open %s: ", dev); - perror(""); - i2cfd = 0; - return 1; - } - - if (ioctl(i2cfd, I2C_SLAVE, addr) < 0) { - fprintf(stderr, "Unable to set I2C slave device 0x%02x: ", addr); - perror(""); - return 1; - } - - return 0; -} - -int i2c_write(uint8_t *buf, int len) -{ - if (debug) { - int i; - printf("write ["); - for (i = 0; i < len; ++i) - printf(" %02x", buf[i]); - printf(" ]\n"); - } - - if (write(i2cfd, buf, len) != len) { - perror("i2c write failed"); - return 1; - } - - return 0; -} - -int i2c_read(uint8_t *b) -{ - /* read() on the i2c device only returns one byte at a time, - * and tc_get_resp() needs to parse the response one byte at a time - */ - if (read(i2cfd, b, 1) != 1) { - perror("i2c read failed"); - return 1; - } - - return 0; -} +const uint8_t NIST_1024_DOUBLE0[] = +{ 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, + 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, + 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, + 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, + 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, + 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, + 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, + 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, + 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, + 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, + 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, + 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73, + 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, + 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; +const uint8_t NIST_1024_DOUBLE1[] = +{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x80 }; + +const uint8_t SHA512_224_DOUBLE_DIGEST[] = +{ 0x23, 0xfe, 0xc5, 0xbb, 0x94, 0xd6, 0x0b, 0x23, + 0x30, 0x81, 0x92, 0x64, 0x0b, 0x0c, 0x45, 0x33, + 0x35, 0xd6, 0x64, 0x73, 0x4f, 0xe4, 0x0e, 0x72, + 0x68, 0x67, 0x4a, 0xf9 }; +const uint8_t SHA512_256_DOUBLE_DIGEST[] = +{ 0x39, 0x28, 0xe1, 0x84, 0xfb, 0x86, 0x90, 0xf8, + 0x40, 0xda, 0x39, 0x88, 0x12, 0x1d, 0x31, 0xbe, + 0x65, 0xcb, 0x9d, 0x3e, 0xf8, 0x3e, 0xe6, 0x14, + 0x6f, 0xea, 0xc8, 0x61, 0xe1, 0x9b, 0x56, 0x3a }; +const uint8_t SHA384_DOUBLE_DIGEST[] = +{ 0x09, 0x33, 0x0c, 0x33, 0xf7, 0x11, 0x47, 0xe8, + 0x3d, 0x19, 0x2f, 0xc7, 0x82, 0xcd, 0x1b, 0x47, + 0x53, 0x11, 0x1b, 0x17, 0x3b, 0x3b, 0x05, 0xd2, + 0x2f, 0xa0, 0x80, 0x86, 0xe3, 0xb0, 0xf7, 0x12, + 0xfc, 0xc7, 0xc7, 0x1a, 0x55, 0x7e, 0x2d, 0xb9, + 0x66, 0xc3, 0xe9, 0xfa, 0x91, 0x74, 0x60, 0x39 }; +const uint8_t SHA512_DOUBLE_DIGEST[] = +{ 0x8e, 0x95, 0x9b, 0x75, 0xda, 0xe3, 0x13, 0xda, + 0x8c, 0xf4, 0xf7, 0x28, 0x14, 0xfc, 0x14, 0x3f, + 0x8f, 0x77, 0x79, 0xc6, 0xeb, 0x9f, 0x7f, 0xa1, + 0x72, 0x99, 0xae, 0xad, 0xb6, 0x88, 0x90, 0x18, + 0x50, 0x1d, 0x28, 0x9e, 0x49, 0x00, 0xf7, 0xe4, + 0x33, 0x1b, 0x99, 0xde, 0xc4, 0xb5, 0x43, 0x3a, + 0xc7, 0xd3, 0x29, 0xee, 0xb6, 0xdd, 0x26, 0x54, + 0x5e, 0x96, 0xe5, 0x5b, 0x87, 0x4b, 0xe9, 0x09 }; /* ---------------- test-case low-level code ---------------- */ -int tc_send_write_cmd(uint8_t addr0, uint8_t addr1, uint32_t data) -{ - uint8_t buf[9]; - - buf[0] = SOC; - buf[1] = WRITE_CMD; - buf[2] = addr0; - buf[3] = addr1; - buf[4] = (data >> 24) & 0xff; - buf[5] = (data >> 16) & 0xff; - buf[6] = (data >> 8) & 0xff; - buf[7] = data & 0xff; - buf[8] = EOC; - - return i2c_write(buf, sizeof(buf)); -} - -int tc_send_read_cmd(uint8_t addr0, uint8_t addr1) -{ - uint8_t buf[5]; - - buf[0] = SOC; - buf[1] = READ_CMD; - buf[2] = addr0; - buf[3] = addr1; - buf[4] = EOC; - - return i2c_write(buf, sizeof(buf)); -} - -int tc_get_resp(uint8_t *buf, int len) -{ - int i; - - for (i = 0; i < len; ++i) { - if (i2c_read(&buf[i]) != 0) - return 1; - if ((i == 0) && (buf[i] != SOR)) { - /* we've gotten out of sync, and there's probably nothing we can do */ - fprintf(stderr, "response byte 0: expected 0x%02x (SOR), got 0x%02x\n", - SOR, buf[0]); - return 1; - } - else if (i == 1) { /* response code */ - switch (buf[i]) { - case READ_OK: - len = 9; - break; - case WRITE_OK: - len = 5; - break; - case RESET_OK: - len = 3; - break; - case ERROR: - case UNKNOWN: - len = 4; - break; - default: - /* we've gotten out of sync, and there's probably nothing we can do */ - fprintf(stderr, "unknown response code 0x%02x\n", buf[i]); - return 1; - } - } - } - - if (debug) { - printf("read ["); - for (i = 0; i < len; ++i) - printf(" %02x", buf[i]); - printf(" ]\n"); - } - - return 0; -} - -int tc_get_expected(uint8_t *expected, int len) -{ - uint8_t buf[9]; - int i; - - if (tc_get_resp(buf, sizeof(buf)) != 0) - return 1; - - for (i = 0; i < len; ++i) { - if (buf[i] != expected[i]) { - fprintf(stderr, "response byte %d: expected 0x%02x, got 0x%02x\n", - i, expected[i], buf[i]); - return 1; - } - } - - return 0; -} - -int tc_get_write_resp(uint8_t addr0, uint8_t addr1) -{ - uint8_t expected[5]; - - expected[0] = SOR; - expected[1] = WRITE_OK; - expected[2] = addr0; - expected[3] = addr1; - expected[4] = EOR; - - return tc_get_expected(expected, sizeof(expected)); -} - -int tc_get_read_resp(uint8_t addr0, uint8_t addr1, uint32_t data) -{ - uint8_t expected[9]; - - expected[0] = SOR; - expected[1] = READ_OK; - expected[2] = addr0; - expected[3] = addr1; - expected[4] = (data >> 24) & 0xff; - expected[5] = (data >> 16) & 0xff; - expected[6] = (data >> 8) & 0xff; - expected[7] = data & 0xff; - expected[8] = EOR; - - return tc_get_expected(expected, sizeof(expected)); -} - -int tc_write(uint8_t addr0, uint8_t addr1, uint32_t data) -{ - return (tc_send_write_cmd(addr0, addr1, data) || - tc_get_write_resp(addr0, addr1)); -} -int tc_read(uint8_t addr0, uint8_t addr1, uint32_t data) +int tc_init(off_t offset) { - return (tc_send_read_cmd(addr0, addr1) || - tc_get_read_resp(addr0, addr1, data)); -} - -int tc_init(uint8_t addr0) -{ - return tc_write(addr0, ADDR_CTRL, CTRL_INIT_CMD); -} + uint8_t buf[4] = { 0, 0, 0, CTRL_INIT_CMD }; -int tc_next(uint8_t addr0) -{ - return tc_write(addr0, ADDR_CTRL, CTRL_NEXT_CMD); + return tc_write(offset, buf, 4); } -int tc_wait(uint8_t addr0, uint8_t status) +int tc_next(off_t offset) { - uint8_t buf[9]; - - do { - if (tc_send_read_cmd(addr0, ADDR_STATUS) != 0) - return 1; - if (tc_get_resp(buf, 9) != 0) - return 1; - if (buf[1] != READ_OK) - return 1; - } while ((buf[7] & status) != status); + uint8_t buf[4] = { 0, 0, 0, CTRL_NEXT_CMD }; - return 0; + return tc_write(offset, buf, 4); } -int tc_wait_ready(uint8_t addr0) +int tc_wait_ready(off_t offset) { - return tc_wait(addr0, STATUS_READY_BIT); + int limit = 10; + return tc_wait(offset, STATUS_READY_BIT, &limit); } -int tc_wait_valid(uint8_t addr0) +int tc_wait_valid(off_t offset) { - return tc_wait(addr0, STATUS_VALID_BIT); + int limit = 10; + return tc_wait(offset, STATUS_VALID_BIT, &limit); } /* ---------------- sanity test case ---------------- */ int TC0() { - uint32_t board_name0 = 0x50565431; /* "PVT1" */ - uint32_t board_name1 = 0x20202020; /* " " */ - uint32_t board_version = 0x302e3130; /* "0.10" */ + uint8_t board_name0[4] = "PVT1"; + uint8_t board_name1[4] = " "; + uint8_t board_version[4] = "0.10"; - uint32_t comm_name0 = 0x69326320; /* "i2c " */ - uint32_t comm_name1 = 0x20202020; /* " " */ - uint32_t comm_version = 0x302e3130; /* "0.10" */ + uint8_t comm_name0[4] = "i2c "; + uint8_t comm_name1[4] = " "; + uint8_t comm_version[4] = "0.10"; - uint32_t t; + uint8_t t[4]; - printf("TC0-1: Reading board type, version, and dummy reg from global registers.\n"); + if (!quiet) + printf("TC0-1: Reading board type, version, and dummy reg from global registers.\n"); /* write current time into dummy register, then try to read it back - * to make sure that we can actually write something into I2C + * to make sure that we can actually write something into EIM */ - t = time(NULL); - tc_write(BOARD_ADDR_PREFIX, BOARD_ADDR_DUMMY, t); - - if (tc_read(BOARD_ADDR_PREFIX, ADDR_NAME0, board_name0) || - tc_read(BOARD_ADDR_PREFIX, ADDR_NAME1, board_name1) || - tc_read(BOARD_ADDR_PREFIX, ADDR_VERSION, board_version) || - tc_read(BOARD_ADDR_PREFIX, BOARD_ADDR_DUMMY, t)) + (void)time((time_t *)t); + if (tc_write(BOARD_ADDR_DUMMY, t, 4) != 0) return 1; - printf("TC0-2: Reading name and version words from communications core.\n"); + if (tc_expected(BOARD_ADDR_NAME0, board_name0, 4) || + tc_expected(BOARD_ADDR_NAME1, board_name1, 4) || + tc_expected(BOARD_ADDR_VERSION, board_version, 4) || + tc_expected(BOARD_ADDR_DUMMY, t, 4)) + return 1; - return - tc_read(COMM_ADDR_PREFIX, ADDR_NAME0, comm_name0) || - tc_read(COMM_ADDR_PREFIX, ADDR_NAME1, comm_name1) || - tc_read(COMM_ADDR_PREFIX, ADDR_VERSION, comm_version); -} - -/* ---------------- SHA-1 test cases ---------------- */ + if (!quiet) + printf("TC0-2: Reading name and version words from communications core.\n"); -int sha1_read(uint8_t addr, uint32_t data) -{ - return tc_read(SHA1_ADDR_PREFIX, addr, data); -} - -int sha1_write(uint8_t addr, uint32_t data) -{ - return tc_write(SHA1_ADDR_PREFIX, addr, data); -} - -int sha1_init(void) -{ - return tc_init(SHA1_ADDR_PREFIX); -} - -int sha1_next(void) -{ - return tc_next(SHA1_ADDR_PREFIX); -} - -int sha1_wait_ready(void) -{ - return tc_wait_ready(SHA1_ADDR_PREFIX); + return + tc_expected(COMM_ADDR_NAME0, comm_name0, 4) || + tc_expected(COMM_ADDR_NAME1, comm_name1, 4) || + tc_expected(COMM_ADDR_VERSION, comm_version, 4); } -int sha1_wait_valid(void) -{ - return tc_wait_valid(SHA1_ADDR_PREFIX); -} +/* ---------------- SHA-1 test cases ---------------- */ /* TC1: Read name and version from SHA-1 core. */ int TC1(void) { - uint32_t name0 = 0x73686131; /* "sha1" */ - uint32_t name1 = 0x20202020; /* " " */ - uint32_t version = 0x302e3530; /* "0.50" */ + uint8_t name0[4] = "sha1"; + uint8_t name1[4] = " "; + uint8_t version[4] = "0.50"; - printf("TC1: Reading name, type and version words from SHA-1 core.\n"); + if (!quiet) + printf("TC1: Reading name and version words from SHA-1 core.\n"); - return - sha1_read(ADDR_NAME0, name0) || - sha1_read(ADDR_NAME1, name1) || - sha1_read(ADDR_VERSION, version); + return + tc_expected(SHA1_ADDR_NAME0, name0, 4) || + tc_expected(SHA1_ADDR_NAME1, name1, 4) || + tc_expected(SHA1_ADDR_VERSION, version, 4); } /* TC2: SHA-1 Single block message test as specified by NIST. */ int TC2(void) { - const uint32_t *block = NIST_512_SINGLE; - const uint32_t *expected = SHA1_SINGLE_DIGEST; - int i; + const uint8_t *block = NIST_512_SINGLE; + const uint8_t *expected = SHA1_SINGLE_DIGEST; + int ret; - printf("TC2: Single block message test for SHA-1.\n"); + if (!quiet) + printf("TC2: Single block message test for SHA-1.\n"); /* Write block to SHA-1. */ - for (i = 0; i < SHA1_BLOCK_LEN; ++i) { - if (sha1_write(SHA1_ADDR_BLOCK + i, block[i]) != 0) - return 1; - } - + tc_write(SHA1_ADDR_BLOCK, block, SHA1_BLOCK_LEN); /* Start initial block hashing, wait and check status. */ - if ((sha1_init() != 0) || (sha1_wait_valid() != 0)) - return 1; - + tc_init(SHA1_ADDR_CTRL); + tc_wait_valid(SHA1_ADDR_STATUS); /* Extract the digest. */ - for (i = 0; i < SHA1_DIGEST_LEN; ++i) { - if (sha1_read(SHA1_ADDR_DIGEST + i, expected[i]) != 0) - return 1; - } - - return 0; + ret = tc_expected(SHA1_ADDR_DIGEST, expected, SHA1_DIGEST_LEN); + return ret; } /* TC3: SHA-1 Double block message test as specified by NIST. */ int TC3(void) { - const uint32_t *block[2] = { NIST_512_DOUBLE0, NIST_512_DOUBLE1 }; - static const uint32_t block0_expected[] = - { 0xF4286818, 0xC37B27AE, 0x0408F581, 0x84677148, 0x4A566572 }; - const uint32_t *expected = SHA1_DOUBLE_DIGEST; - int i; + const uint8_t *block[2] = { NIST_512_DOUBLE0, NIST_512_DOUBLE1 }; + static const uint8_t block0_expected[] = + { 0xF4, 0x28, 0x68, 0x18, 0xC3, 0x7B, 0x27, 0xAE, + 0x04, 0x08, 0xF5, 0x81, 0x84, 0x67, 0x71, 0x48, + 0x4A, 0x56, 0x65, 0x72 }; + const uint8_t *expected = SHA1_DOUBLE_DIGEST; + int ret; - printf("TC3: Double block message test for SHA-1.\n"); + if (!quiet) + printf("TC3: Double block message test for SHA-1.\n"); /* Write first block to SHA-1. */ - for (i = 0; i < SHA1_BLOCK_LEN; ++i) { - if (sha1_write(SHA1_ADDR_BLOCK + i, block[0][i]) != 0) - return 1; - } - + tc_write(SHA1_ADDR_BLOCK, block[0], SHA1_BLOCK_LEN); /* Start initial block hashing, wait and check status. */ - if ((sha1_init() != 0) || (sha1_wait_valid() != 0)) - return 1; - + tc_init(SHA1_ADDR_CTRL); + tc_wait_valid(SHA1_ADDR_STATUS); /* Extract the first digest. */ - for (i = 0; i < SHA1_DIGEST_LEN; ++i) { - if (sha1_read(SHA1_ADDR_DIGEST + i, block0_expected[i]) != 0) - return 1; - } - + tc_expected(SHA1_ADDR_DIGEST, block0_expected, SHA1_DIGEST_LEN); /* Write second block to SHA-1. */ - for (i = 0; i < SHA1_BLOCK_LEN; ++i) { - if (sha1_write(SHA1_ADDR_BLOCK + i, block[1][i]) != 0) - return 1; - } - + tc_write(SHA1_ADDR_BLOCK, block[1], SHA1_BLOCK_LEN); /* Start next block hashing, wait and check status. */ - if ((sha1_next() != 0) || (sha1_wait_valid() != 0)) - return 1; - + tc_next(SHA1_ADDR_CTRL); + tc_wait_valid(SHA1_ADDR_STATUS); /* Extract the second digest. */ - for (i = 0; i < SHA1_DIGEST_LEN; ++i) { - if (sha1_read(SHA1_ADDR_DIGEST + i, expected[i]) != 0) - return 1; - } - - return 0; + ret = tc_expected(SHA1_ADDR_DIGEST, expected, SHA1_DIGEST_LEN); + return ret; } /* ---------------- SHA-256 test cases ---------------- */ -int sha256_read(uint8_t addr, uint32_t data) -{ - return tc_read(SHA256_ADDR_PREFIX, addr, data); -} - -int sha256_write(uint8_t addr, uint32_t data) -{ - return tc_write(SHA256_ADDR_PREFIX, addr, data); -} - -int sha256_init(void) -{ - return tc_init(SHA256_ADDR_PREFIX); -} - -int sha256_next(void) -{ - return tc_next(SHA256_ADDR_PREFIX); -} - -int sha256_wait_ready(void) -{ - return tc_wait_ready(SHA256_ADDR_PREFIX); -} - -int sha256_wait_valid(void) -{ - return tc_wait_valid(SHA256_ADDR_PREFIX); -} - /* TC4: Read name and version from SHA-256 core. */ int TC4(void) { - uint32_t name0 = 0x73686132; /* "sha2" */ - uint32_t name1 = 0x2d323536; /* "-256" */ - uint32_t version = 0x302e3830; /* "0.80" */ + uint8_t name0[4] = "sha2"; + uint8_t name1[4] = "-256"; + uint8_t version[4] = "0.80"; - printf("TC4: Reading name, type and version words from SHA-256 core.\n"); + if (!quiet) + printf("TC4: Reading name, type and version words from SHA-256 core.\n"); return - sha256_read(ADDR_NAME0, name0) || - sha256_read(ADDR_NAME1, name1) || - sha256_read(ADDR_VERSION, version); + tc_expected(SHA256_ADDR_NAME0, name0, 4) || + tc_expected(SHA256_ADDR_NAME1, name1, 4) || + tc_expected(SHA256_ADDR_VERSION, version, 4); } /* TC5: SHA-256 Single block message test as specified by NIST. */ -int TC5(void) +int TC5() { - const uint32_t *block = NIST_512_SINGLE; - const uint32_t *expected = SHA256_SINGLE_DIGEST; - int i; + const uint8_t *block = NIST_512_SINGLE; + const uint8_t *expected = SHA256_SINGLE_DIGEST; - printf("TC5: Single block message test for SHA-256.\n"); + if (!quiet) + printf("TC5: Single block message test for SHA-256.\n"); - /* Write block to SHA-256. */ - for (i = 0; i < SHA256_BLOCK_LEN; ++i) { - if (sha256_write(SHA256_ADDR_BLOCK + i, block[i]) != 0) - return 1; - } - - /* Start initial block hashing, wait and check status. */ - if ((sha256_init() != 0) || (sha256_wait_valid() != 0)) - return 1; - - /* Extract the digest. */ - for (i = 0; i < SHA256_DIGEST_LEN; ++i) { - if (sha256_read(SHA256_ADDR_DIGEST + i, expected[i]) != 0) - return 1; - } - - - return 0; + return + /* Write block to SHA-256. */ + tc_write(SHA256_ADDR_BLOCK, block, SHA256_BLOCK_LEN) || + /* Start initial block hashing, wait and check status. */ + tc_init(SHA256_ADDR_CTRL) || + tc_wait_valid(SHA256_ADDR_STATUS) || + /* Extract the digest. */ + tc_expected(SHA256_ADDR_DIGEST, expected, SHA256_DIGEST_LEN); } -/* TC6: SHA-1 Double block message test as specified by NIST. */ -int TC6(void) +/* TC6: SHA-256 Double block message test as specified by NIST. */ +int TC6() { - const uint32_t *block[2] = { NIST_512_DOUBLE0, NIST_512_DOUBLE1 }; - static const uint32_t block0_expected[] = - { 0x85E655D6, 0x417A1795, 0x3363376A, 0x624CDE5C, - 0x76E09589, 0xCAC5F811, 0xCC4B32C1, 0xF20E533A }; - const uint32_t *expected = SHA256_DOUBLE_DIGEST; - int i; - - printf("TC6: Double block message test for SHA-256.\n"); - - /* Write first block to SHA-256. */ - for (i = 0; i < SHA256_BLOCK_LEN; ++i) { - if (sha256_write(SHA256_ADDR_BLOCK + i, block[0][i]) != 0) - return 1; - } - - /* Start initial block hashing, wait and check status. */ - if ((sha256_init() != 0) || (sha256_wait_valid() != 0)) - return 1; + const uint8_t *block[2] = { NIST_512_DOUBLE0, NIST_512_DOUBLE1 }; + static const uint8_t block0_expected[] = + { 0x85, 0xE6, 0x55, 0xD6, 0x41, 0x7A, 0x17, 0x95, + 0x33, 0x63, 0x37, 0x6A, 0x62, 0x4C, 0xDE, 0x5C, + 0x76, 0xE0, 0x95, 0x89, 0xCA, 0xC5, 0xF8, 0x11, + 0xCC, 0x4B, 0x32, 0xC1, 0xF2, 0x0E, 0x53, 0x3A }; + const uint8_t *expected = SHA256_DOUBLE_DIGEST; - /* Extract the first digest. */ - for (i = 0; i < SHA256_DIGEST_LEN; ++i) { - if (sha256_read(SHA256_ADDR_DIGEST + i, block0_expected[i]) != 0) - return 1; - } - - /* Write second block to SHA-256. */ - for (i = 0; i < SHA256_BLOCK_LEN; ++i) { - if (sha256_write(SHA256_ADDR_BLOCK + i, block[1][i]) != 0) - return 1; - } - - /* Start next block hashing, wait and check status. */ - if ((sha256_next() != 0) || (sha256_wait_valid() != 0)) - return 1; + if (!quiet) + printf("TC6: Double block message test for SHA-256.\n"); - /* Extract the second digest. */ - for (i = 0; i < SHA256_DIGEST_LEN; ++i) { - if (sha256_read(SHA256_ADDR_DIGEST + i, expected[i]) != 0) - return 1; - } - - return 0; + return + /* Write first block to SHA-256. */ + tc_write(SHA256_ADDR_BLOCK, block[0], SHA256_BLOCK_LEN) || + /* Start initial block hashing, wait and check status. */ + tc_init(SHA256_ADDR_CTRL) || + tc_wait_valid(SHA256_ADDR_STATUS) || + /* Extract the first digest. */ + tc_expected(SHA256_ADDR_DIGEST, block0_expected, SHA256_DIGEST_LEN) || + /* Write second block to SHA-256. */ + tc_write(SHA256_ADDR_BLOCK, block[1], SHA256_BLOCK_LEN) || + /* Start next block hashing, wait and check status. */ + tc_next(SHA256_ADDR_CTRL) || + tc_wait_valid(SHA256_ADDR_STATUS) || + /* Extract the second digest. */ + tc_expected(SHA256_ADDR_DIGEST, expected, SHA256_DIGEST_LEN); } /* TC7: SHA-256 Huge message test. */ -int TC7(void) -{ - static const uint32_t block[] = - { 0xaa55aa55, 0xdeadbeef, 0x55aa55aa, 0xf00ff00f, - 0xaa55aa55, 0xdeadbeef, 0x55aa55aa, 0xf00ff00f, - 0xaa55aa55, 0xdeadbeef, 0x55aa55aa, 0xf00ff00f, - 0xaa55aa55, 0xdeadbeef, 0x55aa55aa, 0xf00ff00f }; +int TC7() +{ + static const uint8_t block[] = + { 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef, + 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f, + 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef, + 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f, + 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef, + 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f, + 0xaa, 0x55, 0xaa, 0x55, 0xde, 0xad, 0xbe, 0xef, + 0x55, 0xaa, 0x55, 0xaa, 0xf0, 0x0f, 0xf0, 0x0f }; /* final digest after 1000 iterations */ - static const uint32_t expected[] = - { 0x7638f3bc, 0x500dd1a6, 0x586dd4d0, 0x1a1551af, - 0xd821d235, 0x2f919e28, 0xd5842fab, 0x03a40f2a }; + static const uint8_t expected[] = + { 0x76, 0x38, 0xf3, 0xbc, 0x50, 0x0d, 0xd1, 0xa6, + 0x58, 0x6d, 0xd4, 0xd0, 0x1a, 0x15, 0x51, 0xaf, + 0xd8, 0x21, 0xd2, 0x35, 0x2f, 0x91, 0x9e, 0x28, + 0xd5, 0x84, 0x2f, 0xab, 0x03, 0xa4, 0x0f, 0x2a }; int i, n = 1000; - printf("TC7: Message with %d blocks test for SHA-256.\n", n); + if (!quiet) + printf("TC7: Message with %d blocks test for SHA-256.\n", n); - /* Write first block to SHA-256. */ - for (i = 0; i < SHA256_BLOCK_LEN; ++i) { - if (sha256_write( SHA256_ADDR_BLOCK + i, block[i]) != 0) - return 1; - } + /* Write block data to SHA-256. */ + if (tc_write(SHA256_ADDR_BLOCK, block, SHA256_BLOCK_LEN)) + return 1; /* Start initial block hashing, wait and check status. */ - if ((sha256_init() != 0) || (sha256_wait_ready() != 0)) - return 1; + if (tc_init(SHA256_ADDR_CTRL) || + tc_wait_ready(SHA256_ADDR_STATUS)) + return 1; /* First block done. Do the rest. */ for (i = 1; i < n; ++i) { - /* Start next block hashing, wait and check status. */ - if ((sha256_next() != 0) || (sha256_wait_ready() != 0)) - return 1; + /* Start next block hashing, wait and check status. */ + if (tc_next(SHA256_ADDR_CTRL) || + tc_wait_ready(SHA256_ADDR_STATUS)) + return 1; } /* XXX valid is probably set at the same time as ready */ - if (sha256_wait_valid() != 0) - return 1; + if (tc_wait_valid(SHA256_ADDR_STATUS)) + return 1; /* Extract the final digest. */ - for (i = 0; i < SHA256_DIGEST_LEN; ++i) { - if (sha256_read(SHA256_ADDR_DIGEST + i, expected[i]) != 0) - return 1; - } - - return 0; + return tc_expected(SHA256_ADDR_DIGEST, expected, SHA256_DIGEST_LEN); } /* ---------------- SHA-512 test cases ---------------- */ -int sha512_read(uint8_t addr, uint32_t data) -{ - return tc_read(SHA512_ADDR_PREFIX, addr, data); -} - -int sha512_write(uint8_t addr, uint32_t data) -{ - return tc_write(SHA512_ADDR_PREFIX, addr, data); -} - -int sha512_init(uint8_t mode) -{ - return tc_write(SHA512_ADDR_PREFIX, ADDR_CTRL, - CTRL_INIT_CMD + (mode << SHA512_CTRL_MODE_LOW)); -} - -int sha512_next(uint8_t mode) -{ - return tc_write(SHA512_ADDR_PREFIX, ADDR_CTRL, - CTRL_NEXT_CMD + (mode << SHA512_CTRL_MODE_LOW)); -} - -int sha512_wait_ready(void) -{ - return tc_wait_ready(SHA512_ADDR_PREFIX); -} - -int sha512_wait_valid(void) -{ - return tc_wait_valid(SHA512_ADDR_PREFIX); -} - /* TC8: Read name and version from SHA-512 core. */ -int TC8(void) +int TC8() { - uint32_t name0 = 0x73686132; /* "sha2" */ - uint32_t name1 = 0x2d353132; /* "-512" */ - uint32_t version = 0x302e3830; /* "0.80" */ + uint8_t name0[4] = "sha2"; + uint8_t name1[4] = "-512"; + uint8_t version[4] = "0.80"; - printf("TC8: Reading name, type and version words from SHA-512 core.\n"); + if (!quiet) + printf("TC8: Reading name, type and version words from SHA-512 core.\n"); - return - sha512_read(ADDR_NAME0, name0) || - sha512_read(ADDR_NAME1, name1) || - sha512_read(ADDR_VERSION, version); + return + tc_expected(SHA512_ADDR_NAME0, name0, 4) || + tc_expected(SHA512_ADDR_NAME1, name1, 4) || + tc_expected(SHA512_ADDR_VERSION, version, 4); } /* TC9: SHA-512 Single block message test as specified by NIST. We do this for all modes. */ -int tc9(uint8_t mode, const uint32_t *expected, int len) +int tc9(int mode, const uint8_t *expected, int digest_len) { - const uint32_t *block = NIST_1024_SINGLE; - int i; - - /* Write block to SHA-512. */ - for (i = 0; i < SHA512_BLOCK_LEN; ++i) { - if (sha512_write(SHA512_ADDR_BLOCK + i, block[i]) != 0) - return 1; - } - - /* Start initial block hashing, wait and check status. */ - if ((sha512_init(mode) != 0) || (sha512_wait_valid() != 0)) - return 1; + const uint8_t *block = NIST_1024_SINGLE; + uint8_t init[4] = { 0, 0, 0, CTRL_INIT_CMD + mode }; - /* Extract the digest. */ - for (i = 0; i < len/4; ++i) { - if (sha512_read(SHA512_ADDR_DIGEST + i, expected[i]) != 0) - return 1; - } - - return 0; + return + /* Write block to SHA-512. */ + tc_write(SHA512_ADDR_BLOCK, block, SHA512_BLOCK_LEN) || + /* Start initial block hashing, wait and check status. */ + tc_write(SHA512_ADDR_CTRL, init, 4) || + tc_wait_valid(SHA512_ADDR_STATUS) || + /* Extract the digest. */ + tc_expected(SHA512_ADDR_DIGEST, expected, digest_len); } -int TC9(void) +int TC9() { - printf("TC9-1: Single block message test for SHA-512/224.\n"); - if (tc9(MODE_SHA_512_224, SHA512_224_SINGLE_DIGEST, - sizeof(SHA512_224_SINGLE_DIGEST)) != 0) - return 1; + if (!quiet) + printf("TC9-1: Single block message test for SHA-512/224.\n"); + if (tc9(MODE_SHA_512_224, SHA512_224_SINGLE_DIGEST, SHA512_224_DIGEST_LEN) != 0) + return 1; - printf("TC9-2: Single block message test for SHA-512/256.\n"); - if (tc9(MODE_SHA_512_256, SHA512_256_SINGLE_DIGEST, - sizeof(SHA512_256_SINGLE_DIGEST)) != 0) - return 1; + if (!quiet) + printf("TC9-2: Single block message test for SHA-512/256.\n"); + if (tc9(MODE_SHA_512_256, SHA512_256_SINGLE_DIGEST, SHA512_256_DIGEST_LEN) != 0) + return 1; - printf("TC9-3: Single block message test for SHA-384.\n"); - if (tc9(MODE_SHA_384, SHA384_SINGLE_DIGEST, - sizeof(SHA384_SINGLE_DIGEST)) != 0) - return 1; + if (!quiet) + printf("TC9-3: Single block message test for SHA-384.\n"); + if (tc9(MODE_SHA_384, SHA384_SINGLE_DIGEST, SHA384_DIGEST_LEN) != 0) + return 1; - printf("TC9-4: Single block message test for SHA-512.\n"); - if (tc9(MODE_SHA_512, SHA512_SINGLE_DIGEST, - sizeof(SHA512_SINGLE_DIGEST)) != 0) - return 1; + if (!quiet) + printf("TC9-4: Single block message test for SHA-512.\n"); + if (tc9(MODE_SHA_512, SHA512_SINGLE_DIGEST, SHA512_DIGEST_LEN) != 0) + return 1; return 0; } /* TC10: SHA-512 Double block message test as specified by NIST. We do this for all modes. */ -int tc10(uint8_t mode, const uint32_t *expected, int len) +int tc10(int mode, const uint8_t *expected, int digest_len) { - const uint32_t *block[2] = { NIST_1024_DOUBLE0, NIST_1024_DOUBLE1 }; - int i; - - /* Write first block to SHA-512. */ - for (i = 0; i < SHA512_BLOCK_LEN; ++i) { - if (sha512_write(SHA512_ADDR_BLOCK + i, block[0][i]) != 0) - return 1; - } - - /* Start initial block hashing, wait and check status. */ - if ((sha512_init(mode) != 0) || (sha512_wait_ready() != 0)) - return 1; - - /* Write second block to SHA-512. */ - for (i = 0; i < SHA512_BLOCK_LEN; ++i) { - if (sha512_write(SHA512_ADDR_BLOCK + i, block[1][i]) != 0) - return 1; - } - - /* Start next block hashing, wait and check status. */ - if ((sha512_next(mode) != 0) || (sha512_wait_valid() != 0)) - return 1; - - /* Extract the digest. */ - for (i = 0; i < len/4; ++i) { - if (sha512_read(SHA512_ADDR_DIGEST + i, expected[i]) != 0) - return 1; - } + const uint8_t *block[2] = { NIST_1024_DOUBLE0, NIST_1024_DOUBLE1 }; + uint8_t init[4] = { 0, 0, 0, CTRL_INIT_CMD + mode }; + uint8_t next[4] = { 0, 0, 0, CTRL_NEXT_CMD + mode }; - return 0; -} - -int TC10(void) -{ - printf("TC10-1: Double block message test for SHA-512/224.\n"); - if (tc10(MODE_SHA_512_224, SHA512_224_DOUBLE_DIGEST, - sizeof(SHA512_224_DOUBLE_DIGEST)) != 0) - return 1; - - printf("TC10-2: Double block message test for SHA-512/256.\n"); - if (tc10(MODE_SHA_512_256, SHA512_256_DOUBLE_DIGEST, - sizeof(SHA512_256_DOUBLE_DIGEST)) != 0) - return 1; - - printf("TC10-3: Double block message test for SHA-384.\n"); - if (tc10(MODE_SHA_384, SHA384_DOUBLE_DIGEST, - sizeof(SHA384_DOUBLE_DIGEST)) != 0) - return 1; - - printf("TC10-4: Double block message test for SHA-512.\n"); - if (tc10(MODE_SHA_512, SHA512_DOUBLE_DIGEST, - sizeof(SHA512_DOUBLE_DIGEST)) != 0) - return 1; + return + /* Write first block to SHA-512. */ + tc_write(SHA512_ADDR_BLOCK, block[0], SHA512_BLOCK_LEN) || + /* Start initial block hashing, wait and check status. */ + tc_write(SHA512_ADDR_CTRL, init, 4) || + tc_wait_ready(SHA512_ADDR_STATUS) || + /* Write second block to SHA-512. */ + tc_write(SHA512_ADDR_BLOCK, block[1], SHA512_BLOCK_LEN) || + /* Start next block hashing, wait and check status. */ + tc_write(SHA512_ADDR_CTRL, next, 4) || + tc_wait_valid(SHA512_ADDR_STATUS) || + /* Extract the digest. */ + tc_expected(SHA512_ADDR_DIGEST, expected, digest_len); +} + +int TC10() +{ + if (!quiet) + printf("TC10-1: Double block message test for SHA-512/224.\n"); + if (tc10(MODE_SHA_512_224, SHA512_224_DOUBLE_DIGEST, SHA512_224_DIGEST_LEN) != 0) + return 1; + + if (!quiet) + printf("TC10-2: Double block message test for SHA-512/256.\n"); + if (tc10(MODE_SHA_512_256, SHA512_256_DOUBLE_DIGEST, SHA512_256_DIGEST_LEN) != 0) + return 1; + + if (!quiet) + printf("TC10-3: Double block message test for SHA-384.\n"); + if (tc10(MODE_SHA_384, SHA384_DOUBLE_DIGEST, SHA384_DIGEST_LEN) != 0) + return 1; + + if (!quiet) + printf("TC10-4: Double block message test for SHA-512.\n"); + if (tc10(MODE_SHA_512, SHA512_DOUBLE_DIGEST, SHA512_DIGEST_LEN) != 0) + return 1; return 0; } @@ -952,79 +669,83 @@ int main(int argc, char *argv[]) tcfp sha256_tests[] = { TC4, TC5, TC6, TC7 }; tcfp sha512_tests[] = { TC8, TC9, TC10 }; - char *usage = "Usage: %s [-d] [-i I2C_device] [-a I2C_addr] tc...\n"; + char *usage = "Usage: %s [-h] [-d] [-q] [-i I2C_device] [-a I2C_addr] tc...\n"; char *dev = I2C_dev; int addr = I2C_addr; int i, j, opt; - while ((opt = getopt(argc, argv, "h?di:a:")) != -1) { - switch (opt) { - case 'h': - case '?': - printf(usage, argv[0]); - return 0; - case 'd': - debug = 1; - break; - case 'i': - dev = optarg; - break; - case 'a': - addr = (int)strtol(optarg, NULL, 0); - if ((addr < 0x03) || (addr > 0x77)) { - fprintf(stderr, "addr must be between 0x03 and 0x77\n"); - return 1; - } - break; - default: - fprintf(stderr, usage, argv[0]); - return 1; - } + while ((opt = getopt(argc, argv, "h?dqi:a:")) != -1) { + switch (opt) { + case 'h': + case '?': + printf(usage, argv[0]); + return 0; + case 'd': + debug = 1; + break; + case 'q': + quiet = 1; + break; + case 'i': + dev = optarg; + break; + case 'a': + addr = (int)strtol(optarg, NULL, 0); + if ((addr < 0x03) || (addr > 0x77)) { + fprintf(stderr, "addr must be between 0x03 and 0x77\n"); + return 1; + } + break; + default: + fprintf(stderr, usage, argv[0]); + return EXIT_FAILURE; + } } - if (i2c_setup(dev, addr) != 0) - return 1; + if (i2c_open(dev, addr) != 0) + return 1; /* no args == run all tests */ if (optind >= argc) { - for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) - if (all_tests[j]() != 0) - return 1; - return 0; + for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) + if (all_tests[j]() != 0) + return EXIT_FAILURE; + return EXIT_SUCCESS; } + /* run one or more tests (by number) or groups of tests (by name) */ for (i = optind; i < argc; ++i) { - if (strcmp(argv[i], "all") == 0) { - for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) - if (all_tests[j]() != 0) - return 1; - } - else if (strcmp(argv[i], "sha1") == 0) { - for (j = 0; j < sizeof(sha1_tests)/sizeof(sha1_tests[0]); ++j) - if (sha1_tests[j]() != 0) - return 1; - } - else if (strcmp(argv[i], "sha256") == 0) { - for (j = 0; j < sizeof(sha256_tests)/sizeof(sha256_tests[0]); ++j) - if (sha256_tests[j]() != 0) - return 1; - } - else if (strcmp(argv[i], "sha512") == 0) { - for (j = 0; j < sizeof(sha512_tests)/sizeof(sha512_tests[0]); ++j) - if (sha512_tests[j]() != 0) - return 1; - } - else if (isdigit(argv[i][0]) && - (((j = atoi(argv[i])) >= 0) && - (j < sizeof(all_tests)/sizeof(all_tests[0])))) { - if (all_tests[j]() != 0) - return 1; - } - else { - fprintf(stderr, "unknown test case %s\n", argv[i]); - return 1; - } + if (strcmp(argv[i], "all") == 0) { + for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) + if (all_tests[j]() != 0) + return EXIT_FAILURE; + } + else if (strcmp(argv[i], "sha1") == 0) { + for (j = 0; j < sizeof(sha1_tests)/sizeof(sha1_tests[0]); ++j) + if (sha1_tests[j]() != 0) + return EXIT_FAILURE; + } + else if (strcmp(argv[i], "sha256") == 0) { + for (j = 0; j < sizeof(sha256_tests)/sizeof(sha256_tests[0]); ++j) + if (sha256_tests[j]() != 0) + return EXIT_FAILURE; + } + else if (strcmp(argv[i], "sha512") == 0) { + for (j = 0; j < sizeof(sha512_tests)/sizeof(sha512_tests[0]); ++j) + if (sha512_tests[j]() != 0) + return EXIT_FAILURE; + } + else if (isdigit(argv[i][0]) && + (((j = atoi(argv[i])) >= 0) && + (j < sizeof(all_tests)/sizeof(all_tests[0])))) { + if (all_tests[j]() != 0) + return EXIT_FAILURE; + } + else { + fprintf(stderr, "unknown test case %s\n", argv[i]); + return EXIT_FAILURE; + } } - return 0; + return EXIT_SUCCESS; } diff --git a/i2c/sw/tc_i2c.c b/i2c/sw/tc_i2c.c new file mode 100644 index 0000000..da1ab14 --- /dev/null +++ b/i2c/sw/tc_i2c.c @@ -0,0 +1,297 @@ +/* + * tc_i2c.c + * -------- + * This module contains common code to talk to the FPGA over the I2C bus. + * + * Author: Paul Selkirk + * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of the NORDUnet nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <stdio.h> +#include <stdlib.h> +#include <fcntl.h> +#include <unistd.h> +#include <linux/i2c-dev.h> +#include <sys/ioctl.h> +#include <stdint.h> + +#include "tc_i2c.h" + +extern int debug; + +/* ---------------- I2C low-level code ---------------- */ + +static int i2cfd; + +static void dump(char *label, const uint8_t *buf, size_t len) +{ + if (debug) { + int i; + printf("%s [", label); + for (i = 0; i < len; ++i) + printf(" %02x", buf[i]); + printf(" ]\n"); + } +} + +static void i2c_close(void) +{ + close(i2cfd); +} + +int i2c_open(char *dev, int addr) +{ + i2cfd = open(dev, O_RDWR); + if (i2cfd < 0) { + fprintf(stderr, "Unable to open %s: ", dev); + perror(""); + i2cfd = 0; + return 1; + } + + if (ioctl(i2cfd, I2C_SLAVE, addr) < 0) { + fprintf(stderr, "Unable to set I2C slave device 0x%02x: ", addr); + perror(""); + return 1; + } + + if (atexit(i2c_close) != 0) { + fprintf(stderr, "Unable to set I2C atexit handler."); + return 1; + } + + return 0; +} + +static int i2c_write(const uint8_t *buf, size_t len) +{ + dump("write ", buf, len); + + if (write(i2cfd, buf, len) != len) { + perror("i2c write failed"); + return 1; + } + + return 0; +} + +static int i2c_read(uint8_t *b) +{ + /* read() on the i2c device only returns one byte at a time, + * and tc_get_resp() needs to parse the response one byte at a time + */ + if (read(i2cfd, b, 1) != 1) { + perror("i2c read failed"); + return 1; + } + + return 0; +} + +/* ---------------- test-case low-level code ---------------- */ + +/* coretest command codes */ +#define SOC 0x55 +#define EOC 0xaa +#define READ_CMD 0x10 +#define WRITE_CMD 0x11 +#define RESET_CMD 0x01 + +/* coretest response codes */ +#define SOR 0xaa +#define EOR 0x55 +#define READ_OK 0x7f +#define WRITE_OK 0x7e +#define RESET_OK 0x7d +#define UNKNOWN 0xfe +#define ERROR 0xfd + +static int tc_send_write_cmd(off_t offset, const uint8_t *data) +{ + uint8_t buf[9] = { SOC, WRITE_CMD, (offset >> 8) & 0xff, offset & 0xff, + data[0], data[1], data[2], data[3], EOC }; + + return i2c_write(buf, sizeof(buf)); +} + +static int tc_send_read_cmd(off_t offset) +{ + uint8_t buf[5] = { SOC, READ_CMD, (offset >> 8) & 0xff, offset & 0xff, EOC }; + + return i2c_write(buf, sizeof(buf)); +} + +static int tc_get_resp(uint8_t *buf, size_t len) +{ + int i; + + for (i = 0; i < len; ++i) { + if (i2c_read(&buf[i]) != 0) + return 1; + if ((i == 0) && (buf[i] != SOR)) { + /* we've gotten out of sync, and there's probably nothing we can do */ + fprintf(stderr, "response byte 0: expected 0x%02x (SOR), got 0x%02x\n", + SOR, buf[0]); + return 1; + } + else if (i == 1) { /* response code */ + switch (buf[i]) { + case READ_OK: + len = 9; + break; + case WRITE_OK: + len = 5; + break; + case RESET_OK: + len = 3; + break; + case ERROR: + case UNKNOWN: + len = 4; + break; + default: + /* we've gotten out of sync, and there's probably nothing we can do */ + fprintf(stderr, "unknown response code 0x%02x\n", buf[i]); + return 1; + } + } + } + + dump("read ", buf, len); + + return 0; +} + +static int tc_compare(uint8_t *buf, const uint8_t *expected, size_t len) +{ + int i; + + /* start at byte 1 because SOR has already been tested */ + for (i = 1; i < len; ++i) { + if (buf[i] != expected[i]) { + fprintf(stderr, "response byte %d: expected 0x%02x, got 0x%02x\n", + i, expected[i], buf[i]); + return 1; + } + } + + return 0; +} + +static int tc_get_write_resp(off_t offset) +{ + uint8_t buf[5]; + uint8_t expected[5] = { SOR, WRITE_OK, (offset >> 8) & 0xff, offset & 0xff, EOR }; + + return + tc_get_resp(buf, sizeof(buf)) || + tc_compare(buf, expected, sizeof(expected)); +} + +static int tc_get_read_resp(off_t offset, uint8_t *data) +{ + uint8_t buf[9]; + uint8_t expected[4] = { SOR, READ_OK, (offset >> 8) & 0xff, offset & 0xff }; + + if ((tc_get_resp(buf, sizeof(buf)) != 0) || + (tc_compare(buf, expected, 4) != 0) || buf[8] != EOR) + return 1; + + data[0] = buf[4]; + data[1] = buf[5]; + data[2] = buf[6]; + data[3] = buf[7]; + + return 0; +} + +static int tc_get_read_resp_expected(off_t offset, const uint8_t *data) +{ + uint8_t buf[9]; + uint8_t expected[9] = { SOR, READ_OK, (offset >> 8) & 0xff, offset & 0xff, + data[0], data[1], data[2], data[3], EOR }; + + dump("expect", expected, 9); + + return (tc_get_resp(buf, sizeof(buf)) || + tc_compare(buf, expected, sizeof(buf))); +} + +int tc_write(off_t offset, const uint8_t *buf, size_t len) +{ + for (; len > 0; offset++, buf += 4, len -= 4) { + if (tc_send_write_cmd(offset, buf) || + tc_get_write_resp(offset)) + return 1; + } + + return 0; +} + +int tc_read(off_t offset, uint8_t *buf, size_t len) +{ + for (; len > 0; offset++, buf += 4, len -= 4) { + if (tc_send_read_cmd(offset) || + tc_get_read_resp(offset, buf)) + return 1; + } + + return 0; +} + +int tc_expected(off_t offset, const uint8_t *buf, size_t len) +{ + for (; len > 0; offset++, buf += 4, len -= 4) { + if (tc_send_read_cmd(offset) || + tc_get_read_resp_expected(offset, buf)) + return 1; + } + + return 0; +} + +int tc_wait(off_t offset, uint8_t status, int *count) +{ + uint8_t buf[4]; + int i; + + for (i = 1; ; ++i) { + if (count && (*count > 0) && (i >= *count)) { + fprintf(stderr, "tc_wait timed out\n"); + return 1; + } + if (tc_read(offset, buf, 4) != 0) + return -1; + if (buf[3] & status) { + if (count) + *count = i; + return 0; + } + } +} diff --git a/i2c/sw/tc_i2c.h b/i2c/sw/tc_i2c.h new file mode 100644 index 0000000..f9648da --- /dev/null +++ b/i2c/sw/tc_i2c.h @@ -0,0 +1,47 @@ +/* + * tc_i2c.h + * -------- + * This module contains common code to talk to the FPGA over the I2C bus. + * + * Author: Paul Selkirk + * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of the NORDUnet nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* I2C configuration */ +#define I2C_dev "/dev/i2c-2" +#define I2C_addr 0x0f + +/* I2C public functions */ +int i2c_open(char *dev, int addr); + +/* test case public functions */ +int tc_write(off_t offset, const uint8_t *data, size_t len); +int tc_read(off_t offset, uint8_t *data, size_t len); +int tc_expected(off_t offset, const uint8_t *data, size_t len); +int tc_wait(off_t offset, uint8_t status, int *count); diff --git a/i2c/sw/trng_tester_i2c.c b/i2c/sw/trng_tester_i2c.c new file mode 100644 index 0000000..a38f7fa --- /dev/null +++ b/i2c/sw/trng_tester_i2c.c @@ -0,0 +1,421 @@ +/* + * trng_tester.c + * -------------- + * This program sends several commands to the TRNG subsystem + * in order to verify the avalanche_entropy, rosc_entropy, and csprng cores. + * + * Note: This version of the program talks to the FPGA over an I2C bus. + * + * + * Author: Paul Selkirk + * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of the NORDUnet nor the names of its contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <string.h> +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> +#include <time.h> +#include <stdint.h> +#include <ctype.h> + +#include "tc_i2c.h" + +#define WAIT_STATS /* report number of status reads before core says "ready" */ + +int debug = 0; +int quiet = 0; +int num_words = 10; + +/* memory segments for core families */ +#define SEGMENT_OFFSET_GLOBALS 0x0000 +#define SEGMENT_OFFSET_HASHES 0x2000 +#define SEGMENT_OFFSET_RNGS 0x4000 +#define SEGMENT_OFFSET_CIPHERS 0x6000 + +/* addresses and codes common to all cores */ +#define ADDR_NAME0 0x00 +#define ADDR_NAME1 0x01 +#define ADDR_VERSION 0x02 + +/* At segment 0, we have board-level register and communication channel registers */ +#define BOARD_ADDR_BASE SEGMENT_OFFSET_GLOBALS + 0x0000 +#define BOARD_ADDR_NAME0 BOARD_ADDR_BASE + ADDR_NAME0 +#define BOARD_ADDR_NAME1 BOARD_ADDR_BASE + ADDR_NAME1 +#define BOARD_ADDR_VERSION BOARD_ADDR_BASE + ADDR_VERSION +#define BOARD_ADDR_DUMMY BOARD_ADDR_BASE + 0xFF + +#define COMM_ADDR_BASE SEGMENT_OFFSET_GLOBALS + 0x0100 +#define COMM_ADDR_NAME0 COMM_ADDR_BASE + ADDR_NAME0 +#define COMM_ADDR_NAME1 COMM_ADDR_BASE + ADDR_NAME1 +#define COMM_ADDR_VERSION COMM_ADDR_BASE + ADDR_VERSION + +#define CORE_SIZE 0x100 + +/* addresses and codes for the TRNG cores */ +#define TRNG_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x00 * CORE_SIZE) +#define TRNG_ADDR_NAME0 TRNG_ADDR_BASE + ADDR_NAME0 +#define TRNG_ADDR_NAME1 TRNG_ADDR_BASE + ADDR_NAME1 +#define TRNG_ADDR_VERSION TRNG_ADDR_BASE + ADDR_VERSION +#define TRNG_ADDR_CTRL TRNG_ADDR_BASE + 0x10 +#define TRNG_CTRL_DISCARD 1 +#define TRNG_CTRL_TEST_MODE 2 +#define TRNG_ADDR_STATUS TRNG_ADDR_BASE + 0x11 +/* no status bits defined */ +#define TRNG_ADDR_DELAY TRNG_ADDR_BASE + 0x13 + +#define ENTROPY1_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x05 * CORE_SIZE) +#define ENTROPY1_ADDR_NAME0 ENTROPY1_ADDR_BASE + ADDR_NAME0 +#define ENTROPY1_ADDR_NAME1 ENTROPY1_ADDR_BASE + ADDR_NAME1 +#define ENTROPY1_ADDR_VERSION ENTROPY1_ADDR_BASE + ADDR_VERSION +#define ENTROPY1_ADDR_CTRL ENTROPY1_ADDR_BASE + 0x10 +#define ENTROPY1_CTRL_ENABLE 1 +#define ENTROPY1_ADDR_STATUS ENTROPY1_ADDR_BASE + 0x11 +#define ENTROPY1_STATUS_VALID 1 +#define ENTROPY1_ADDR_ENTROPY ENTROPY1_ADDR_BASE + 0x20 +#define ENTROPY1_ADDR_DELTA ENTROPY1_ADDR_BASE + 0x30 + +#define ENTROPY2_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x06 * CORE_SIZE) +#define ENTROPY2_ADDR_NAME0 ENTROPY2_ADDR_BASE + ADDR_NAME0 +#define ENTROPY2_ADDR_NAME1 ENTROPY2_ADDR_BASE + ADDR_NAME1 +#define ENTROPY2_ADDR_VERSION ENTROPY2_ADDR_BASE + ADDR_VERSION +#define ENTROPY2_ADDR_CTRL ENTROPY2_ADDR_BASE + 0x10 +#define ENTROPY2_CTRL_ENABLE 1 +#define ENTROPY2_ADDR_STATUS ENTROPY2_ADDR_BASE + 0x11 +#define ENTROPY2_STATUS_VALID 1 +#define ENTROPY2_ADDR_OPA ENTROPY2_ADDR_BASE + 0x18 +#define ENTROPY2_ADDR_OPB ENTROPY2_ADDR_BASE + 0x19 +#define ENTROPY2_ADDR_ENTROPY ENTROPY2_ADDR_BASE + 0x20 +#define ENTROPY2_ADDR_RAW ENTROPY2_ADDR_BASE + 0x21 +#define ENTROPY2_ADDR_ROSC ENTROPY2_ADDR_BASE + 0x22 + +#define MIXER_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x0a * CORE_SIZE) +#define MIXER_ADDR_NAME0 MIXER_ADDR_BASE + ADDR_NAME0 +#define MIXER_ADDR_NAME1 MIXER_ADDR_BASE + ADDR_NAME1 +#define MIXER_ADDR_VERSION MIXER_ADDR_BASE + ADDR_VERSION +#define MIXER_ADDR_CTRL MIXER_ADDR_BASE + 0x10 +#define MIXER_CTRL_ENABLE 1 +#define MIXER_CTRL_RESTART 2 +#define MIXER_ADDR_STATUS MIXER_ADDR_BASE + 0x11 +/* no status bits defined */ +#define MIXER_ADDR_TIMEOUT MIXER_ADDR_BASE + 0x20 + +#define CSPRNG_ADDR_BASE SEGMENT_OFFSET_RNGS + (0x0b * CORE_SIZE) +#define CSPRNG_ADDR_NAME0 CSPRNG_ADDR_BASE + ADDR_NAME0 +#define CSPRNG_ADDR_NAME1 CSPRNG_ADDR_BASE + ADDR_NAME1 +#define CSPRNG_ADDR_VERSION CSPRNG_ADDR_BASE + ADDR_VERSION +#define CSPRNG_ADDR_CTRL CSPRNG_ADDR_BASE + 0x10 +#define CSPRNG_CTRL_ENABLE 1 +#define CSPRNG_CTRL_SEED 2 +#define CSPRNG_ADDR_STATUS CSPRNG_ADDR_BASE + 0x11 +#define CSPRNG_STATUS_VALID 1 +#define CSPRNG_ADDR_RANDOM CSPRNG_ADDR_BASE + 0x20 +#define CSPRNG_ADDR_NROUNDS CSPRNG_ADDR_BASE + 0x40 +#define CSPRNG_ADDR_NBLOCKS_LO CSPRNG_ADDR_BASE + 0x41 +#define CSPRNG_ADDR_NBLOCKS_HI CSPRNG_ADDR_BASE + 0x42 + +/* ---------------- sanity test case ---------------- */ + +int TC0() +{ + uint8_t board_name0[4] = "PVT1"; + uint8_t board_name1[4] = " "; + uint8_t board_version[4] = "0.10"; + + uint8_t comm_name0[4] = "i2c "; + uint8_t comm_name1[4] = " "; + uint8_t comm_version[4] = "0.10"; + + uint8_t t[4]; + + if (!quiet) + printf("TC0-1: Reading board type, version, and dummy reg from global registers.\n"); + + /* write current time into dummy register, then try to read it back + * to make sure that we can actually write something into EIM + */ + (void)time((time_t *)t); + if (tc_write(BOARD_ADDR_DUMMY, t, 4) != 0) + return 1; + + if (tc_expected(BOARD_ADDR_NAME0, board_name0, 4) || + tc_expected(BOARD_ADDR_NAME1, board_name1, 4) || + tc_expected(BOARD_ADDR_VERSION, board_version, 4) || + tc_expected(BOARD_ADDR_DUMMY, t, 4)) + return 1; + + if (!quiet) + printf("TC0-2: Reading name and version words from communications core.\n"); + + return + tc_expected(COMM_ADDR_NAME0, comm_name0, 4) || + tc_expected(COMM_ADDR_NAME1, comm_name1, 4) || + tc_expected(COMM_ADDR_VERSION, comm_version, 4); +} + +/* ---------------- trng test cases ---------------- */ + +/* TC1: Read name and version from trng core. */ +int TC1(void) +{ + uint8_t name0[4] = "trng"; + uint8_t name1[4] = " "; + uint8_t version[4] = "0.01"; + + if (!quiet) + printf("TC1: Reading name and version words from trng core.\n"); + + return + tc_expected(TRNG_ADDR_NAME0, name0, 4) || + tc_expected(TRNG_ADDR_NAME1, name1, 4) || + tc_expected(TRNG_ADDR_VERSION, version, 4); +} + +/* XXX test cases for setting blinkenlights? */ +/* XXX set 'discard' control bit, see if we read the same value */ + +/* ---------------- avalanche_entropy test cases ---------------- */ + +/* TC2: Read name and version from avalanche_entropy core. */ +int TC2(void) +{ + uint8_t name0[4] = "extn"; + uint8_t name1[4] = "oise"; + uint8_t version[4] = "0.10"; + + if (!quiet) + printf("TC2: Reading name and version words from avalanche_entropy core.\n"); + + return + tc_expected(ENTROPY1_ADDR_NAME0, name0, 4) || + tc_expected(ENTROPY1_ADDR_NAME1, name1, 4) || + tc_expected(ENTROPY1_ADDR_VERSION, version, 4); +} + +/* XXX clear 'enable' control bit, see if we read the same value */ + +/* TC3: Read random data from avalanche_entropy. */ +int TC3(void) +{ + int i, n; + unsigned long entropy; + + if (!quiet) + printf("TC3: Read random data from avalanche_entropy.\n"); + + for (i = 0; i < num_words; ++i) { + /* check status */ + n = 10; + if (tc_wait(ENTROPY1_ADDR_STATUS, ENTROPY1_STATUS_VALID, &n) != 0) + return 1; + /* read entropy data */ + if (tc_read(ENTROPY1_ADDR_ENTROPY, (uint8_t *)&entropy, 4) != 0) + return 1; + /* display entropy data */ + if (!debug) +#ifdef WAIT_STATS + printf("%08lx %d\n", entropy, n); +#else + printf("%08lx\n", entropy); +#endif + } + + return 0; +} + +/* ---------------- rosc_entropy test cases ---------------- */ + +/* TC4: Read name and version from rosc_entropy core. */ +int TC4(void) +{ + uint8_t name0[4] = "rosc"; + uint8_t name1[4] = " ent"; + uint8_t version[4] = "0.10"; + + if (!quiet) + printf("TC4: Reading name and version words from rosc_entropy core.\n"); + + return + tc_expected(ENTROPY2_ADDR_NAME0, name0, 4) || + tc_expected(ENTROPY2_ADDR_NAME1, name1, 4) || + tc_expected(ENTROPY2_ADDR_VERSION, version, 4); +} + +/* XXX clear 'enable' control bit, see if we read the same value */ + +/* TC5: Read random data from rosc_entropy. */ +int TC5(void) +{ + int i, n; + unsigned long entropy; + + if (!quiet) + printf("TC5: Read random data from rosc_entropy.\n"); + + for (i = 0; i < num_words; ++i) { + /* check status */ + n = 10; + if (tc_wait(ENTROPY2_ADDR_STATUS, ENTROPY2_STATUS_VALID, &n) != 0) + return 1; + /* read entropy data */ + if (tc_read(ENTROPY2_ADDR_ENTROPY, (uint8_t *)&entropy, 4) != 0) + return 1; + /* display entropy data */ + if (!debug) +#ifdef WAIT_STATS + printf("%08lx %d\n", entropy, n); +#else + printf("%08lx\n", entropy); +#endif + } + + return 0; +} + +/* ---------------- trng_csprng test cases ---------------- */ + +/* TC6: Read name and version from trng_csprng core. */ +int TC6(void) +{ + /* XXX csprng core currently doesn't have name/version registers */ + return 0; +} + +/* XXX clear 'enable' control bit, see if we read the same value */ +/* XXX set 'seed' control bit, see if we read the same value */ + +/* TC7: Read random data from trng_csprng. */ +int TC7(void) +{ + int i, n; + unsigned long random; + + if (!quiet) + printf("TC7: Read random data from trng_csprng.\n"); + + for (i = 0; i < num_words; ++i) { + /* check status */ + n = 10; + if (tc_wait(CSPRNG_ADDR_STATUS, CSPRNG_STATUS_VALID, &n) != 0) + return 1; + /* read random data */ + if (tc_read(CSPRNG_ADDR_RANDOM, (uint8_t *)&random, 4) != 0) + return 1; + /* display random data */ + if (!debug) +#ifdef WAIT_STATS + printf("%08lx %d\n", random, n); +#else + printf("%08lx\n", random); +#endif + } + + return 0; +} + +/* ---------------- main ---------------- */ + +int main(int argc, char *argv[]) +{ + typedef int (*tcfp)(void); + tcfp all_tests[] = { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 }; + + char *usage = "Usage: %s [-h] [-d] [-q] [-n #] [-i I2C_device] [-a I2C_addr] tc...\n"; + char *dev = I2C_dev; + int addr = I2C_addr; + int i, j, opt; + + while ((opt = getopt(argc, argv, "h?dqn:i:a:")) != -1) { + switch (opt) { + case 'h': + case '?': + printf(usage, argv[0]); + return EXIT_SUCCESS; + case 'd': + debug = 1; + break; + case 'q': + quiet = 1; + break; + case 'n': + num_words = atoi(optarg); + if (num_words <= 0) { + fprintf(stderr, "-n requires a positive integer argument\n"); + return EXIT_FAILURE; + } + break; + case 'i': + dev = optarg; + break; + case 'a': + addr = (int)strtol(optarg, NULL, 0); + if ((addr < 0x03) || (addr > 0x77)) { + fprintf(stderr, "addr must be between 0x03 and 0x77\n"); + return 1; + } + break; + default: + fprintf(stderr, usage, argv[0]); + return EXIT_FAILURE; + } + } + + /* set up I2C */ + if (i2c_open(dev, addr) != 0) + return EXIT_FAILURE; + + /* no args == run all tests */ + if (optind >= argc) { + for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) + if (all_tests[j]() != 0) + return EXIT_FAILURE; + return EXIT_SUCCESS; + } + + /* run one or more tests (by number) or groups of tests (by name) */ + for (i = optind; i < argc; ++i) { + if (strcmp(argv[i], "all") == 0) { + for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j) + if (all_tests[j]() != 0) + return EXIT_FAILURE; + } + else if (isdigit(argv[i][0]) && + (((j = atoi(argv[i])) >= 0) && + (j < sizeof(all_tests)/sizeof(all_tests[0])))) { + if (all_tests[j]() != 0) + return EXIT_FAILURE; + } + else { + fprintf(stderr, "unknown test case %s\n", argv[i]); + return EXIT_FAILURE; + } + } + + return EXIT_SUCCESS; +} |