integrate trng into core_selector framework

5 files changed, 673 insertions, 40 deletions

diff --git a/eim/build/Makefile b/eim/build/Makefile
index c89d4ec..b677364 100644
--- a/eim/build/Makefile
+++ b/eim/build/Makefile
@@ -35,6 +35,18 @@ vfiles = \
 	../../../../hash/sha512/src/rtl/sha512_core.v \
 	../../../../hash/sha512/src/rtl/sha512_h_constants.v \
 	../../../../hash/sha512/src/rtl/sha512_k_constants.v \
-	../../../../hash/sha512/src/rtl/sha512_w_mem.v
+	../../../../hash/sha512/src/rtl/sha512_w_mem.v \
+	../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy.v \
+	../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v \
+	../../../../rng/rosc_entropy/src/rtl/rosc.v \
+	../../../../rng/rosc_entropy/src/rtl/rosc_entropy.v \
+	../../../../rng/rosc_entropy/src/rtl/rosc_entropy_core.v \
+	../../../../rng/trng/src/rtl/trng.v \
+	../../../../rng/trng/src/rtl/trng_csprng.v \
+	../../../../rng/trng/src/rtl/trng_csprng_fifo.v \
+	../../../../rng/trng/src/rtl/trng_mixer.v \
+	../../../../cipher/chacha/src/rtl/chacha.v \
+	../../../../cipher/chacha/src/rtl/chacha_core.v \
+	../../../../cipher/chacha/src/rtl/chacha_qr.v
 
 include xilinx.mk
diff --git a/eim/iseconfig/novena_eim.xise b/eim/iseconfig/novena_eim.xise
index 0633e22..b22ae9f 100644
--- a/eim/iseconfig/novena_eim.xise
+++ b/eim/iseconfig/novena_eim.xise
@@ -17,119 +17,163 @@
   <files>
     <file xil_pn:name="../rtl/novena_eim.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
     </file>
     <file xil_pn:name="../rtl/novena_regs.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
     </file>
     <file xil_pn:name="../../common/rtl/novena_clkmgr.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
     </file>
     <file xil_pn:name="../../common/rtl/ipcore/clkmgr_dcm.xco" xil_pn:type="FILE_COREGEN">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
     </file>
     <file xil_pn:name="../../../common/core_selector/src/rtl/core_selector.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
     </file>
     <file xil_pn:name="../../../common/core_selector/src/rtl/global_selector.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
     </file>
     <file xil_pn:name="../../../common/core_selector/src/rtl/cipher_selector.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
     </file>
     <file xil_pn:name="../../../common/core_selector/src/rtl/hash_selector.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
     </file>
     <file xil_pn:name="../../../common/core_selector/src/rtl/rng_selector.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
     </file>
     <file xil_pn:name="../../../../comm/eim/src/rtl/cdc_bus_pulse.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
     </file>
     <file xil_pn:name="../../../../comm/eim/src/rtl/eim_arbiter_cdc.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
     </file>
     <file xil_pn:name="../../../../comm/eim/src/rtl/eim_arbiter.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
     </file>
     <file xil_pn:name="../../../../comm/eim/src/rtl/eim_da_phy.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
     </file>
     <file xil_pn:name="../../../../comm/eim/src/rtl/eim_indicator.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
     </file>
     <file xil_pn:name="../../../../comm/eim/src/rtl/eim.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
     </file>
     <file xil_pn:name="../../../../hash/sha1/src/rtl/sha1_core.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
     </file>
     <file xil_pn:name="../../../../hash/sha1/src/rtl/sha1_w_mem.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="../../../../hash/sha1/src/rtl/sha1.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
     </file>
     <file xil_pn:name="../../../../hash/sha256/src/rtl/sha256_core.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
     </file>
     <file xil_pn:name="../../../../hash/sha256/src/rtl/sha256_k_constants.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="../../../../hash/sha256/src/rtl/sha256_w_mem.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="../../../../hash/sha256/src/rtl/sha256.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
     </file>
     <file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_core.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_h_constants.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_k_constants.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="../../../../hash/sha512/src/rtl/sha512_w_mem.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="../../../../hash/sha512/src/rtl/sha512.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
     </file>
     <file xil_pn:name="../ucf/novena_eim.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="../../../../comm/eim/src/rtl/eim_regs.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
+    </file>
+    <file xil_pn:name="../../../../rng/trng/src/rtl/trng.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+    </file>
+    <file xil_pn:name="../../../../rng/trng/src/rtl/trng_mixer.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+    </file>
+    <file xil_pn:name="../../../../rng/trng/src/rtl/trng_csprng.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
+    <file xil_pn:name="../../../../rng/trng/src/rtl/trng_csprng_fifo.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+    </file>
+    <file xil_pn:name="../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+    </file>
+    <file xil_pn:name="../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+    </file>
+    <file xil_pn:name="../../../../rng/rosc_entropy/src/rtl/rosc_entropy_core.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+    </file>
+    <file xil_pn:name="../../../../rng/rosc_entropy/src/rtl/rosc_entropy.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+    </file>
+    <file xil_pn:name="../../../../rng/rosc_entropy/src/rtl/rosc.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="../../../../cipher/chacha/src/rtl/chacha_core.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+    </file>
+    <file xil_pn:name="../../../../cipher/chacha/src/rtl/chacha_qr.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+    </file>
     <file xil_pn:name="../../common/rtl/ipcore/clkmgr_dcm.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
diff --git a/eim/rtl/novena_eim.v b/eim/rtl/novena_eim.v
index fbff86c..d2b11ed 100644
--- a/eim/rtl/novena_eim.v
+++ b/eim/rtl/novena_eim.v
@@ -146,22 +146,17 @@ module novena_top
       .sys_clk(sys_clk),
       .sys_rst(sys_rst),
 
+      .noise(ct_noise),
+
       .sys_eim_addr(sys_eim_addr),
       .sys_eim_wr(sys_eim_wr),
       .sys_eim_rd(sys_eim_rd),
 
       .sys_write_data(sys_eim_dout),
-      .sys_read_data(sys_eim_din)
-      );  
+      .sys_read_data(sys_eim_din),
 
-
-   //----------------------------------------------------------------
-   // Cryptech Logic
-   //
-   // Logic specific to the Cryptech use of the Novena.
-   // Currently we just hard wire the LED outputs.
-   //----------------------------------------------------------------
-   assign ct_led = {8{ct_noise}};
+      .debug(ct_led)
+      );  
 
 
    //----------------------------------------------------------------
diff --git a/eim/sw/Makefile b/eim/sw/Makefile
index 9d28af7..87cd78f 100755
--- a/eim/sw/Makefile
+++ b/eim/sw/Makefile
@@ -1,4 +1,4 @@
-all: hash_tester_eim
+all: hash_tester_eim trng_tester_eim
 
 .c.o:
 	gcc -c -Wall -o $@ $<
@@ -8,7 +8,12 @@ hash_tester_eim: hash_tester_eim.o novena-eim.o
 
 hash_tester_eim.o: hash_tester_eim.c novena-eim.h
 
+trng_tester_eim: trng_tester_eim.o novena-eim.o
+	gcc -o $@ $^
+
+trng_tester_eim.o: trng_tester_eim.c novena-eim.h
+
 novena-eim.o: novena-eim.c novena-eim.h
 
 clean:
-	rm -f *.o hash_tester_eim
+	rm -f *.o hash_tester_eim trng_tester_eim
diff --git a/eim/sw/trng_tester_eim.c b/eim/sw/trng_tester_eim.c
new file mode 100644
index 0000000..7c452b0
--- /dev/null
+++ b/eim/sw/trng_tester_eim.c
@@ -0,0 +1,577 @@
+/* 
+ * trng_tester.c
+ * --------------
+ * This program sends several commands to the TRNG subsystem
+ * in order to verify the avalanche_entropy, rosc_entropy, and csprng cores.
+ *
+ * Note: This version of the program talks to the FPGA over an EIM bus.
+ *
+ * 
+ * Author: Paul Selkirk
+ * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * - Redistributions of source code must retain the above copyright notice,
+ *   this list of conditions and the following disclaimer.
+ *
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ * - Neither the name of the NORDUnet nor the names of its contributors may
+ *   be used to endorse or promote products derived from this software
+ *   without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <string.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <sys/mman.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <time.h>
+#include <sys/time.h>
+#include <sys/ioctl.h>
+#include <arpa/inet.h>
+#include <ctype.h>
+#include <signal.h>
+
+#include "novena-eim.h"
+
+#define WAIT_STATS      /* report number of status reads before core says "ready" */
+
+int debug = 0;
+int quiet = 0;
+int repeat = 0;
+int num_words = 10;
+
+#define SEGMENT_OFFSET_GLOBALS  EIM_BASE_ADDR + 0x000000
+#define SEGMENT_OFFSET_HASHES   EIM_BASE_ADDR + 0x010000
+#define SEGMENT_OFFSET_RNGS     EIM_BASE_ADDR + 0x020000
+#define SEGMENT_OFFSET_CIPHERS  EIM_BASE_ADDR + 0x030000
+
+/* addresses and codes common to all cores */
+#define ADDR_NAME0              (0x0 << 2)
+#define ADDR_NAME1              (0x1 << 2)
+#define ADDR_VERSION            (0x2 << 2)
+
+/* At segment 0, we have board-level register and communication channel registers */
+#define BOARD_ADDR_BASE         SEGMENT_OFFSET_GLOBALS + 0x0000
+#define BOARD_ADDR_NAME0        BOARD_ADDR_BASE + ADDR_NAME0
+#define BOARD_ADDR_NAME1        BOARD_ADDR_BASE + ADDR_NAME1
+#define BOARD_ADDR_VERSION      BOARD_ADDR_BASE + ADDR_VERSION
+#define BOARD_ADDR_DUMMY        BOARD_ADDR_BASE + (0xFF << 2)
+
+#define COMM_ADDR_BASE          SEGMENT_OFFSET_GLOBALS + 0x0400
+#define COMM_ADDR_NAME0         COMM_ADDR_BASE + ADDR_NAME0
+#define COMM_ADDR_NAME1         COMM_ADDR_BASE + ADDR_NAME1
+#define COMM_ADDR_VERSION       COMM_ADDR_BASE + ADDR_VERSION
+
+#define CORE_SIZE               (0x100 << 2)
+
+/* addresses and codes for the TRNG cores */
+#define TRNG_ADDR_BASE          SEGMENT_OFFSET_RNGS + (0 * CORE_SIZE)
+#define TRNG_ADDR_NAME0         TRNG_ADDR_BASE + ADDR_NAME0
+#define TRNG_ADDR_NAME1         TRNG_ADDR_BASE + ADDR_NAME1
+#define TRNG_ADDR_VERSION       TRNG_ADDR_BASE + ADDR_VERSION
+#define TRNG_ADDR_CTRL          TRNG_ADDR_BASE + (0x10 << 2)
+#define TRNG_CTRL_DISCARD       1
+#define TRNG_CTRL_TEST_MODE     2
+#define TRNG_ADDR_STATUS        TRNG_ADDR_BASE + (0x11 << 2)
+/* no status bits defined */
+#define TRNG_ADDR_DELAY         TRNG_ADDR_BASE + (0x13 << 2)
+
+#define ENTROPY1_ADDR_BASE      SEGMENT_OFFSET_RNGS + (5 * CORE_SIZE)
+#define ENTROPY1_ADDR_NAME0     ENTROPY1_ADDR_BASE + ADDR_NAME0
+#define ENTROPY1_ADDR_NAME1     ENTROPY1_ADDR_BASE + ADDR_NAME1
+#define ENTROPY1_ADDR_VERSION   ENTROPY1_ADDR_BASE + ADDR_VERSION
+#define ENTROPY1_ADDR_CTRL      ENTROPY1_ADDR_BASE + (0x10 << 2)
+#define ENTROPY1_CTRL_ENABLE    1
+#define ENTROPY1_ADDR_STATUS    ENTROPY1_ADDR_BASE + (0x11 << 2)
+#define ENTROPY1_STATUS_VALID   1
+#define ENTROPY1_ADDR_ENTROPY   ENTROPY1_ADDR_BASE + (0x20 << 2)
+#define ENTROPY1_ADDR_DELTA     ENTROPY1_ADDR_BASE + (0x30 << 2)
+
+#define ENTROPY2_ADDR_BASE      SEGMENT_OFFSET_RNGS + (6 * CORE_SIZE)
+#define ENTROPY2_ADDR_NAME0     ENTROPY2_ADDR_BASE + ADDR_NAME0
+#define ENTROPY2_ADDR_NAME1     ENTROPY2_ADDR_BASE + ADDR_NAME1
+#define ENTROPY2_ADDR_VERSION   ENTROPY2_ADDR_BASE + ADDR_VERSION
+#define ENTROPY2_ADDR_CTRL      ENTROPY2_ADDR_BASE + (0x10 << 2)
+#define ENTROPY2_CTRL_ENABLE    1
+#define ENTROPY2_ADDR_STATUS    ENTROPY2_ADDR_BASE + (0x11 << 2)
+#define ENTROPY2_STATUS_VALID   1
+#define ENTROPY2_ADDR_OPA       ENTROPY2_ADDR_BASE + (0x18 << 2)
+#define ENTROPY2_ADDR_OPB       ENTROPY2_ADDR_BASE + (0x19 << 2)
+#define ENTROPY2_ADDR_ENTROPY   ENTROPY2_ADDR_BASE + (0x20 << 2)
+#define ENTROPY2_ADDR_RAW       ENTROPY2_ADDR_BASE + (0x21 << 2)
+#define ENTROPY2_ADDR_ROSC      ENTROPY2_ADDR_BASE + (0x22 << 2)
+
+#define MIXER_ADDR_BASE         SEGMENT_OFFSET_RNGS + (0x0a * CORE_SIZE)
+#define MIXER_ADDR_NAME0        MIXER_ADDR_BASE + ADDR_NAME0
+#define MIXER_ADDR_NAME1        MIXER_ADDR_BASE + ADDR_NAME1
+#define MIXER_ADDR_VERSION      MIXER_ADDR_BASE + ADDR_VERSION
+#define MIXER_ADDR_CTRL         MIXER_ADDR_BASE + (0x10 << 2)
+#define MIXER_CTRL_ENABLE       1
+#define MIXER_CTRL_RESTART      2
+#define MIXER_ADDR_STATUS       MIXER_ADDR_BASE + (0x11 << 2)
+/* no status bits defined */
+#define MIXER_ADDR_TIMEOUT      MIXER_ADDR_BASE + (0x20 << 2)
+
+#define CSPRNG_ADDR_BASE        SEGMENT_OFFSET_RNGS + (0x0b * CORE_SIZE)
+#define CSPRNG_ADDR_NAME0       CSPRNG_ADDR_BASE + ADDR_NAME0
+#define CSPRNG_ADDR_NAME1       CSPRNG_ADDR_BASE + ADDR_NAME1
+#define CSPRNG_ADDR_VERSION     CSPRNG_ADDR_BASE + ADDR_VERSION
+#define CSPRNG_ADDR_CTRL        CSPRNG_ADDR_BASE + (0x10 << 2)
+#define CSPRNG_CTRL_ENABLE      1
+#define CSPRNG_CTRL_SEED        2
+#define CSPRNG_ADDR_STATUS      CSPRNG_ADDR_BASE + (0x11 << 2)
+#define CSPRNG_STATUS_VALID     1
+#define CSPRNG_ADDR_RANDOM      CSPRNG_ADDR_BASE + (0x20 << 2)
+#define CSPRNG_ADDR_NROUNDS     CSPRNG_ADDR_BASE + (0x40 << 2)
+#define CSPRNG_ADDR_NBLOCKS_LO  CSPRNG_ADDR_BASE + (0x41 << 2)
+#define CSPRNG_ADDR_NBLOCKS_HI  CSPRNG_ADDR_BASE + (0x42 << 2)
+
+/* ---------------- test-case low-level code ---------------- */
+
+void dump(char *label, const uint8_t *buf, int len)
+{
+    if (debug) {
+        int i;
+        printf("%s [", label);
+        for (i = 0; i < len; ++i)
+            printf(" %02x", buf[i]);
+        printf(" ]\n");
+    }
+}
+
+int tc_write(off_t offset, const uint8_t *buf, int len)
+{
+    dump("write ", buf, len);
+
+    for (; len > 0; offset += 4, buf += 4, len -= 4) {
+        uint32_t val;
+        val = htonl(*(uint32_t *)buf);
+        eim_write_32(offset, &val);
+    }
+
+    return 0;
+}
+
+int tc_read(off_t offset, uint8_t *buf, int len)
+{
+    uint8_t *rbuf = buf;
+    int rlen = len;
+
+    for (; rlen > 0; offset += 4, rbuf += 4, rlen -= 4) {
+        uint32_t val;
+        eim_read_32(offset, &val);
+        *(uint32_t *)rbuf = ntohl(val);
+    }
+
+    dump("read  ", buf, len);
+
+    return 0;
+}
+
+int tc_expected(off_t offset, const uint8_t *expected, int len)
+{
+    uint8_t *buf;
+    int i;
+
+    buf = malloc(len);
+    if (buf == NULL) {
+        perror("malloc");
+        return 1;
+    }
+    dump("expect", expected, len);
+
+    if (tc_read(offset, buf, len) != 0)
+        goto errout;
+
+    for (i = 0; i < len; ++i)
+        if (buf[i] != expected[i]) {
+            fprintf(stderr, "response byte %d: expected 0x%02x, got 0x%02x\n",
+                    i, expected[i], buf[i]);
+            goto errout;
+        }
+
+    free(buf);
+    return 0;
+errout:
+    free(buf);
+    return 1;
+}
+
+#ifdef WAIT_STATS
+int tc_wait(off_t offset, uint8_t status)
+{
+    uint8_t buf[4];
+    int i;
+
+    for (i = 1; ; ++i) {
+        if (tc_read(offset, buf, 4) != 0)
+            return -1;
+        if (buf[3] & status)
+            return i;
+    }
+}
+#else
+int tc_wait(off_t offset, uint8_t status)
+{
+    uint8_t buf[4];
+    do {
+        if (tc_read(offset, buf, 4) != 0)
+            return 1;
+    } while (!(buf[3] & status));
+
+    return 0;
+}
+#endif
+
+/* ---------------- sanity test case ---------------- */
+
+int TC0()
+{
+    uint8_t board_name0[4]      = "PVT1";
+    uint8_t board_name1[4]      = "    ";
+    uint8_t board_version[4]    = "0.10";
+
+    uint8_t comm_name0[4]       = "eim ";
+    uint8_t comm_name1[4]       = "    ";
+    uint8_t comm_version[4]     = "0.10";
+
+    uint8_t t[4];
+
+    if (!quiet)
+        printf("TC0-1: Reading board type, version, and dummy reg from global registers.\n");
+
+    /* write current time into dummy register, then try to read it back
+     * to make sure that we can actually write something into EIM
+     */
+    (void)time((time_t *)t);
+    tc_write(BOARD_ADDR_DUMMY, (void *)&t, 4);
+
+    if (tc_expected(BOARD_ADDR_NAME0,   board_name0,   4) ||
+        tc_expected(BOARD_ADDR_NAME1,   board_name1,   4) ||
+        tc_expected(BOARD_ADDR_VERSION, board_version, 4) ||
+        tc_expected(BOARD_ADDR_DUMMY,   (void *)t,     4))
+        return 1;
+
+    if (!quiet)
+        printf("TC0-2: Reading name and version words from communications core.\n");
+
+    return
+        tc_expected(COMM_ADDR_NAME0,    comm_name0,   4) ||
+        tc_expected(COMM_ADDR_NAME1,    comm_name1,   4) ||
+        tc_expected(COMM_ADDR_VERSION,  comm_version, 4);
+}
+
+/* ---------------- trng test cases ---------------- */
+
+/* TC1: Read name and version from trng core. */
+int TC1(void)
+{
+    uint8_t name0[4]   = "trng";
+    uint8_t name1[4]   = "    ";
+    uint8_t version[4] = "0.01";
+
+    if (!quiet)
+        printf("TC1: Reading name and version words from trng core.\n");
+
+    return
+        tc_expected(TRNG_ADDR_NAME0, name0, 4) ||
+        tc_expected(TRNG_ADDR_NAME1, name1, 4) ||
+        tc_expected(TRNG_ADDR_VERSION, version, 4);
+}
+
+/* XXX test cases for setting blinkenlights? */
+/* XXX set 'discard' control bit, see if we read the same value */
+
+/* ---------------- avalanche_entropy test cases ---------------- */
+
+/* TC2: Read name and version from avalanche_entropy core. */
+int TC2(void)
+{
+    uint8_t name0[4]   = "extn";
+    uint8_t name1[4]   = "oise";
+    uint8_t version[4] = "0.10";
+
+    if (!quiet)
+        printf("TC2: Reading name and version words from avalanche_entropy core.\n");
+
+    return
+        tc_expected(ENTROPY1_ADDR_NAME0, name0, 4) ||
+        tc_expected(ENTROPY1_ADDR_NAME1, name1, 4) ||
+        tc_expected(ENTROPY1_ADDR_VERSION, version, 4);
+}
+
+/* XXX clear 'enable' control bit, see if we read the same value */
+
+/* TC3: Read random data from avalanche_entropy. */
+int TC3(void)
+{
+    int i;
+#ifdef WAIT_STATS
+    int n;
+#endif
+    unsigned long entropy;
+
+    if (!quiet)
+        printf("TC3: Read random data from avalanche_entropy.\n");
+
+    for (i = 0; i < num_words; ++i) {
+        /* check status */
+#ifdef WAIT_STATS
+        if ((n = tc_wait(ENTROPY1_ADDR_STATUS, ENTROPY1_STATUS_VALID)) < 0)
+#else
+        if (tc_wait(ENTROPY1_ADDR_STATUS, ENTROPY1_STATUS_VALID) != 0)
+#endif
+            return 1;
+        /* read entropy data */
+        if (tc_read(ENTROPY1_ADDR_ENTROPY, (uint8_t *)&entropy, 4) != 0)
+            return 1;
+        /* display entropy data */
+        if (!debug)
+#ifdef WAIT_STATS
+            printf("%08lx %d\n", entropy, n);
+#else
+            printf("%08lx\n", entropy);
+#endif
+    }
+
+    return 0;
+}
+
+/* ---------------- rosc_entropy test cases ---------------- */
+
+/* TC4: Read name and version from rosc_entropy core. */
+int TC4(void)
+{
+    uint8_t name0[4]   = "rosc";
+    uint8_t name1[4]   = " ent";
+    uint8_t version[4] = "0.10";
+
+    if (!quiet)
+        printf("TC4: Reading name and version words from rosc_entropy core.\n");
+
+    return
+        tc_expected(ENTROPY2_ADDR_NAME0, name0, 4) ||
+        tc_expected(ENTROPY2_ADDR_NAME1, name1, 4) ||
+        tc_expected(ENTROPY2_ADDR_VERSION, version, 4);
+}
+
+/* XXX clear 'enable' control bit, see if we read the same value */
+
+/* TC5: Read random data from rosc_entropy. */
+int TC5(void)
+{
+    int i;
+#ifdef WAIT_STATS
+    int n;
+#endif
+    unsigned long entropy;
+
+    if (!quiet)
+        printf("TC5: Read random data from rosc_entropy.\n");
+
+    for (i = 0; i < num_words; ++i) {
+        /* check status */
+#ifdef WAIT_STATS
+        if ((n = tc_wait(ENTROPY2_ADDR_STATUS, ENTROPY2_STATUS_VALID)) < 0)
+#else
+        if (tc_wait(ENTROPY2_ADDR_STATUS, ENTROPY2_STATUS_VALID) != 0)
+#endif
+            return 1;
+        /* read entropy data */
+        if (tc_read(ENTROPY2_ADDR_ENTROPY, (uint8_t *)&entropy, 4) != 0)
+            return 1;
+        /* display entropy data */
+        if (!debug)
+#ifdef WAIT_STATS
+            printf("%08lx %d\n", entropy, n);
+#else
+            printf("%08lx\n", entropy);
+#endif
+    }
+
+    return 0;
+}
+
+/* ---------------- trng_csprng test cases ---------------- */
+
+/* TC6: Read name and version from trng_csprng core. */
+int TC6(void)
+{
+    /* XXX csprng core currently doesn't have name/version registers */
+    return 0;
+}
+
+/* XXX clear 'enable' control bit, see if we read the same value */
+/* XXX set 'seed' control bit, see if we read the same value */
+
+/* TC7: Read random data from trng_csprng. */
+int TC7(void)
+{
+    int i;
+#ifdef WAIT_STATS
+    int n;
+#endif
+    unsigned long random;
+
+    if (!quiet)
+        printf("TC7: Read random data from trng_csprng.\n");
+
+    for (i = 0; i < num_words; ++i) {
+        /* check status */
+#ifdef WAIT_STATS
+        if ((n = tc_wait(CSPRNG_ADDR_STATUS, CSPRNG_STATUS_VALID)) < 0)
+#else
+        if (tc_wait(CSPRNG_ADDR_STATUS, CSPRNG_STATUS_VALID) != 0)
+#endif
+            return 1;
+        /* read random data */
+        if (tc_read(CSPRNG_ADDR_RANDOM, (uint8_t *)&random, 4) != 0)
+            return 1;
+        /* display random data */
+        if (!debug)
+#ifdef WAIT_STATS
+            printf("%08lx %d\n", random, n);
+#else
+            printf("%08lx\n", random);
+#endif
+    }
+
+    return 0;
+}
+
+/* ---------------- main ---------------- */
+
+/* signal handler for ctrl-c to end repeat testing */
+unsigned long iter = 0;
+struct timeval tv_start, tv_end;
+void sighandler(int unused)
+{
+    double tv_diff;
+
+    gettimeofday(&tv_end, NULL);
+    tv_diff = (double)(tv_end.tv_sec - tv_start.tv_sec) +
+        (double)(tv_end.tv_usec - tv_start.tv_usec)/1000000;
+    printf("\n%lu iterations in %.3f seconds (%.3f iterations/sec)\n",
+           iter, tv_diff, (double)iter/tv_diff);
+    exit(EXIT_SUCCESS);
+}
+
+int main(int argc, char *argv[])
+{
+    typedef int (*tcfp)(void);
+    tcfp all_tests[] = { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 };
+
+    char *usage = "Usage: %s [-h] [-d] [-q] [-r] [-n #] tc...\n";
+    int i, j, opt;
+
+    while ((opt = getopt(argc, argv, "h?dqrn:")) != -1) {
+        switch (opt) {
+        case 'h':
+        case '?':
+            printf(usage, argv[0]);
+            return EXIT_SUCCESS;
+        case 'd':
+            debug = 1;
+            break;
+        case 'q':
+            quiet = 1;
+            break;
+        case 'r':
+            repeat = 1;
+            break;
+        case 'n':
+            num_words = atoi(optarg);
+            if (num_words <= 0) {
+                fprintf(stderr, "-n requires a positive integer argument\n");
+                return EXIT_FAILURE;
+            }
+            break;
+        default:
+            fprintf(stderr, usage, argv[0]);
+            return EXIT_FAILURE;
+        }
+    }
+
+    /* set up EIM */
+    if (eim_setup() != 0) {
+        fprintf(stderr, "EIM setup failed\n");
+        return EXIT_FAILURE;
+    }
+
+    /* repeat one test until interrupted */
+    if (repeat) {
+        tcfp tc;
+        if (optind != argc - 1) {
+            fprintf(stderr, "only one test case can be repeated\n");
+            return EXIT_FAILURE;
+        }
+        j = atoi(argv[optind]);
+        if (j < 0 || j >= sizeof(all_tests)/sizeof(all_tests[0])) {
+            fprintf(stderr, "invalid test number %s\n", argv[optind]);
+            return EXIT_FAILURE;
+        }
+        tc = (all_tests[j]);
+        srand(time(NULL));
+        signal(SIGINT, sighandler);
+        gettimeofday(&tv_start, NULL);
+        while (1) {
+            ++iter;
+            if ((iter & 0xffff) == 0) {
+                printf(".");
+                fflush(stdout);
+            }
+            if (tc() != 0)
+                sighandler(0);
+        }
+        return EXIT_SUCCESS;    /*NOTREACHED*/
+    }
+
+    /* no args == run all tests */
+    if (optind >= argc) {
+        for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j)
+            if (all_tests[j]() != 0)
+                return EXIT_FAILURE;
+        return EXIT_SUCCESS;
+    }
+
+    /* run one or more tests (by number) or groups of tests (by name) */
+    for (i = optind; i < argc; ++i) {
+        if (strcmp(argv[i], "all") == 0) {
+            for (j = 0; j < sizeof(all_tests)/sizeof(all_tests[0]); ++j)
+                if (all_tests[j]() != 0)
+                    return EXIT_FAILURE;
+        }
+        else if (isdigit(argv[i][0]) &&
+                 (((j = atoi(argv[i])) >= 0) &&
+                  (j < sizeof(all_tests)/sizeof(all_tests[0])))) {
+            if (all_tests[j]() != 0)
+                return EXIT_FAILURE;
+        }
+        else {
+            fprintf(stderr, "unknown test case %s\n", argv[i]);
+            return EXIT_FAILURE;
+        }
+    }
+
+    return EXIT_SUCCESS;
+}