diff options
Diffstat (limited to 'core_selector/src/rtl/rng_selector.v')
| -rw-r--r-- | core_selector/src/rtl/rng_selector.v | 88 |
1 files changed, 30 insertions, 58 deletions
diff --git a/core_selector/src/rtl/rng_selector.v b/core_selector/src/rtl/rng_selector.v index d88fe82..3a0bd73 100644 --- a/core_selector/src/rtl/rng_selector.v +++ b/core_selector/src/rtl/rng_selector.v @@ -41,69 +41,41 @@ module rng_selector ( - input wire sys_clk, - input wire sys_rst, - input wire sys_ena, + input wire sys_clk, + input wire sys_rst, - input wire [13: 0] sys_eim_addr, - input wire sys_eim_wr, - input wire sys_eim_rd, + input wire noise, + + input wire sys_ena, + input wire [13: 0] sys_eim_addr, + input wire sys_eim_wr, + input wire sys_eim_rd, output wire [31 : 0] sys_read_data, - input wire [31 : 0] sys_write_data + input wire [31 : 0] sys_write_data, + + output wire [7 : 0] debug ); - - // - // Output Register - // - reg [31: 0] tmp_read_data; - assign sys_read_data = tmp_read_data; - - /* So far we have no RNG cores, let's make some dummy 32-bit registers here - * to prevent ISE from complaining that we don't use input ports. - */ - - reg [31: 0] reg_dummy_first; - reg [31: 0] reg_dummy_second; - reg [31: 0] reg_dummy_third; - - always @(posedge sys_clk) - // - if (sys_rst) begin - reg_dummy_first <= {8{4'hA}}; - reg_dummy_second <= {8{4'hB}}; - reg_dummy_third <= {8{4'hC}}; - end else if (sys_ena) begin - // - if (sys_eim_wr) begin - // - // WRITE handler - // - case (sys_eim_addr) - 14'd0: reg_dummy_first <= sys_write_data; - 14'd1: reg_dummy_second <= sys_write_data; - 14'd2: reg_dummy_third <= sys_write_data; - endcase - // - end - // - if (sys_eim_rd) begin - // - // READ handler - // - case (sys_eim_addr) - 14'd0: tmp_read_data <= reg_dummy_first; - 14'd1: tmp_read_data <= reg_dummy_second; - 14'd2: tmp_read_data <= reg_dummy_third; - // - default: - tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes - endcase - // - end - // - end + // This is a pass-through to trng.v, which instantiates and muxes the + // entropy sources, mixer, and csprng. + + trng trng_inst + ( + .clk(sys_clk), + .reset_n(~sys_rst), + + .avalanche_noise(noise), + + .cs(sys_ena & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address(sys_eim_addr[11:0]), + .write_data(sys_write_data), + .read_data(sys_read_data), + + .debug(debug) + ); endmodule |