diff options
Diffstat (limited to 'core_selector/src/rtl/cipher_selector.v')
| -rw-r--r-- | core_selector/src/rtl/cipher_selector.v | 165 |
1 files changed, 108 insertions, 57 deletions
diff --git a/core_selector/src/rtl/cipher_selector.v b/core_selector/src/rtl/cipher_selector.v index c7ae812..654ab4e 100644 --- a/core_selector/src/rtl/cipher_selector.v +++ b/core_selector/src/rtl/cipher_selector.v @@ -10,7 +10,7 @@ // // Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov // Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: @@ -49,66 +49,117 @@ module cipher_selector input wire sys_eim_wr, input wire sys_eim_rd, output wire [31 : 0] sys_read_data, - input wire [31 : 0] sys_write_data + input wire [31 : 0] sys_write_data, + output wire sys_error ); + //---------------------------------------------------------------- + // Address Decoder + //---------------------------------------------------------------- + // upper 6 bits specify core being addressed + wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8]; + // lower 8 bits specify register offset in core + wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; + + + //---------------------------------------------------------------- + // List of Available Cores + //---------------------------------------------------------------- + // Comment following lines to exclude cores from implementation. + `define USE_CORE_AES + `define USE_CORE_CHACHA + + + //---------------------------------------------------------------- + // Core Address Table + //---------------------------------------------------------------- + localparam CORE_ADDR_AES = 6'd0; + localparam CORE_ADDR_CHACHA = 6'd1; + + + //---------------------------------------------------------------- + // AES + //---------------------------------------------------------------- + `ifdef USE_CORE_AES + wire enable_aes = sys_ena && (addr_core_num == CORE_ADDR_AES); + wire [31: 0] read_data_aes; + wire error_aes; + + aes aes_inst + ( + .clk(sys_clk), + .reset_n(~sys_rst), + + .cs(enable_aes & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), - // - // Output Register - // - reg [31: 0] tmp_read_data; - assign sys_read_data = tmp_read_data; - - - /* So far we have no CIPHER cores, let's make some dummy 32-bit registers here - * to prevent ISE from complaining that we don't use input ports. - */ - - reg [31: 0] reg_dummy_first; - reg [31: 0] reg_dummy_second; - reg [31: 0] reg_dummy_third; - - always @(posedge sys_clk) + .address(addr_core_reg), + .write_data(sys_write_data), + .read_data(read_data_aes), + .error(error_aes) + ); + `endif + + + //---------------------------------------------------------------- + // CHACHA + //---------------------------------------------------------------- + `ifdef USE_CORE_CHACHA + wire enable_chacha = sys_ena && (addr_core_num == CORE_ADDR_CHACHA); + wire [31: 0] read_data_chacha; + wire error_chacha; + + chacha chacha_inst + ( + .clk(sys_clk), + .reset_n(~sys_rst), + + .cs(enable_chacha & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address(addr_core_reg), + .write_data(sys_write_data), + .read_data(read_data_chacha), + .error(error_chacha) + ); + `endif + + + //---------------------------------------------------------------- + // Output (Read Data) Multiplexor + //---------------------------------------------------------------- + reg [31: 0] sys_read_data_mux; + assign sys_read_data = sys_read_data_mux; + reg sys_error_mux; + assign sys_error = sys_error_mux; + + always @* // - if (sys_rst) - begin - reg_dummy_first <= {8{4'hD}}; - reg_dummy_second <= {8{4'hE}}; - reg_dummy_third <= {8{4'hF}}; - end - else if (sys_ena) - begin - // - if (sys_eim_wr) - begin - // - // WRITE handler - // - case (sys_eim_addr) - 14'd0: reg_dummy_first <= sys_write_data; - 14'd1: reg_dummy_second <= sys_write_data; - 14'd2: reg_dummy_third <= sys_write_data; - endcase - // - end - // - if (sys_eim_rd) - begin - // - // READ handler - // - case (sys_eim_addr) - 14'd0: tmp_read_data <= reg_dummy_first; - 14'd1: tmp_read_data <= reg_dummy_second; - 14'd2: tmp_read_data <= reg_dummy_third; - // - default: tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes - endcase - // - end - // - end - + case (addr_core_num) + // + `ifdef USE_CORE_AES + CORE_ADDR_AES: + begin + sys_read_data_mux = read_data_aes; + sys_error_mux = error_aes; + end + `endif + `ifdef USE_CORE_CHACHA + CORE_ADDR_CHACHA: + begin + sys_read_data_mux = read_data_chacha; + sys_error_mux = error_chacha; + end + `endif + // + default: + begin + sys_read_data_mux = {32{1'b0}}; + sys_error_mux = 1; + end + // + endcase + endmodule |