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+# Config file for the Cryptech FPGA framework.
+
+# [default] section. Defines defaults, if not specified on the command line.
+#
+# board: Name of the default [board] section to build, if the --board
+#   option is not given.
+#
+# project: Name of the default [project] section to build, if the
+#   --project option is not given.
+
+[default]
+board = alpha
+project = hsm
+
+# [board] sections, defining the target device.
+#
+# bus name: Name of the FPGA communications bus, used by applications to
+#   read/write the FPGA core registers.
+#
+# bus width: Width of the FPGA address bus. (The data bus is always 32 bits.)
+#
+# extra wires: Defines extra I/O ports in the core_selector module definition.
+#   Note this is a blob of text, not interpreted, so formatting and commas
+#   will be copied out verbatim.
+#
+# requires: A list of cores that must be present. This supports a fallback
+#   scheme so that, for example, if 'mkmif' is not in the project's list
+#   of cores, it will use 'dummy-mkmif' instead. In this case, there is no
+#   whitespace around the '/'.
+
+[board alpha]
+# Cryptech Alpha board
+bus name = fmc
+bus width = 24
+modexp = modexpa7
+extra wires =
+   output wire         mkm_sclk,
+   output wire         mkm_cs_n,
+   input wire          mkm_do,
+   output wire         mkm_di,
+requires = mkmif/dummy-mkmif
+
+[board dev-bridge]
+# Cryptech dev-bridge board - a Novena daughterboard that talks to the
+# Novena's FPGA through the high-speed connector.
+bus name = fmc
+bus width = 17
+modexp = modexps6
+
+[board novena]
+# Novena board
+bus name = eim
+bus width = 17
+modexp = modexps6
+
+# [project] sections
+# 
+# cores: A list of cores to build.
+
+[project bare]
+# for quick builds to test the bus
+cores = 
+
+[project hash]
+# for testing just the SHA cores
+cores = sha1 sha256 sha512
+
+[project trng]
+# for testing just the True Random Number Generator
+cores = trng
+
+[project modexp]
+# for testing just the Modular Exponentiation
+cores = modexp
+
+[project mkmif]
+# for testing just the Master Key Memory Interface
+cores = mkmif
+
+[project rsa]
+# RSA signing and verification. This is as much as will fit on the
+# Novena's Spartan-6 FPGA.
+cores = sha256 aes trng modexp
+
+[project hsm]
+# make me one with everything
+#cores = sha1 sha256 sha512 aes trng modexp
+# super-size it
+cores = mkmif trng sha1 sha1 sha1 sha256 sha256 sha256 sha512 sha512 sha512 aes aes aes modexp modexp modexp
+
+# [core] sections
+#
+# vfiles: A list of Verilog files to include in the vfiles list when
+#   including a particular core.  All (optional) cores must have a
+#   vfiles option, so that the configuration program knows what to put
+#   into core_vfiles.mk.
+#
+# requires: A list of other cores whose vfiles must be loaded to build
+#   this core.  This has no effect on the generated core_selector.v
+#   file, and has no effect at all if an instance of a core named here
+#   is already included in the build.
+#
+# subcores: The TRNG core has an internal mux with slots for 16 sub-cores
+#   (although it only uses 4). Unlike 'requires', subcores consume address
+#   space and have to be accounted for in core_selector.v.
+#
+# core blocks: By default, each core gets a block of 256 registers. If a
+#   core needs more address space (e.g. for block memories or subcores),
+#   set the number of 256-block registers here.
+#
+# error wire: boolean indicating whether the core wants a error wire.
+#
+# block memory: boolean indicating whether the core uses block memory.
+#   Effect of this is a bit strange: setting it triggers generation of
+#   a one-cycle timing delay for every core in this build that does
+#   *not* use block memory.  When no cores in the build use block
+#   memory, the delay isn't necessary and is therefore omitted.
+#
+# extra ports: Extra port definitions in the core instance.
+#   Note this is a blob of text, not interpreted, so formatting and commas
+#   will be copied out verbatim.
+
+[core sha1]
+vfiles =
+	hash/sha1/src/rtl/sha1.v
+	hash/sha1/src/rtl/sha1_core.v
+	hash/sha1/src/rtl/sha1_w_mem.v
+
+[core sha256]
+vfiles =
+	hash/sha256/src/rtl/sha256.v
+	hash/sha256/src/rtl/sha256_core.v
+	hash/sha256/src/rtl/sha256_k_constants.v
+	hash/sha256/src/rtl/sha256_w_mem.v
+
+[core sha512]
+vfiles =
+	hash/sha512/src/rtl/sha512.v
+	hash/sha512/src/rtl/sha512_core.v
+	hash/sha512/src/rtl/sha512_h_constants.v
+	hash/sha512/src/rtl/sha512_k_constants.v
+	hash/sha512/src/rtl/sha512_w_mem.v
+
+[core trng]
+requires = chacha sha512
+core blocks = 16
+subcores =
+	avalanche_entropy
+	rosc_entropy
+	trng_mixer
+	trng_csprng
+extra ports =
+      .avalanche_noise(noise),
+      .debug(debug),
+vfiles =
+	rng/avalanche_entropy/src/rtl/avalanche_entropy.v
+	rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v
+	rng/rosc_entropy/src/rtl/rosc.v
+	rng/rosc_entropy/src/rtl/rosc_entropy.v
+	rng/rosc_entropy/src/rtl/rosc_entropy_core.v
+	rng/trng/src/rtl/trng.v
+	rng/trng/src/rtl/trng_csprng.v
+	rng/trng/src/rtl/trng_csprng_fifo.v
+	rng/trng/src/rtl/trng_mixer.v
+
+[core aes]
+vfiles =
+	cipher/aes/src/rtl/aes.v
+	cipher/aes/src/rtl/aes_core.v
+	cipher/aes/src/rtl/aes_decipher_block.v
+	cipher/aes/src/rtl/aes_encipher_block.v
+	cipher/aes/src/rtl/aes_inv_sbox.v
+	cipher/aes/src/rtl/aes_key_mem.v
+	cipher/aes/src/rtl/aes_sbox.v
+
+[core chacha]
+vfiles =
+	cipher/chacha/src/rtl/chacha.v
+	cipher/chacha/src/rtl/chacha_core.v
+	cipher/chacha/src/rtl/chacha_qr.v
+
+[core modexpa7]
+# ModExp for Xilinx Artix-7
+core blocks = 4
+block memory = yes
+error wire = no
+module name = modexpa7_wrapper
+vfiles =
+	math/modexpa7/src/rtl/dsp_multiplier_a7.v
+	math/modexpa7/src/rtl/dsp_subtractor_a7.v
+	math/modexpa7/src/rtl/modexpa7_adder64_carry32.v
+	math/modexpa7/src/rtl/modexpa7_buffer_core.v
+	math/modexpa7/src/rtl/modexpa7_buffer_user.v
+	math/modexpa7/src/rtl/modexpa7_modinv32.v
+	math/modexpa7/src/rtl/modexpa7_montgomery_coeff.v
+	math/modexpa7/src/rtl/modexpa7_montgomery_multiplier.v
+	math/modexpa7/src/rtl/modexpa7_top.v
+	math/modexpa7/src/rtl/modexpa7_wrapper.v
+	math/modexpa7/src/rtl/ram_1rw_1ro_readfirst.v
+
+[core modexps6]
+# ModExp for Xilinx Spartan-6
+core blocks = 4
+block memory = yes
+error wire = no
+module name = modexps6_wrapper
+vfiles =
+	math/modexps6/src/rtl/modexps6_adder64_carry32.v
+	math/modexps6/src/rtl/modexps6_buffer_core.v
+	math/modexps6/src/rtl/modexps6_buffer_user.v
+	math/modexps6/src/rtl/modexps6_modinv32.v
+	math/modexps6/src/rtl/modexps6_montgomery_coeff.v
+	math/modexps6/src/rtl/modexps6_montgomery_multiplier.v
+	math/modexps6/src/rtl/modexps6_top.v
+	math/modexps6/src/rtl/modexps6_wrapper.v
+	math/modexps6/src/rtl/ram_1rw_1ro_readfirst.v
+	math/modexps6/src/rtl/ipcore/multiplier_s6.v
+	math/modexps6/src/rtl/ipcore/subtractor_s6.v
+
+[core modexp]
+# portable ModExp
+error wire = no
+vfiles =
+	math/modexp/src/rtl/adder.v
+	math/modexp/src/rtl/blockmem1r1w.v
+	math/modexp/src/rtl/blockmem2r1wptr.v
+	math/modexp/src/rtl/blockmem2r1w.v
+	math/modexp/src/rtl/blockmem2rptr1w.v
+	math/modexp/src/rtl/modexp.v
+	math/modexp/src/rtl/modexp_core.v
+	math/modexp/src/rtl/montprod.v
+	math/modexp/src/rtl/residue.v
+	math/modexp/src/rtl/shl.v
+	math/modexp/src/rtl/shr.v
+
+[core mkmif]
+# Master Key Memory Interface
+error wire = no
+extra ports =
+      .spi_sclk(mkm_sclk),
+      .spi_cs_n(mkm_cs_n),
+      .spi_do(mkm_do),
+      .spi_di(mkm_di),
+vfiles =
+	util/mkmif/src/rtl/mkmif.v
+	util/mkmif/src/rtl/mkmif_core.v
+	util/mkmif/src/rtl/mkmif_spi.v
+
+[core dummy-mkmif]
+# Dummy wires if the mkmif core isn't present, so we don't have unsourced
+# outputs.
+dummy =
+   assign mkm_sclk = 0;
+   assign mkm_cs_n = 0;
+   assign mkm_di = 0;