diff options
| -rw-r--r-- | config/config.cfg | 8 | ||||
| -rw-r--r-- | core_selector/src/rtl/cipher_selector.v | 168 | ||||
| -rw-r--r-- | core_selector/src/rtl/core_selector.v | 307 | ||||
| -rw-r--r-- | core_selector/src/rtl/global_selector.v | 153 | ||||
| -rw-r--r-- | core_selector/src/rtl/hash_selector.v | 260 | ||||
| -rw-r--r-- | core_selector/src/rtl/math_selector.v | 129 | ||||
| -rw-r--r-- | core_selector/src/rtl/rng_selector.v | 84 |
7 files changed, 2 insertions, 1107 deletions
diff --git a/config/config.cfg b/config/config.cfg index 2132509..337ebe5 100644 --- a/config/config.cfg +++ b/config/config.cfg @@ -28,27 +28,23 @@ [default] default-section = rsa -# only the board and comm cores, useful for quick builds to test the bus +# for quick builds to test the bus [bare] cores = -# just the hash cores [hash] cores = sha1 sha256 sha512 -# just the RNG cores [trng] cores = trng -# just the Modular Exponentiation cores [modexp] cores = modexps6 -# just what we need to run RSA [rsa] cores = sha256 aes trng modexps6 -# generate multiple of the same cores +# include multiple of the same core [multi-test] cores = sha256 aes aes chacha aes diff --git a/core_selector/src/rtl/cipher_selector.v b/core_selector/src/rtl/cipher_selector.v deleted file mode 100644 index a8de37e..0000000 --- a/core_selector/src/rtl/cipher_selector.v +++ /dev/null @@ -1,168 +0,0 @@ -//====================================================================== -// -// cipher_selector.v -// ----------------- -// Top level wrapper that creates the Cryptech coretest system. -// The wrapper contains instances of external interface, coretest -// and the core to be tested. And if more than one core is -// present the wrapper also includes address and data muxes. -// -// -// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov -// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -module cipher_selector - ( - input wire sys_clk, - input wire sys_rst_n, - input wire sys_ena, - - input wire [13: 0] sys_eim_addr, - input wire sys_eim_wr, - input wire sys_eim_rd, - output wire [31 : 0] sys_read_data, - input wire [31 : 0] sys_write_data, - output wire sys_error - ); - - //---------------------------------------------------------------- - // Address Decoder - //---------------------------------------------------------------- - // upper 6 bits specify core being addressed - wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8]; - // lower 8 bits specify register offset in core - wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; - - - //---------------------------------------------------------------- - // List of Available Cores - //---------------------------------------------------------------- - // Comment following lines to exclude cores from implementation. - `define USE_CORE_AES - `define USE_CORE_CHACHA - - - //---------------------------------------------------------------- - // Core Address Table - //---------------------------------------------------------------- - localparam CORE_ADDR_AES = 6'd0; - localparam CORE_ADDR_CHACHA = 6'd1; - - - //---------------------------------------------------------------- - // AES - //---------------------------------------------------------------- - `ifdef USE_CORE_AES - wire enable_aes = sys_ena && (addr_core_num == CORE_ADDR_AES); - wire [31: 0] read_data_aes; - wire error_aes; - - aes aes_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_aes & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_aes), - .error(error_aes) - ); - `endif - - - //---------------------------------------------------------------- - // CHACHA - //---------------------------------------------------------------- - `ifdef USE_CORE_CHACHA - wire enable_chacha = sys_ena && (addr_core_num == CORE_ADDR_CHACHA); - wire [31: 0] read_data_chacha; - wire error_chacha; - - chacha chacha_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_chacha & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_chacha), - .error(error_chacha) - ); - `endif - - - //---------------------------------------------------------------- - // Output (Read Data) Multiplexor - //---------------------------------------------------------------- - reg [31: 0] sys_read_data_mux; - assign sys_read_data = sys_read_data_mux; - reg sys_error_mux; - assign sys_error = sys_error_mux; - - always @* - // - case (addr_core_num) - // - `ifdef USE_CORE_AES - CORE_ADDR_AES: - begin - sys_read_data_mux = read_data_aes; - sys_error_mux = error_aes; - end - `endif - `ifdef USE_CORE_CHACHA - CORE_ADDR_CHACHA: - begin - sys_read_data_mux = read_data_chacha; - sys_error_mux = error_chacha; - end - `endif - // - default: - begin - sys_read_data_mux = {32{1'b0}}; - sys_error_mux = 1; - end - // - endcase - - -endmodule - -//====================================================================== -// EOF cipher_selector.v -//====================================================================== diff --git a/core_selector/src/rtl/core_selector.v b/core_selector/src/rtl/core_selector.v deleted file mode 100644 index 9607cb3..0000000 --- a/core_selector/src/rtl/core_selector.v +++ /dev/null @@ -1,307 +0,0 @@ -//====================================================================== -// -// core_selector.v -// --------------- -// Top level wrapper that creates the Cryptech coretest system. -// The wrapper contains instances of external interface, coretest -// and the core to be tested. And if more than one core is -// present the wrapper also includes address and data muxes. -// -// -// Author: Pavel Shatov -// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -module core_selector - ( - input wire sys_clk, - input wire sys_rst_n, - - input wire [16: 0] sys_eim_addr, - input wire sys_eim_wr, - input wire sys_eim_rd, - output wire [31: 0] sys_read_data, - input wire [31: 0] sys_write_data, - output wire sys_error, - - input wire noise, - output wire [7 : 0] debug - ); - - - /* Three upper bits of address [16:14] are used to select memory segment. - * There can be eight segments. So far segment 0 is used for global - * registers, segment 1 is used for hashes, segment 2 is reserved for - * random number generators, segment 3 is reserved for chiphers. Other - * segments are not used so far. - */ - - /* Every segment has its own memory map, take at look at corresponding - * selectors for more information. - */ - - //---------------------------------------------------------------- - // Address Decoder - //---------------------------------------------------------------- - // 3 upper bits are decoded here - wire [ 2: 0] addr_segment = sys_eim_addr[16:14]; - // 14 lower bits are decoded in corresponding segment selectors - wire [13: 0] addr_segment_int = sys_eim_addr[13: 0]; - - - //---------------------------------------------------------------- - // List of Available Segments - //---------------------------------------------------------------- - // Comment following lines to exclude segments from implementation. - `define USE_SEGMENT_GLOBALS - `define USE_SEGMENT_HASHES - `define USE_SEGMENT_RNGS - `define USE_SEGMENT_CIPHERS - `define USE_SEGMENT_MATH - - - //---------------------------------------------------------------- - // Segment Address Table - //---------------------------------------------------------------- - localparam SEGMENT_ADDR_GLOBALS = 3'd0; - localparam SEGMENT_ADDR_HASHES = 3'd1; - localparam SEGMENT_ADDR_RNGS = 3'd2; - localparam SEGMENT_ADDR_CIPHERS = 3'd3; - localparam SEGMENT_ADDR_MATH = 3'd4; - - - //---------------------------------------------------------------- - // GLOBALS Segment - //---------------------------------------------------------------- - `ifdef USE_SEGMENT_GLOBALS - wire segment_enable_globals = (addr_segment == SEGMENT_ADDR_GLOBALS) ? 1'b1 : 1'b0; - wire [31: 0] segment_globals_read_data; - wire segment_globals_error; - - global_selector globals - ( - .sys_clk(sys_clk), - .sys_rst_n(sys_rst_n), - .sys_ena(segment_enable_globals), - - .sys_eim_addr(addr_segment_int), - .sys_eim_wr(sys_eim_wr), - .sys_eim_rd(sys_eim_rd), - .sys_write_data(sys_write_data), - .sys_read_data(segment_globals_read_data), - .sys_error(segment_globals_error) - ); - - reg [31: 0] segment_globals_read_data_reg; - always @(posedge sys_clk) - segment_globals_read_data_reg <= segment_globals_read_data; - - `endif - - - //---------------------------------------------------------------- - // HASHES Segment - //---------------------------------------------------------------- - `ifdef USE_SEGMENT_HASHES - wire segment_enable_hashes = (addr_segment == SEGMENT_ADDR_HASHES) ? 1'b1 : 1'b0; - wire [31: 0] segment_hashes_read_data; - wire segment_hashes_error; - - hash_selector hashes - ( - .sys_clk(sys_clk), - .sys_rst_n(sys_rst_n), - .sys_ena(segment_enable_hashes), - - .sys_eim_addr(addr_segment_int), - .sys_eim_wr(sys_eim_wr), - .sys_eim_rd(sys_eim_rd), - .sys_write_data(sys_write_data), - .sys_read_data(segment_hashes_read_data), - .sys_error(segment_hashes_error) - ); - - reg [31: 0] segment_hashes_read_data_reg; - always @(posedge sys_clk) - segment_hashes_read_data_reg <= segment_hashes_read_data; - - `endif - - - //---------------------------------------------------------------- - // RNGS Segment - //---------------------------------------------------------------- - `ifdef USE_SEGMENT_RNGS - wire segment_enable_rngs = (addr_segment == SEGMENT_ADDR_RNGS) ? 1'b1 : 1'b0; - wire [31: 0] segment_rngs_read_data; - wire segment_rngs_error; - wire [7 : 0] segment_rngs_debug; - - rng_selector rngs - ( - .sys_clk(sys_clk), - .sys_rst_n(sys_rst_n), - .sys_ena(segment_enable_rngs), - - .sys_eim_addr(addr_segment_int), - .sys_eim_wr(sys_eim_wr), - .sys_eim_rd(sys_eim_rd), - .sys_write_data(sys_write_data), - .sys_read_data(segment_rngs_read_data), - .sys_error(segment_rngs_error), - - .noise(noise), // only RNG segment uses these ports - .debug(segment_rngs_debug) - ); - - reg [31: 0] segment_rngs_read_data_reg; - always @(posedge sys_clk) - segment_rngs_read_data_reg <= segment_rngs_read_data; - - `endif - - - //---------------------------------------------------------------- - // CIPHERS Segment - //---------------------------------------------------------------- - `ifdef USE_SEGMENT_CIPHERS - wire segment_enable_ciphers = (addr_segment == SEGMENT_ADDR_CIPHERS) ? 1'b1 : 1'b0; - wire [31: 0] segment_ciphers_read_data; - - cipher_selector ciphers - ( - .sys_clk(sys_clk), - .sys_rst_n(sys_rst_n), - .sys_ena(segment_enable_ciphers), - - .sys_eim_addr(addr_segment_int), - .sys_eim_wr(sys_eim_wr), - .sys_eim_rd(sys_eim_rd), - .sys_write_data(sys_write_data), - .sys_read_data(segment_ciphers_read_data), - .sys_error(segment_ciphers_error) - ); - - reg [31: 0] segment_ciphers_read_data_reg; - always @(posedge sys_clk) - segment_ciphers_read_data_reg <= segment_ciphers_read_data; - - `endif - - - //---------------------------------------------------------------- - // MATH Segment - //---------------------------------------------------------------- - `ifdef USE_SEGMENT_MATH - wire segment_enable_math = (addr_segment == SEGMENT_ADDR_MATH) ? 1'b1 : 1'b0; - wire [31: 0] segment_math_read_data; - - math_selector maths - ( - .sys_clk(sys_clk), - .sys_rst_n(sys_rst_n), - .sys_ena(segment_enable_math), - - .sys_eim_addr(addr_segment_int), - .sys_eim_wr(sys_eim_wr), - .sys_eim_rd(sys_eim_rd), - .sys_write_data(sys_write_data), - .sys_read_data(segment_math_read_data) - ); - `endif - - - //---------------------------------------------------------------- - // Output (Read Data) Bus - //---------------------------------------------------------------- - reg [31: 0] sys_read_data_reg; - reg [07: 0] sys_debug; - reg sys_error_reg; - - assign sys_read_data = sys_read_data_reg; - assign sys_error = sys_error_reg; - assign debug = sys_debug; - - always @* - begin : output_select - sys_debug = 8'h00; - sys_read_data_reg = {32{1'b0}}; - sys_error_reg = 1; - sys_debug = 8'h00; - - case (addr_segment) - `ifdef USE_SEGMENT_GLOBALS - SEGMENT_ADDR_GLOBALS: - begin - sys_read_data_reg = segment_globals_read_data_reg; - sys_error_reg = segment_globals_error; - end - `endif - `ifdef USE_SEGMENT_HASHES - SEGMENT_ADDR_HASHES: - begin - sys_read_data_reg = segment_hashes_read_data_reg; - sys_error_reg = segment_hashes_error; - end - `endif - `ifdef USE_SEGMENT_RNGS - SEGMENT_ADDR_RNGS: - begin - sys_read_data_reg = segment_rngs_read_data_reg; - sys_error_reg = segment_rngs_error; - sys_debug = segment_rngs_debug; - end - `endif - `ifdef USE_SEGMENT_CIPHERS - SEGMENT_ADDR_CIPHERS: - begin - sys_read_data_reg = segment_ciphers_read_data_reg; - sys_error_reg = segment_ciphers_error; - end - `endif - `ifdef USE_SEGMENT_MATH - SEGMENT_ADDR_MATH: - begin - sys_read_data_reg = segment_math_read_data; - sys_error_reg = 0; - end - `endif - default: - begin - end - endcase - end // output_select - -endmodule - - -//====================================================================== -// EOF core_selector.v -//====================================================================== diff --git a/core_selector/src/rtl/global_selector.v b/core_selector/src/rtl/global_selector.v deleted file mode 100644 index 2b9e20a..0000000 --- a/core_selector/src/rtl/global_selector.v +++ /dev/null @@ -1,153 +0,0 @@ -//====================================================================== -// -// global_selector.v -// ----------------- -// Top level wrapper that creates the Cryptech coretest system. -// The wrapper contains instances of external interface, coretest -// and the core to be tested. And if more than one core is -// present the wrapper also includes address and data muxes. -// -// -// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov -// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -module global_selector - ( - input wire sys_clk, - input wire sys_rst_n, - input wire sys_ena, - - input wire [13: 0] sys_eim_addr, - input wire sys_eim_wr, - input wire sys_eim_rd, - output wire [31 : 0] sys_read_data, - input wire [31 : 0] sys_write_data, - output wire sys_error - ); - - - //---------------------------------------------------------------- - // Address Decoder - //---------------------------------------------------------------- - // upper 6 bits specify core being addressed - wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8]; - // lower 8 bits specify register offset in core - wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; - - - //---------------------------------------------------------------- - // Core Address Table - //---------------------------------------------------------------- - localparam CORE_ADDR_BOARD_REGS = 6'd0; - localparam CORE_ADDR_COMM_REGS = 6'd1; - - - //---------------------------------------------------------------- - // Board-Level Registers - //---------------------------------------------------------------- - wire [31: 0] read_data_board; - wire enable_board = sys_ena && (addr_core_num == CORE_ADDR_BOARD_REGS); - wire error_board; - - board_regs board_regs - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_board & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_board), - .error(error_board) - ); - - - //---------------------------------------------------------------- - // Communication-Channel Registers - //---------------------------------------------------------------- - wire [31: 0] read_data_comm; - wire enable_comm = sys_ena && (addr_core_num == CORE_ADDR_COMM_REGS); - wire error_comm; - - comm_regs comm_regs - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_comm & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_comm), - .error(error_comm) - ); - - - //---------------------------------------------------------------- - // Output (Read Data) Multiplexor - //---------------------------------------------------------------- - reg [31: 0] sys_read_data_mux; - assign sys_read_data = sys_read_data_mux; - reg sys_error_mux; - assign sys_error = sys_error_mux; - - always @* - // - case (addr_core_num) - // - CORE_ADDR_BOARD_REGS: - begin - sys_read_data_mux = read_data_board; - sys_error_mux = error_board; - end - CORE_ADDR_COMM_REGS: - begin - sys_read_data_mux = read_data_comm; - sys_error_mux = error_comm; - end - // - default: - begin - sys_read_data_mux = {32{1'b0}}; - sys_error_mux = 1; - end - // - endcase - - -endmodule - -//====================================================================== -// EOF global_selector.v -//====================================================================== diff --git a/core_selector/src/rtl/hash_selector.v b/core_selector/src/rtl/hash_selector.v deleted file mode 100644 index 81fac7d..0000000 --- a/core_selector/src/rtl/hash_selector.v +++ /dev/null @@ -1,260 +0,0 @@ -//====================================================================== -// -// hash_selector.v -// --------------- -// Top level wrapper that creates the Cryptech coretest system. -// The wrapper contains instances of external interface, coretest -// and the core to be tested. And if more than one core is -// present the wrapper also includes address and data muxes. -// -// -// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov -// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -module hash_selector - ( - input wire sys_clk, - input wire sys_rst_n, - input wire sys_ena, - - input wire [13 : 0] sys_eim_addr, - input wire sys_eim_wr, - input wire sys_eim_rd, - output wire [31 : 0] sys_read_data, - input wire [31 : 0] sys_write_data, - output wire sys_error - ); - - /* In this memory segment (HASHES) we have 14 address bits. Every core has - * 8-bit internal address space, so we can have up to 2^(14-8) = 64 cores here. - * - * So far we have three cores: SHA-1, SHA-256 and SHA-512. - */ - - /********************************************************* - * To add new HASH core named XXX follow the steps below * - ********************************************************* - * - * 1. Add corresponding `define under "List of Available Cores", this will - * allow users to exclude your core from implementation to save some - * slices in case they don't need it. - * - * `define USE_CORE_XXX -XXX define in wrapper core - * - * - * 2. Choose address of your new core and add corresponding line under - * "Core Address Table". Core addresses can be in the range from 0 to 63 - * inclusively. - * - * localparam CORE_ADDR_XXX = 6'dN; -XXX move to `define in wrapper core?? - * - * - * 3. Add instantiation of your new core after all existing cores - * surrounded by conditional synthesis directives. - * You also need a 32-bit output (read data) bus for your core and an - * enable flag. Note that sys_rst_n in an active-low sync reset signal. - * - * `ifdef USE_CORE_XXX - * wire [31: 0] read_data_xxx; - * wire enable_xxx = sys_ena && (addr_core_num == CORE_ADDR_XXX); - * xxx xxx_inst - * ( - * .clk(sys_clk), - * .reset_n(sys_rst_n), - * .cs(enable_xxx & (sys_eim_rd | sys_eim_wr)), - * .we(sys_eim_wr), - * .address(addr_core_reg), - * .write_data(sys_write_data), - * .read_data(read_data_xxx), - * .error() - * ); - * `endif - * - * - * 4. Add previously created data bus to "Output (Read Data) Multiplexor" - * in the end of this file. - * - * `ifdef USE_CORE_XXX - * CORE_ADDR_XXX: - * sys_read_data_mux = read_data_xxx; - * `endif - * - */ - - - //---------------------------------------------------------------- - // Address Decoder - //---------------------------------------------------------------- - // upper 6 bits specify core being addressed - wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8]; - // lower 8 bits specify register offset in core - wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; - - - //---------------------------------------------------------------- - // List of Available Cores - //---------------------------------------------------------------- - // Comment following lines to exclude cores from implementation. - `define USE_CORE_SHA1 - `define USE_CORE_SHA256 - `define USE_CORE_SHA512 - - - //---------------------------------------------------------------- - // Core Address Table - //---------------------------------------------------------------- - localparam CORE_ADDR_SHA1 = 6'd0; - localparam CORE_ADDR_SHA256 = 6'd1; - localparam CORE_ADDR_SHA512 = 6'd2; - - - //---------------------------------------------------------------- - // SHA-1 - //---------------------------------------------------------------- - `ifdef USE_CORE_SHA1 - wire enable_sha1 = sys_ena && (addr_core_num == CORE_ADDR_SHA1); - wire [31: 0] read_data_sha1; - wire error_sha1; - - sha1 sha1_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_sha1 & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_sha1), - .error(error_sha1) - ); - `endif - - - //---------------------------------------------------------------- - // SHA-256 - //---------------------------------------------------------------- - `ifdef USE_CORE_SHA256 - wire enable_sha256 = sys_ena && (addr_core_num == CORE_ADDR_SHA256); - wire [31: 0] read_data_sha256; - wire error_sha256; - - sha256 sha256_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_sha256), - .error(error_sha256) - ); - `endif - - - //---------------------------------------------------------------- - // SHA-512 - //---------------------------------------------------------------- - `ifdef USE_CORE_SHA512 - wire enable_sha512 = sys_ena && (addr_core_num == CORE_ADDR_SHA512); - wire [31: 0] read_data_sha512; - wire error_sha512; - - sha512 sha512_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_sha512 & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_sha512), - .error(error_sha512) - ); - `endif - - - //---------------------------------------------------------------- - // Output (Read Data) Multiplexor - //---------------------------------------------------------------- - reg [31: 0] sys_read_data_mux; - assign sys_read_data = sys_read_data_mux; - reg sys_error_mux; - assign sys_error = sys_error_mux; - - always @* - // - case (addr_core_num) - // - `ifdef USE_CORE_SHA1 - CORE_ADDR_SHA1: - begin - sys_read_data_mux = read_data_sha1; - sys_error_mux = error_sha1; - end - `endif - `ifdef USE_CORE_SHA256 - CORE_ADDR_SHA256: - begin - sys_read_data_mux = read_data_sha256; - sys_error_mux = error_sha256; - end - `endif - `ifdef USE_CORE_SHA512 - CORE_ADDR_SHA512: - begin - sys_read_data_mux = read_data_sha512; - sys_error_mux = error_sha512; - end - `endif - // - default: - begin - sys_read_data_mux = {32{1'b0}}; - sys_error_mux = 1; - end - // - endcase - - -endmodule - -//====================================================================== -// EOF hash_selector.v -//====================================================================== diff --git a/core_selector/src/rtl/math_selector.v b/core_selector/src/rtl/math_selector.v deleted file mode 100644 index 8b8473a..0000000 --- a/core_selector/src/rtl/math_selector.v +++ /dev/null @@ -1,129 +0,0 @@ -//====================================================================== -// -// math_selector.v -// --------------- -// Selector of math cores. Currently there is only one core in math - -// the modexp core. That core uses 12 bits and we simply ignore the -// top two bits of the address. If we add more math cores we will -// use these bits to select cores here. -// -// -// -// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov -// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -module math_selector - ( - input wire sys_clk, - input wire sys_rst_n, - input wire sys_ena, - - input wire [13: 0] sys_eim_addr, - input wire sys_eim_wr, - input wire sys_eim_rd, - output wire [31 : 0] sys_read_data, - input wire [31 : 0] sys_write_data - ); - - - //---------------------------------------------------------------- - // List of Available Cores - //---------------------------------------------------------------- - // Comment following lines to exclude cores from implementation. - `define USE_CORE_MODEXPS6 - - - //---------------------------------------------------------------- - // Address Decoder - //---------------------------------------------------------------- -`ifdef USE_CORE_MODEXPS6 - // upper 4 bits specify core being addressed - wire [ 3: 0] addr_core_num = sys_eim_addr[13:10]; - // lower 10 bits specify register offset in core - wire [ 9: 0] addr_core_reg = sys_eim_addr[ 9: 0]; -`endif - - - //---------------------------------------------------------------- - // Core Address Table - //---------------------------------------------------------------- - `ifdef USE_CORE_MODEXPS6 - localparam CORE_ADDR_MODEXPS6 = 4'd0; - `endif - - - //---------------------------------------------------------------- - // ModExpS6 - //---------------------------------------------------------------- - `ifdef USE_CORE_MODEXPS6 - wire [31: 0] read_data_modexps6; - wire enable_modexps6 = sys_ena && (addr_core_num == CORE_ADDR_MODEXPS6); - modexps6_wrapper modexps6_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_modexps6 & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_modexps6) - ); - `endif - - - //---------------------------------------------------------------- - // Output (Read Data) Multiplexor - //---------------------------------------------------------------- - reg [31: 0] sys_read_data_mux; - assign sys_read_data = sys_read_data_mux; - - always @* - // - `ifdef USE_CORE_MODEXPS6 - if (addr_core_num == CORE_ADDR_MODEXPS6) - begin - sys_read_data_mux = read_data_modexps6; - end - else - `endif - // - begin - sys_read_data_mux = {32{1'b0}}; - end - - -endmodule - -//====================================================================== -// EOF math_selector.v -//====================================================================== diff --git a/core_selector/src/rtl/rng_selector.v b/core_selector/src/rtl/rng_selector.v deleted file mode 100644 index 82f0e9b..0000000 --- a/core_selector/src/rtl/rng_selector.v +++ /dev/null @@ -1,84 +0,0 @@ -//====================================================================== -// -// rng_selector.v -// ----------------- -// Top level wrapper that creates the Cryptech coretest system. -// The wrapper contains instances of external interface, coretest -// and the core to be tested. And if more than one core is -// present the wrapper also includes address and data muxes. -// -// -// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov -// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -module rng_selector - ( - input wire sys_clk, - input wire sys_rst_n, - input wire sys_ena, - - input wire [13: 0] sys_eim_addr, - input wire sys_eim_wr, - input wire sys_eim_rd, - output wire [31 : 0] sys_read_data, - input wire [31 : 0] sys_write_data, - output wire sys_error, - - input wire noise, - output wire [7 : 0] debug - ); - - - // This is a pass-through to trng.v, which instantiates and muxes the - // entropy sources, mixer, and csprng. - - trng trng_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(sys_ena & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(sys_eim_addr[11:0]), - .write_data(sys_write_data), - .read_data(sys_read_data), - .error(sys_error), - - .avalanche_noise(noise), - .debug(debug) - ); - -endmodule - -//====================================================================== -// EOF rng_selector.v -//====================================================================== |