diff options
| -rw-r--r-- | config/config.cfg | 130 | ||||
| -rwxr-xr-x | config/config.py | 490 | ||||
| -rw-r--r-- | config/core_selector.v | 278 | ||||
| -rw-r--r-- | config/core_vfiles.mk | 42 | ||||
| -rw-r--r-- | core_selector/src/rtl/cipher_selector.v | 168 | ||||
| -rw-r--r-- | core_selector/src/rtl/core_selector.v | 307 | ||||
| -rw-r--r-- | core_selector/src/rtl/global_selector.v | 153 | ||||
| -rw-r--r-- | core_selector/src/rtl/hash_selector.v | 260 | ||||
| -rw-r--r-- | core_selector/src/rtl/math_selector.v | 129 | ||||
| -rw-r--r-- | core_selector/src/rtl/rng_selector.v | 84 |
10 files changed, 940 insertions, 1101 deletions
diff --git a/config/config.cfg b/config/config.cfg new file mode 100644 index 0000000..337ebe5 --- /dev/null +++ b/config/config.cfg @@ -0,0 +1,130 @@ +# Config file for the Cryptech Novena FPGA framework. +# +# Variables used in this file: +# +# default-section: Name of the configuration to build if the user +# doesn't specify one. Only meaningful in the default section. +# +# cores: A list of cores to build. Use with the --section option. +# +# vfiles: A list of Verilog files to include in the vfiles list when +# including a particular core. All (optional) cores must have a +# vfiles option, so that the configuration program knows what to put +# into core_vfiles.mk. +# +# requires: A list of other cores whose vfiles must be loaded to build +# this core. This has no effect on the generated core_selector.v +# file, and has no effect at all if an instance of a core named here +# is already included in the build. +# +# error_wire: boolean indicating whether the core wants a error wire. +# +# block_memory: boolean indicating whether the core uses block memory. +# Effect of this is a bit strange: setting it triggers generation of +# a one-cycle timing delay for every core in this build that does +# *not* use block memory. When no cores in the build use block +# memory, the delay isn't necessary and is therefore omitted. + +[default] +default-section = rsa + +# for quick builds to test the bus +[bare] +cores = + +[hash] +cores = sha1 sha256 sha512 + +[trng] +cores = trng + +[modexp] +cores = modexps6 + +[rsa] +cores = sha256 aes trng modexps6 + +# include multiple of the same core +[multi-test] +cores = sha256 aes aes chacha aes + +[sha1] +vfiles = + hash/sha1/src/rtl/sha1.v + hash/sha1/src/rtl/sha1_core.v + hash/sha1/src/rtl/sha1_w_mem.v + +[sha256] +vfiles = + hash/sha256/src/rtl/sha256.v + hash/sha256/src/rtl/sha256_core.v + hash/sha256/src/rtl/sha256_k_constants.v + hash/sha256/src/rtl/sha256_w_mem.v + +[sha512] +vfiles = + hash/sha512/src/rtl/sha512.v + hash/sha512/src/rtl/sha512_core.v + hash/sha512/src/rtl/sha512_h_constants.v + hash/sha512/src/rtl/sha512_k_constants.v + hash/sha512/src/rtl/sha512_w_mem.v + +[trng] +requires = chacha sha512 +vfiles = + rng/avalanche_entropy/src/rtl/avalanche_entropy.v + rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v + rng/rosc_entropy/src/rtl/rosc.v + rng/rosc_entropy/src/rtl/rosc_entropy.v + rng/rosc_entropy/src/rtl/rosc_entropy_core.v + rng/trng/src/rtl/trng.v + rng/trng/src/rtl/trng_csprng.v + rng/trng/src/rtl/trng_csprng_fifo.v + rng/trng/src/rtl/trng_mixer.v + +[aes] +vfiles = + cipher/aes/src/rtl/aes.v + cipher/aes/src/rtl/aes_core.v + cipher/aes/src/rtl/aes_decipher_block.v + cipher/aes/src/rtl/aes_encipher_block.v + cipher/aes/src/rtl/aes_inv_sbox.v + cipher/aes/src/rtl/aes_key_mem.v + cipher/aes/src/rtl/aes_sbox.v + +[chacha] +vfiles = + cipher/chacha/src/rtl/chacha.v + cipher/chacha/src/rtl/chacha_core.v + cipher/chacha/src/rtl/chacha_qr.v + +[modexps6] +block_memory = yes +error_wire = no +vfiles = + math/modexps6/src/rtl/modexps6_adder64_carry32.v + math/modexps6/src/rtl/modexps6_buffer_core.v + math/modexps6/src/rtl/modexps6_buffer_user.v + math/modexps6/src/rtl/modexps6_modinv32.v + math/modexps6/src/rtl/modexps6_montgomery_coeff.v + math/modexps6/src/rtl/modexps6_montgomery_multiplier.v + math/modexps6/src/rtl/modexps6_top.v + math/modexps6/src/rtl/modexps6_wrapper.v + math/modexps6/src/rtl/ram_1rw_1ro_readfirst.v + math/modexps6/src/rtl/ipcore/multiplier_s6.v + math/modexps6/src/rtl/ipcore/subtractor_s6.v + +[modexp] +error_wire = no +vfiles = + math/modexp/src/rtl/adder.v + math/modexp/src/rtl/blockmem1r1w.v + math/modexp/src/rtl/blockmem2r1wptr.v + math/modexp/src/rtl/blockmem2r1w.v + math/modexp/src/rtl/blockmem2rptr1w.v + math/modexp/src/rtl/modexp.v + math/modexp/src/rtl/modexp_core.v + math/modexp/src/rtl/montprod.v + math/modexp/src/rtl/residue.v + math/modexp/src/rtl/shl.v + math/modexp/src/rtl/shr.v diff --git a/config/config.py b/config/config.py new file mode 100755 index 0000000..f9bab57 --- /dev/null +++ b/config/config.py @@ -0,0 +1,490 @@ +#!/usr/bin/env python + +""" +Generate core_selector.v and core_vfiles.mk for a set of cores. +""" + +# The modexps6 core drags in a one clock cycle delay to other cores, +# to compensate for the extra clock cycle consumed by the block +# memories used in the modexps6 core. We probably want a general +# solution for this, because we're going to run into this problem for +# any core that handles arguments big enough to require block memory. + +# To Do: +# +# - Consider automating the one-clock-cycle delay stuff by adding +# another boolean flag to the config file. Default would be no +# delay, if any included core sets the "I use block memories" flag, +# all other cores would get the delay. Slightly tedious but +# something we can calculate easily enough, and probably an +# improvement over wiring in the delay when nothing needs it. +# +# - Rename script and its config file to something more meaningful. + + +def main(): + """ + Parse arguments and config file, generate core list, generate output. + """ + + from argparse import ArgumentParser, FileType, ArgumentDefaultsHelpFormatter + from sys import exit + + parser = ArgumentParser(description = __doc__, formatter_class = ArgumentDefaultsHelpFormatter) + parser.add_argument("-d", "--debug", help = "enable debugging", action = "store_true") + parser.add_argument("-s", "--section", help = "config file section") + parser.add_argument("-c", "--config", help = "configuration file", default = "config.cfg", type = FileType("r")) + parser.add_argument("--verilog", help = "verilog output file", default = "core_selector.v", type = FileType("w")) + parser.add_argument("--makefile", help = "output makefile", default = "core_vfiles.mk", type = FileType("w")) + parser.add_argument("core", help = "name(s) of core(s)", nargs = "*") + args = parser.parse_args() + + try: + cfg = RawConfigParser() + cfg.readfp(args.config) + + if args.core: + cores = args.core + else: + section = args.section or cfg.get("default", "default-section") + cores = cfg.get(section, "cores").split() + + cores.insert(0, "board_regs") + cores.insert(1, "comm_regs") + + cores = tuple(Core.new(core) for core in cores) + + core_number = 0 + for core in cores: + core_number = core.assign_core_number(core_number) + + for core in cores: + core.configure(cfg) + + if False: + + # For some reason, attempting to optimize out the delay + # code entirely results in a non-working bitstream. Don't + # know why, disabling the optimization works, so just do + # that for now. + + Core.need_one_cycle_delay = any(core.block_memory for core in cores) + + args.verilog.write(createModule_template.format( + addrs = "".join(core.createAddr() for core in cores), + insts = "".join(core.createInstance() for core in cores), + muxes = "".join(core.createMux() for core in cores))) + + args.makefile.write(listVfiles_template.format( + vfiles = "".join(core.listVfiles() for core in cores))) + + except Exception, e: + if args.debug: + raise + exit(str(e)) + + +try: + import ConfigParser as configparser +except ImportError: + import configparser + +class RawConfigParser(configparser.RawConfigParser): + """ + RawConfigParser with a few extensions. + """ + + def getboolean(self, section, option, default = False): + if self.has_option(section, option): + # RawConfigParser is an old-stle class, super() doesn't work, feh. + return configparser.RawConfigParser.getboolean(self, section, option) + else: + return default + + def getvalues(self, section, option): + if self.has_option(section, option): + for value in self.get(section, option).split(): + yield value + + +class Core(object): + """ + Data and methods for a generic core. We can use this directly for + most cores, a few are weird and require subclassing to override + particular methods. + """ + + # Class variable tracking how many times a particular core has + # been instantiated. This controls instance numbering. + + _instance_count = {} + + # Class variable mapping core name to subclass for special cases. + + special_class = {} + + # Class variable recording whether we need a one-cycle delay to + # compensate for block memories. + + need_one_cycle_delay = True + + def __init__(self, name): + self.name = name + self.core_number = None + self.vfiles = [] + self.error_wire = True + self.block_memory = False + self.instance_number = self._instance_count.get(name, 0) + self._instance_count[name] = self.instance_number + 1 + + @classmethod + def new(cls, name): + return cls.special_class.get(name, cls)(name) + + def assign_core_number(self, n): + self.core_number = n + return n + 1 + + def configure(self, cfg): + if self.instance_number == 0: + self.vfiles.extend(cfg.getvalues(self.name, "vfiles")) + for required in cfg.getvalues(self.name, "requires"): + if required not in self._instance_count: + self.vfiles.extend(cfg.getvalues(required, "vfiles")) + self.error_wire = cfg.getboolean(self.name, "error_wire", self.error_wire) + self.block_memory = cfg.getboolean(self.name, "block_memory", self.block_memory) + + @property + def instance_name(self): + if self._instance_count[self.name] > 1: + return "{}_{}".format(self.name, self.instance_number) + else: + return self.name + + @property + def upper_instance_name(self): + return self.instance_name.upper() + + @property + def reset_pin(self): + return ".reset_n(sys_rst_n)" + + @property + def error_port(self): + return ",\n .error(error_{core.instance_name})".format(core = self) if self.error_wire else "" + + @property + def one_cycle_delay(self): + return one_cycle_delay_template.format(core = self) if self.need_one_cycle_delay and not self.block_memory else "" + + @property + def mux_data_reg(self): + return "read_data_" + self.instance_name + ("_reg" if self.need_one_cycle_delay and not self.block_memory else "") + + @property + def mux_error_reg(self): + return "error_" + self.instance_name if self.error_wire else "0" + + def createInstance(self): + return createInstance_template_generic.format(core = self) + + def createAddr(self): + return createAddr_template.format(core = self) + + def createMux(self): + return createMux_template.format(core = self, core0 = self) + + def listVfiles(self): + return "".join(" \\\n\t$(CORE_TREE)/" + vfile for vfile in self.vfiles) + + +class SubCore(Core): + """" + Override mux handling for TRNG's sub-cores. + """ + + def __init__(self, name, parent): + super(SubCore, self).__init__(name) + self.parent = parent + + def createMux(self): + return createMux_template.format(core = self, core0 = self.parent) + + +class TRNGCore(Core): + """ + The TRNG core has an internal mux with slots for 15 sub-cores, + most of which are empty. This is a bit of a mess. + + Mostly this means that our method calls have to iterate over all + of the subcores after handling the base TRNG core, but we also use + different templates, and fiddle with addresses a bit. + + Mux numbers have to be dug out of the TRNG Verilog source. + """ + + # TRNG subcore name -> internal mux number. + subcore_parameters = dict(avalanche_entropy = 0x1, + rosc_entropy = 0x2, + trng_mixer = 0x3, + trng_csprng = 0x4) + + def __init__(self, name): + super(TRNGCore, self).__init__(name) + self.subcores = tuple(SubCore(name, self) + for name in sorted(self.subcore_parameters, + key = lambda x: self.subcore_parameters[x])) + + def assign_core_number(self, n): + n = super(TRNGCore, self).assign_core_number(n) + for subcore in self.subcores: + subcore.assign_core_number(self.core_number + self.subcore_parameters[subcore.name]) + return n + 15 + + @property + def last_subcore_upper_instance_name(self): + return self.subcores[-1].upper_instance_name + + def createInstance(self): + return createInstance_template_TRNG.format(core = self) + + def createAddr(self): + return super(TRNGCore, self).createAddr() + "".join(subcore.createAddr() for subcore in self.subcores) + + def createMux(self): + return super(TRNGCore, self).createMux() + "".join(subcore.createMux() for subcore in self.subcores) + + +class ModExpS6Core(Core): + """ + ModExpS6 core consumes as much space as four ordinary cores, and + uses different templates to handle the differences in timing and + addressing. + """ + + def assign_core_number(self, n): + n = super(ModExpS6Core, self).assign_core_number(n) + return n + 3 + + def createInstance(self): + return createInstance_template_ModExpS6.format(core = self) + + def createMux(self): + return createMux_modexps6_template.format(core = self, core0 = self) + + +# Hook special classes in as handlers for the cores that require them. + +Core.special_class.update( + trng = TRNGCore, + modexps6 = ModExpS6Core) + + +# Templates (format strings), here instead of inline in the functions +# that use them, both because some of these are shared between +# multiple functions and because it's easier to read these (and get +# the indentation right) when the're separate. + +# Template used by .createAddr() methods. + +createAddr_template = """\ + localparam CORE_ADDR_{core.upper_instance_name:21s} = 9'h{core.core_number:02x}; +""" + +# Template used by Core.createInstance(). + +createInstance_template_generic = """\ + //---------------------------------------------------------------- + // {core.upper_instance_name} + //---------------------------------------------------------------- + wire enable_{core.instance_name} = (addr_core_num == CORE_ADDR_{core.upper_instance_name}); + wire [31: 0] read_data_{core.instance_name}; + wire error_{core.instance_name}; + + {core.name} {core.instance_name}_inst + ( + .clk(sys_clk), + {core.reset_pin}, + + .cs(enable_{core.instance_name} & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address(addr_core_reg), + .write_data(sys_write_data), + .read_data(read_data_{core.instance_name}){core.error_port} + ); + +{core.one_cycle_delay} + +""" + +# Template used by ModExpS6Core.createInstance(). This is different +# enough from the base template that it's easier to make this separate. + +createInstance_template_ModExpS6 = """\ + //---------------------------------------------------------------- + // {core.upper_instance_name} + //---------------------------------------------------------------- + wire enable_{core.instance_name} = (addr_core_num >= CORE_ADDR_{core.upper_instance_name}) && (addr_core_num <= CORE_ADDR_{core.upper_instance_name} + 9'h03); + wire [31: 0] read_data_{core.instance_name}; + wire [1:0] {core.instance_name}_prefix = addr_core_num[1:0] - CORE_ADDR_{core.upper_instance_name}; + + {core.name}_wrapper {core.instance_name}_inst + ( + .clk(sys_clk), + {core.reset_pin}, + + .cs(enable_{core.instance_name} & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address({{{core.instance_name}_prefix, addr_core_reg}}), + .write_data(sys_write_data), + .read_data(read_data_{core.instance_name}) + ); + + +""" + +# Template used by TRNGCore.createInstance(); this is different enough +# from the generic template that it's (probably) clearer to have this +# separate. + +createInstance_template_TRNG = """\ + //---------------------------------------------------------------- + // {core.upper_instance_name} + //---------------------------------------------------------------- + wire enable_{core.instance_name} = (addr_core_num >= CORE_ADDR_{core.upper_instance_name}) && (addr_core_num <= CORE_ADDR_{core.upper_instance_name} + 9'h0f); + wire [31: 0] read_data_{core.instance_name}; + wire error_{core.instance_name}; + wire [3:0] {core.instance_name}_prefix = addr_core_num[3:0] - CORE_ADDR_{core.upper_instance_name}; + + {core.name} {core.instance_name}_inst + ( + .clk(sys_clk), + {core.reset_pin}, + + .cs(enable_{core.instance_name} & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address({{{core.instance_name}_prefix, addr_core_reg}}), + .write_data(sys_write_data), + .read_data(read_data_{core.instance_name}), + .error(error_{core.instance_name}), + + .avalanche_noise(noise), + .debug(debug) + ); + +{core.one_cycle_delay} + +""" + +# Template for one-cycle delay code. + +one_cycle_delay_template = """\ + reg [31: 0] read_data_{core.instance_name}_reg; + always @(posedge sys_clk) + read_data_{core.instance_name}_reg <= read_data_{core.instance_name}; +""" + +# Template for .createMux() methods. + +createMux_template = """\ + CORE_ADDR_{core.upper_instance_name}: + begin + sys_read_data_mux = {core0.mux_data_reg}; + sys_error_mux = {core0.mux_error_reg}; + end +""" + +# Template for ModExpS6.createMux() method. + +createMux_modexps6_template = """\ + CORE_ADDR_{core.upper_instance_name} + 0, + CORE_ADDR_{core.upper_instance_name} + 1, + CORE_ADDR_{core.upper_instance_name} + 2, + CORE_ADDR_{core.upper_instance_name} + 3: + begin + sys_read_data_mux = {core0.mux_data_reg}; + sys_error_mux = {core0.mux_error_reg}; + end +""" + + +# Top-level (createModule) template. + +createModule_template = """\ +// NOTE: This file is generated; do not edit by hand. + +module core_selector + ( + input wire sys_clk, + input wire sys_rst_n, + + input wire [16: 0] sys_eim_addr, + input wire sys_eim_wr, + input wire sys_eim_rd, + output wire [31: 0] sys_read_data, + input wire [31: 0] sys_write_data, + output wire sys_error, + + input wire noise, + output wire [7 : 0] debug + ); + + + //---------------------------------------------------------------- + // Address Decoder + //---------------------------------------------------------------- + // upper 9 bits specify core being addressed + wire [ 8: 0] addr_core_num = sys_eim_addr[16: 8]; + // lower 8 bits specify register offset in core + wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; + + + //---------------------------------------------------------------- + // Core Address Table + //---------------------------------------------------------------- +{addrs} + +{insts} + //---------------------------------------------------------------- + // Output (Read Data) Multiplexer + //---------------------------------------------------------------- + reg [31: 0] sys_read_data_mux; + assign sys_read_data = sys_read_data_mux; + reg sys_error_mux; + assign sys_error = sys_error_mux; + + always @* + + case (addr_core_num) +{muxes} + default: + begin + sys_read_data_mux = {{32{{1'b0}}}}; + sys_error_mux = 1; + end + endcase + + +endmodule + + +//====================================================================== +// EOF core_selector.v +//====================================================================== +""" + +# Template for makefile snippet listing Verilog source files. + +listVfiles_template = """\ +# NOTE: This file is generated; do not edit by hand. + +vfiles +={vfiles} +""" + +# Run main program. + +if __name__ == "__main__": + main() diff --git a/config/core_selector.v b/config/core_selector.v new file mode 100644 index 0000000..298c39e --- /dev/null +++ b/config/core_selector.v @@ -0,0 +1,278 @@ +// NOTE: This file is generated; do not edit by hand. + +module core_selector + ( + input wire sys_clk, + input wire sys_rst_n, + + input wire [16: 0] sys_eim_addr, + input wire sys_eim_wr, + input wire sys_eim_rd, + output wire [31: 0] sys_read_data, + input wire [31: 0] sys_write_data, + output wire sys_error, + + input wire noise, + output wire [7 : 0] debug + ); + + + //---------------------------------------------------------------- + // Address Decoder + //---------------------------------------------------------------- + // upper 9 bits specify core being addressed + wire [ 8: 0] addr_core_num = sys_eim_addr[16: 8]; + // lower 8 bits specify register offset in core + wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; + + + //---------------------------------------------------------------- + // Core Address Table + //---------------------------------------------------------------- + localparam CORE_ADDR_BOARD_REGS = 9'h00; + localparam CORE_ADDR_COMM_REGS = 9'h01; + localparam CORE_ADDR_SHA256 = 9'h02; + localparam CORE_ADDR_AES = 9'h03; + localparam CORE_ADDR_TRNG = 9'h04; + localparam CORE_ADDR_AVALANCHE_ENTROPY = 9'h05; + localparam CORE_ADDR_ROSC_ENTROPY = 9'h06; + localparam CORE_ADDR_TRNG_MIXER = 9'h07; + localparam CORE_ADDR_TRNG_CSPRNG = 9'h08; + localparam CORE_ADDR_MODEXPS6 = 9'h14; + + + //---------------------------------------------------------------- + // BOARD_REGS + //---------------------------------------------------------------- + wire enable_board_regs = (addr_core_num == CORE_ADDR_BOARD_REGS); + wire [31: 0] read_data_board_regs; + wire error_board_regs; + + board_regs board_regs_inst + ( + .clk(sys_clk), + .reset_n(sys_rst_n), + + .cs(enable_board_regs & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address(addr_core_reg), + .write_data(sys_write_data), + .read_data(read_data_board_regs), + .error(error_board_regs) + ); + + reg [31: 0] read_data_board_regs_reg; + always @(posedge sys_clk) + read_data_board_regs_reg <= read_data_board_regs; + + + //---------------------------------------------------------------- + // COMM_REGS + //---------------------------------------------------------------- + wire enable_comm_regs = (addr_core_num == CORE_ADDR_COMM_REGS); + wire [31: 0] read_data_comm_regs; + wire error_comm_regs; + + comm_regs comm_regs_inst + ( + .clk(sys_clk), + .reset_n(sys_rst_n), + + .cs(enable_comm_regs & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address(addr_core_reg), + .write_data(sys_write_data), + .read_data(read_data_comm_regs), + .error(error_comm_regs) + ); + + reg [31: 0] read_data_comm_regs_reg; + always @(posedge sys_clk) + read_data_comm_regs_reg <= read_data_comm_regs; + + + //---------------------------------------------------------------- + // SHA256 + //---------------------------------------------------------------- + wire enable_sha256 = (addr_core_num == CORE_ADDR_SHA256); + wire [31: 0] read_data_sha256; + wire error_sha256; + + sha256 sha256_inst + ( + .clk(sys_clk), + .reset_n(sys_rst_n), + + .cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address(addr_core_reg), + .write_data(sys_write_data), + .read_data(read_data_sha256), + .error(error_sha256) + ); + + reg [31: 0] read_data_sha256_reg; + always @(posedge sys_clk) + read_data_sha256_reg <= read_data_sha256; + + + //---------------------------------------------------------------- + // AES + //---------------------------------------------------------------- + wire enable_aes = (addr_core_num == CORE_ADDR_AES); + wire [31: 0] read_data_aes; + wire error_aes; + + aes aes_inst + ( + .clk(sys_clk), + .reset_n(sys_rst_n), + + .cs(enable_aes & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address(addr_core_reg), + .write_data(sys_write_data), + .read_data(read_data_aes), + .error(error_aes) + ); + + reg [31: 0] read_data_aes_reg; + always @(posedge sys_clk) + read_data_aes_reg <= read_data_aes; + + + //---------------------------------------------------------------- + // TRNG + //---------------------------------------------------------------- + wire enable_trng = (addr_core_num >= CORE_ADDR_TRNG) && (addr_core_num <= CORE_ADDR_TRNG + 9'h0f); + wire [31: 0] read_data_trng; + wire error_trng; + wire [3:0] trng_prefix = addr_core_num[3:0] - CORE_ADDR_TRNG; + + trng trng_inst + ( + .clk(sys_clk), + .reset_n(sys_rst_n), + + .cs(enable_trng & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address({trng_prefix, addr_core_reg}), + .write_data(sys_write_data), + .read_data(read_data_trng), + .error(error_trng), + + .avalanche_noise(noise), + .debug(debug) + ); + + reg [31: 0] read_data_trng_reg; + always @(posedge sys_clk) + read_data_trng_reg <= read_data_trng; + + + //---------------------------------------------------------------- + // MODEXPS6 + //---------------------------------------------------------------- + wire enable_modexps6 = (addr_core_num >= CORE_ADDR_MODEXPS6) && (addr_core_num <= CORE_ADDR_MODEXPS6 + 9'h03); + wire [31: 0] read_data_modexps6; + wire [1:0] modexps6_prefix = addr_core_num[1:0] - CORE_ADDR_MODEXPS6; + + modexps6_wrapper modexps6_inst + ( + .clk(sys_clk), + .reset_n(sys_rst_n), + + .cs(enable_modexps6 & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address({modexps6_prefix, addr_core_reg}), + .write_data(sys_write_data), + .read_data(read_data_modexps6) + ); + + + + //---------------------------------------------------------------- + // Output (Read Data) Multiplexer + //---------------------------------------------------------------- + reg [31: 0] sys_read_data_mux; + assign sys_read_data = sys_read_data_mux; + reg sys_error_mux; + assign sys_error = sys_error_mux; + + always @* + + case (addr_core_num) + CORE_ADDR_BOARD_REGS: + begin + sys_read_data_mux = read_data_board_regs_reg; + sys_error_mux = error_board_regs; + end + CORE_ADDR_COMM_REGS: + begin + sys_read_data_mux = read_data_comm_regs_reg; + sys_error_mux = error_comm_regs; + end + CORE_ADDR_SHA256: + begin + sys_read_data_mux = read_data_sha256_reg; + sys_error_mux = error_sha256; + end + CORE_ADDR_AES: + begin + sys_read_data_mux = read_data_aes_reg; + sys_error_mux = error_aes; + end + CORE_ADDR_TRNG: + begin + sys_read_data_mux = read_data_trng_reg; + sys_error_mux = error_trng; + end + CORE_ADDR_AVALANCHE_ENTROPY: + begin + sys_read_data_mux = read_data_trng_reg; + sys_error_mux = error_trng; + end + CORE_ADDR_ROSC_ENTROPY: + begin + sys_read_data_mux = read_data_trng_reg; + sys_error_mux = error_trng; + end + CORE_ADDR_TRNG_MIXER: + begin + sys_read_data_mux = read_data_trng_reg; + sys_error_mux = error_trng; + end + CORE_ADDR_TRNG_CSPRNG: + begin + sys_read_data_mux = read_data_trng_reg; + sys_error_mux = error_trng; + end + CORE_ADDR_MODEXPS6 + 0, + CORE_ADDR_MODEXPS6 + 1, + CORE_ADDR_MODEXPS6 + 2, + CORE_ADDR_MODEXPS6 + 3: + begin + sys_read_data_mux = read_data_modexps6; + sys_error_mux = 0; + end + + default: + begin + sys_read_data_mux = {32{1'b0}}; + sys_error_mux = 1; + end + endcase + + +endmodule + + +//====================================================================== +// EOF core_selector.v +//====================================================================== diff --git a/config/core_vfiles.mk b/config/core_vfiles.mk new file mode 100644 index 0000000..4020234 --- /dev/null +++ b/config/core_vfiles.mk @@ -0,0 +1,42 @@ +# NOTE: This file is generated; do not edit by hand. + +vfiles += \ + $(CORE_TREE)/hash/sha256/src/rtl/sha256.v \ + $(CORE_TREE)/hash/sha256/src/rtl/sha256_core.v \ + $(CORE_TREE)/hash/sha256/src/rtl/sha256_k_constants.v \ + $(CORE_TREE)/hash/sha256/src/rtl/sha256_w_mem.v \ + $(CORE_TREE)/cipher/aes/src/rtl/aes.v \ + $(CORE_TREE)/cipher/aes/src/rtl/aes_core.v \ + $(CORE_TREE)/cipher/aes/src/rtl/aes_decipher_block.v \ + $(CORE_TREE)/cipher/aes/src/rtl/aes_encipher_block.v \ + $(CORE_TREE)/cipher/aes/src/rtl/aes_inv_sbox.v \ + $(CORE_TREE)/cipher/aes/src/rtl/aes_key_mem.v \ + $(CORE_TREE)/cipher/aes/src/rtl/aes_sbox.v \ + $(CORE_TREE)/rng/avalanche_entropy/src/rtl/avalanche_entropy.v \ + $(CORE_TREE)/rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v \ + $(CORE_TREE)/rng/rosc_entropy/src/rtl/rosc.v \ + $(CORE_TREE)/rng/rosc_entropy/src/rtl/rosc_entropy.v \ + $(CORE_TREE)/rng/rosc_entropy/src/rtl/rosc_entropy_core.v \ + $(CORE_TREE)/rng/trng/src/rtl/trng.v \ + $(CORE_TREE)/rng/trng/src/rtl/trng_csprng.v \ + $(CORE_TREE)/rng/trng/src/rtl/trng_csprng_fifo.v \ + $(CORE_TREE)/rng/trng/src/rtl/trng_mixer.v \ + $(CORE_TREE)/cipher/chacha/src/rtl/chacha.v \ + $(CORE_TREE)/cipher/chacha/src/rtl/chacha_core.v \ + $(CORE_TREE)/cipher/chacha/src/rtl/chacha_qr.v \ + $(CORE_TREE)/hash/sha512/src/rtl/sha512.v \ + $(CORE_TREE)/hash/sha512/src/rtl/sha512_core.v \ + $(CORE_TREE)/hash/sha512/src/rtl/sha512_h_constants.v \ + $(CORE_TREE)/hash/sha512/src/rtl/sha512_k_constants.v \ + $(CORE_TREE)/hash/sha512/src/rtl/sha512_w_mem.v \ + $(CORE_TREE)/math/modexps6/src/rtl/modexps6_adder64_carry32.v \ + $(CORE_TREE)/math/modexps6/src/rtl/modexps6_buffer_core.v \ + $(CORE_TREE)/math/modexps6/src/rtl/modexps6_buffer_user.v \ + $(CORE_TREE)/math/modexps6/src/rtl/modexps6_modinv32.v \ + $(CORE_TREE)/math/modexps6/src/rtl/modexps6_montgomery_coeff.v \ + $(CORE_TREE)/math/modexps6/src/rtl/modexps6_montgomery_multiplier.v \ + $(CORE_TREE)/math/modexps6/src/rtl/modexps6_top.v \ + $(CORE_TREE)/math/modexps6/src/rtl/modexps6_wrapper.v \ + $(CORE_TREE)/math/modexps6/src/rtl/ram_1rw_1ro_readfirst.v \ + $(CORE_TREE)/math/modexps6/src/rtl/ipcore/multiplier_s6.v \ + $(CORE_TREE)/math/modexps6/src/rtl/ipcore/subtractor_s6.v diff --git a/core_selector/src/rtl/cipher_selector.v b/core_selector/src/rtl/cipher_selector.v deleted file mode 100644 index a8de37e..0000000 --- a/core_selector/src/rtl/cipher_selector.v +++ /dev/null @@ -1,168 +0,0 @@ -//====================================================================== -// -// cipher_selector.v -// ----------------- -// Top level wrapper that creates the Cryptech coretest system. -// The wrapper contains instances of external interface, coretest -// and the core to be tested. And if more than one core is -// present the wrapper also includes address and data muxes. -// -// -// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov -// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -module cipher_selector - ( - input wire sys_clk, - input wire sys_rst_n, - input wire sys_ena, - - input wire [13: 0] sys_eim_addr, - input wire sys_eim_wr, - input wire sys_eim_rd, - output wire [31 : 0] sys_read_data, - input wire [31 : 0] sys_write_data, - output wire sys_error - ); - - //---------------------------------------------------------------- - // Address Decoder - //---------------------------------------------------------------- - // upper 6 bits specify core being addressed - wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8]; - // lower 8 bits specify register offset in core - wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; - - - //---------------------------------------------------------------- - // List of Available Cores - //---------------------------------------------------------------- - // Comment following lines to exclude cores from implementation. - `define USE_CORE_AES - `define USE_CORE_CHACHA - - - //---------------------------------------------------------------- - // Core Address Table - //---------------------------------------------------------------- - localparam CORE_ADDR_AES = 6'd0; - localparam CORE_ADDR_CHACHA = 6'd1; - - - //---------------------------------------------------------------- - // AES - //---------------------------------------------------------------- - `ifdef USE_CORE_AES - wire enable_aes = sys_ena && (addr_core_num == CORE_ADDR_AES); - wire [31: 0] read_data_aes; - wire error_aes; - - aes aes_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_aes & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_aes), - .error(error_aes) - ); - `endif - - - //---------------------------------------------------------------- - // CHACHA - //---------------------------------------------------------------- - `ifdef USE_CORE_CHACHA - wire enable_chacha = sys_ena && (addr_core_num == CORE_ADDR_CHACHA); - wire [31: 0] read_data_chacha; - wire error_chacha; - - chacha chacha_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_chacha & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_chacha), - .error(error_chacha) - ); - `endif - - - //---------------------------------------------------------------- - // Output (Read Data) Multiplexor - //---------------------------------------------------------------- - reg [31: 0] sys_read_data_mux; - assign sys_read_data = sys_read_data_mux; - reg sys_error_mux; - assign sys_error = sys_error_mux; - - always @* - // - case (addr_core_num) - // - `ifdef USE_CORE_AES - CORE_ADDR_AES: - begin - sys_read_data_mux = read_data_aes; - sys_error_mux = error_aes; - end - `endif - `ifdef USE_CORE_CHACHA - CORE_ADDR_CHACHA: - begin - sys_read_data_mux = read_data_chacha; - sys_error_mux = error_chacha; - end - `endif - // - default: - begin - sys_read_data_mux = {32{1'b0}}; - sys_error_mux = 1; - end - // - endcase - - -endmodule - -//====================================================================== -// EOF cipher_selector.v -//====================================================================== diff --git a/core_selector/src/rtl/core_selector.v b/core_selector/src/rtl/core_selector.v deleted file mode 100644 index 9607cb3..0000000 --- a/core_selector/src/rtl/core_selector.v +++ /dev/null @@ -1,307 +0,0 @@ -//====================================================================== -// -// core_selector.v -// --------------- -// Top level wrapper that creates the Cryptech coretest system. -// The wrapper contains instances of external interface, coretest -// and the core to be tested. And if more than one core is -// present the wrapper also includes address and data muxes. -// -// -// Author: Pavel Shatov -// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -module core_selector - ( - input wire sys_clk, - input wire sys_rst_n, - - input wire [16: 0] sys_eim_addr, - input wire sys_eim_wr, - input wire sys_eim_rd, - output wire [31: 0] sys_read_data, - input wire [31: 0] sys_write_data, - output wire sys_error, - - input wire noise, - output wire [7 : 0] debug - ); - - - /* Three upper bits of address [16:14] are used to select memory segment. - * There can be eight segments. So far segment 0 is used for global - * registers, segment 1 is used for hashes, segment 2 is reserved for - * random number generators, segment 3 is reserved for chiphers. Other - * segments are not used so far. - */ - - /* Every segment has its own memory map, take at look at corresponding - * selectors for more information. - */ - - //---------------------------------------------------------------- - // Address Decoder - //---------------------------------------------------------------- - // 3 upper bits are decoded here - wire [ 2: 0] addr_segment = sys_eim_addr[16:14]; - // 14 lower bits are decoded in corresponding segment selectors - wire [13: 0] addr_segment_int = sys_eim_addr[13: 0]; - - - //---------------------------------------------------------------- - // List of Available Segments - //---------------------------------------------------------------- - // Comment following lines to exclude segments from implementation. - `define USE_SEGMENT_GLOBALS - `define USE_SEGMENT_HASHES - `define USE_SEGMENT_RNGS - `define USE_SEGMENT_CIPHERS - `define USE_SEGMENT_MATH - - - //---------------------------------------------------------------- - // Segment Address Table - //---------------------------------------------------------------- - localparam SEGMENT_ADDR_GLOBALS = 3'd0; - localparam SEGMENT_ADDR_HASHES = 3'd1; - localparam SEGMENT_ADDR_RNGS = 3'd2; - localparam SEGMENT_ADDR_CIPHERS = 3'd3; - localparam SEGMENT_ADDR_MATH = 3'd4; - - - //---------------------------------------------------------------- - // GLOBALS Segment - //---------------------------------------------------------------- - `ifdef USE_SEGMENT_GLOBALS - wire segment_enable_globals = (addr_segment == SEGMENT_ADDR_GLOBALS) ? 1'b1 : 1'b0; - wire [31: 0] segment_globals_read_data; - wire segment_globals_error; - - global_selector globals - ( - .sys_clk(sys_clk), - .sys_rst_n(sys_rst_n), - .sys_ena(segment_enable_globals), - - .sys_eim_addr(addr_segment_int), - .sys_eim_wr(sys_eim_wr), - .sys_eim_rd(sys_eim_rd), - .sys_write_data(sys_write_data), - .sys_read_data(segment_globals_read_data), - .sys_error(segment_globals_error) - ); - - reg [31: 0] segment_globals_read_data_reg; - always @(posedge sys_clk) - segment_globals_read_data_reg <= segment_globals_read_data; - - `endif - - - //---------------------------------------------------------------- - // HASHES Segment - //---------------------------------------------------------------- - `ifdef USE_SEGMENT_HASHES - wire segment_enable_hashes = (addr_segment == SEGMENT_ADDR_HASHES) ? 1'b1 : 1'b0; - wire [31: 0] segment_hashes_read_data; - wire segment_hashes_error; - - hash_selector hashes - ( - .sys_clk(sys_clk), - .sys_rst_n(sys_rst_n), - .sys_ena(segment_enable_hashes), - - .sys_eim_addr(addr_segment_int), - .sys_eim_wr(sys_eim_wr), - .sys_eim_rd(sys_eim_rd), - .sys_write_data(sys_write_data), - .sys_read_data(segment_hashes_read_data), - .sys_error(segment_hashes_error) - ); - - reg [31: 0] segment_hashes_read_data_reg; - always @(posedge sys_clk) - segment_hashes_read_data_reg <= segment_hashes_read_data; - - `endif - - - //---------------------------------------------------------------- - // RNGS Segment - //---------------------------------------------------------------- - `ifdef USE_SEGMENT_RNGS - wire segment_enable_rngs = (addr_segment == SEGMENT_ADDR_RNGS) ? 1'b1 : 1'b0; - wire [31: 0] segment_rngs_read_data; - wire segment_rngs_error; - wire [7 : 0] segment_rngs_debug; - - rng_selector rngs - ( - .sys_clk(sys_clk), - .sys_rst_n(sys_rst_n), - .sys_ena(segment_enable_rngs), - - .sys_eim_addr(addr_segment_int), - .sys_eim_wr(sys_eim_wr), - .sys_eim_rd(sys_eim_rd), - .sys_write_data(sys_write_data), - .sys_read_data(segment_rngs_read_data), - .sys_error(segment_rngs_error), - - .noise(noise), // only RNG segment uses these ports - .debug(segment_rngs_debug) - ); - - reg [31: 0] segment_rngs_read_data_reg; - always @(posedge sys_clk) - segment_rngs_read_data_reg <= segment_rngs_read_data; - - `endif - - - //---------------------------------------------------------------- - // CIPHERS Segment - //---------------------------------------------------------------- - `ifdef USE_SEGMENT_CIPHERS - wire segment_enable_ciphers = (addr_segment == SEGMENT_ADDR_CIPHERS) ? 1'b1 : 1'b0; - wire [31: 0] segment_ciphers_read_data; - - cipher_selector ciphers - ( - .sys_clk(sys_clk), - .sys_rst_n(sys_rst_n), - .sys_ena(segment_enable_ciphers), - - .sys_eim_addr(addr_segment_int), - .sys_eim_wr(sys_eim_wr), - .sys_eim_rd(sys_eim_rd), - .sys_write_data(sys_write_data), - .sys_read_data(segment_ciphers_read_data), - .sys_error(segment_ciphers_error) - ); - - reg [31: 0] segment_ciphers_read_data_reg; - always @(posedge sys_clk) - segment_ciphers_read_data_reg <= segment_ciphers_read_data; - - `endif - - - //---------------------------------------------------------------- - // MATH Segment - //---------------------------------------------------------------- - `ifdef USE_SEGMENT_MATH - wire segment_enable_math = (addr_segment == SEGMENT_ADDR_MATH) ? 1'b1 : 1'b0; - wire [31: 0] segment_math_read_data; - - math_selector maths - ( - .sys_clk(sys_clk), - .sys_rst_n(sys_rst_n), - .sys_ena(segment_enable_math), - - .sys_eim_addr(addr_segment_int), - .sys_eim_wr(sys_eim_wr), - .sys_eim_rd(sys_eim_rd), - .sys_write_data(sys_write_data), - .sys_read_data(segment_math_read_data) - ); - `endif - - - //---------------------------------------------------------------- - // Output (Read Data) Bus - //---------------------------------------------------------------- - reg [31: 0] sys_read_data_reg; - reg [07: 0] sys_debug; - reg sys_error_reg; - - assign sys_read_data = sys_read_data_reg; - assign sys_error = sys_error_reg; - assign debug = sys_debug; - - always @* - begin : output_select - sys_debug = 8'h00; - sys_read_data_reg = {32{1'b0}}; - sys_error_reg = 1; - sys_debug = 8'h00; - - case (addr_segment) - `ifdef USE_SEGMENT_GLOBALS - SEGMENT_ADDR_GLOBALS: - begin - sys_read_data_reg = segment_globals_read_data_reg; - sys_error_reg = segment_globals_error; - end - `endif - `ifdef USE_SEGMENT_HASHES - SEGMENT_ADDR_HASHES: - begin - sys_read_data_reg = segment_hashes_read_data_reg; - sys_error_reg = segment_hashes_error; - end - `endif - `ifdef USE_SEGMENT_RNGS - SEGMENT_ADDR_RNGS: - begin - sys_read_data_reg = segment_rngs_read_data_reg; - sys_error_reg = segment_rngs_error; - sys_debug = segment_rngs_debug; - end - `endif - `ifdef USE_SEGMENT_CIPHERS - SEGMENT_ADDR_CIPHERS: - begin - sys_read_data_reg = segment_ciphers_read_data_reg; - sys_error_reg = segment_ciphers_error; - end - `endif - `ifdef USE_SEGMENT_MATH - SEGMENT_ADDR_MATH: - begin - sys_read_data_reg = segment_math_read_data; - sys_error_reg = 0; - end - `endif - default: - begin - end - endcase - end // output_select - -endmodule - - -//====================================================================== -// EOF core_selector.v -//====================================================================== diff --git a/core_selector/src/rtl/global_selector.v b/core_selector/src/rtl/global_selector.v deleted file mode 100644 index 2b9e20a..0000000 --- a/core_selector/src/rtl/global_selector.v +++ /dev/null @@ -1,153 +0,0 @@ -//====================================================================== -// -// global_selector.v -// ----------------- -// Top level wrapper that creates the Cryptech coretest system. -// The wrapper contains instances of external interface, coretest -// and the core to be tested. And if more than one core is -// present the wrapper also includes address and data muxes. -// -// -// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov -// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -module global_selector - ( - input wire sys_clk, - input wire sys_rst_n, - input wire sys_ena, - - input wire [13: 0] sys_eim_addr, - input wire sys_eim_wr, - input wire sys_eim_rd, - output wire [31 : 0] sys_read_data, - input wire [31 : 0] sys_write_data, - output wire sys_error - ); - - - //---------------------------------------------------------------- - // Address Decoder - //---------------------------------------------------------------- - // upper 6 bits specify core being addressed - wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8]; - // lower 8 bits specify register offset in core - wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; - - - //---------------------------------------------------------------- - // Core Address Table - //---------------------------------------------------------------- - localparam CORE_ADDR_BOARD_REGS = 6'd0; - localparam CORE_ADDR_COMM_REGS = 6'd1; - - - //---------------------------------------------------------------- - // Board-Level Registers - //---------------------------------------------------------------- - wire [31: 0] read_data_board; - wire enable_board = sys_ena && (addr_core_num == CORE_ADDR_BOARD_REGS); - wire error_board; - - board_regs board_regs - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_board & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_board), - .error(error_board) - ); - - - //---------------------------------------------------------------- - // Communication-Channel Registers - //---------------------------------------------------------------- - wire [31: 0] read_data_comm; - wire enable_comm = sys_ena && (addr_core_num == CORE_ADDR_COMM_REGS); - wire error_comm; - - comm_regs comm_regs - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_comm & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_comm), - .error(error_comm) - ); - - - //---------------------------------------------------------------- - // Output (Read Data) Multiplexor - //---------------------------------------------------------------- - reg [31: 0] sys_read_data_mux; - assign sys_read_data = sys_read_data_mux; - reg sys_error_mux; - assign sys_error = sys_error_mux; - - always @* - // - case (addr_core_num) - // - CORE_ADDR_BOARD_REGS: - begin - sys_read_data_mux = read_data_board; - sys_error_mux = error_board; - end - CORE_ADDR_COMM_REGS: - begin - sys_read_data_mux = read_data_comm; - sys_error_mux = error_comm; - end - // - default: - begin - sys_read_data_mux = {32{1'b0}}; - sys_error_mux = 1; - end - // - endcase - - -endmodule - -//====================================================================== -// EOF global_selector.v -//====================================================================== diff --git a/core_selector/src/rtl/hash_selector.v b/core_selector/src/rtl/hash_selector.v deleted file mode 100644 index 81fac7d..0000000 --- a/core_selector/src/rtl/hash_selector.v +++ /dev/null @@ -1,260 +0,0 @@ -//====================================================================== -// -// hash_selector.v -// --------------- -// Top level wrapper that creates the Cryptech coretest system. -// The wrapper contains instances of external interface, coretest -// and the core to be tested. And if more than one core is -// present the wrapper also includes address and data muxes. -// -// -// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov -// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -module hash_selector - ( - input wire sys_clk, - input wire sys_rst_n, - input wire sys_ena, - - input wire [13 : 0] sys_eim_addr, - input wire sys_eim_wr, - input wire sys_eim_rd, - output wire [31 : 0] sys_read_data, - input wire [31 : 0] sys_write_data, - output wire sys_error - ); - - /* In this memory segment (HASHES) we have 14 address bits. Every core has - * 8-bit internal address space, so we can have up to 2^(14-8) = 64 cores here. - * - * So far we have three cores: SHA-1, SHA-256 and SHA-512. - */ - - /********************************************************* - * To add new HASH core named XXX follow the steps below * - ********************************************************* - * - * 1. Add corresponding `define under "List of Available Cores", this will - * allow users to exclude your core from implementation to save some - * slices in case they don't need it. - * - * `define USE_CORE_XXX -XXX define in wrapper core - * - * - * 2. Choose address of your new core and add corresponding line under - * "Core Address Table". Core addresses can be in the range from 0 to 63 - * inclusively. - * - * localparam CORE_ADDR_XXX = 6'dN; -XXX move to `define in wrapper core?? - * - * - * 3. Add instantiation of your new core after all existing cores - * surrounded by conditional synthesis directives. - * You also need a 32-bit output (read data) bus for your core and an - * enable flag. Note that sys_rst_n in an active-low sync reset signal. - * - * `ifdef USE_CORE_XXX - * wire [31: 0] read_data_xxx; - * wire enable_xxx = sys_ena && (addr_core_num == CORE_ADDR_XXX); - * xxx xxx_inst - * ( - * .clk(sys_clk), - * .reset_n(sys_rst_n), - * .cs(enable_xxx & (sys_eim_rd | sys_eim_wr)), - * .we(sys_eim_wr), - * .address(addr_core_reg), - * .write_data(sys_write_data), - * .read_data(read_data_xxx), - * .error() - * ); - * `endif - * - * - * 4. Add previously created data bus to "Output (Read Data) Multiplexor" - * in the end of this file. - * - * `ifdef USE_CORE_XXX - * CORE_ADDR_XXX: - * sys_read_data_mux = read_data_xxx; - * `endif - * - */ - - - //---------------------------------------------------------------- - // Address Decoder - //---------------------------------------------------------------- - // upper 6 bits specify core being addressed - wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8]; - // lower 8 bits specify register offset in core - wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; - - - //---------------------------------------------------------------- - // List of Available Cores - //---------------------------------------------------------------- - // Comment following lines to exclude cores from implementation. - `define USE_CORE_SHA1 - `define USE_CORE_SHA256 - `define USE_CORE_SHA512 - - - //---------------------------------------------------------------- - // Core Address Table - //---------------------------------------------------------------- - localparam CORE_ADDR_SHA1 = 6'd0; - localparam CORE_ADDR_SHA256 = 6'd1; - localparam CORE_ADDR_SHA512 = 6'd2; - - - //---------------------------------------------------------------- - // SHA-1 - //---------------------------------------------------------------- - `ifdef USE_CORE_SHA1 - wire enable_sha1 = sys_ena && (addr_core_num == CORE_ADDR_SHA1); - wire [31: 0] read_data_sha1; - wire error_sha1; - - sha1 sha1_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_sha1 & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_sha1), - .error(error_sha1) - ); - `endif - - - //---------------------------------------------------------------- - // SHA-256 - //---------------------------------------------------------------- - `ifdef USE_CORE_SHA256 - wire enable_sha256 = sys_ena && (addr_core_num == CORE_ADDR_SHA256); - wire [31: 0] read_data_sha256; - wire error_sha256; - - sha256 sha256_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_sha256), - .error(error_sha256) - ); - `endif - - - //---------------------------------------------------------------- - // SHA-512 - //---------------------------------------------------------------- - `ifdef USE_CORE_SHA512 - wire enable_sha512 = sys_ena && (addr_core_num == CORE_ADDR_SHA512); - wire [31: 0] read_data_sha512; - wire error_sha512; - - sha512 sha512_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_sha512 & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_sha512), - .error(error_sha512) - ); - `endif - - - //---------------------------------------------------------------- - // Output (Read Data) Multiplexor - //---------------------------------------------------------------- - reg [31: 0] sys_read_data_mux; - assign sys_read_data = sys_read_data_mux; - reg sys_error_mux; - assign sys_error = sys_error_mux; - - always @* - // - case (addr_core_num) - // - `ifdef USE_CORE_SHA1 - CORE_ADDR_SHA1: - begin - sys_read_data_mux = read_data_sha1; - sys_error_mux = error_sha1; - end - `endif - `ifdef USE_CORE_SHA256 - CORE_ADDR_SHA256: - begin - sys_read_data_mux = read_data_sha256; - sys_error_mux = error_sha256; - end - `endif - `ifdef USE_CORE_SHA512 - CORE_ADDR_SHA512: - begin - sys_read_data_mux = read_data_sha512; - sys_error_mux = error_sha512; - end - `endif - // - default: - begin - sys_read_data_mux = {32{1'b0}}; - sys_error_mux = 1; - end - // - endcase - - -endmodule - -//====================================================================== -// EOF hash_selector.v -//====================================================================== diff --git a/core_selector/src/rtl/math_selector.v b/core_selector/src/rtl/math_selector.v deleted file mode 100644 index 8b8473a..0000000 --- a/core_selector/src/rtl/math_selector.v +++ /dev/null @@ -1,129 +0,0 @@ -//====================================================================== -// -// math_selector.v -// --------------- -// Selector of math cores. Currently there is only one core in math - -// the modexp core. That core uses 12 bits and we simply ignore the -// top two bits of the address. If we add more math cores we will -// use these bits to select cores here. -// -// -// -// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov -// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -module math_selector - ( - input wire sys_clk, - input wire sys_rst_n, - input wire sys_ena, - - input wire [13: 0] sys_eim_addr, - input wire sys_eim_wr, - input wire sys_eim_rd, - output wire [31 : 0] sys_read_data, - input wire [31 : 0] sys_write_data - ); - - - //---------------------------------------------------------------- - // List of Available Cores - //---------------------------------------------------------------- - // Comment following lines to exclude cores from implementation. - `define USE_CORE_MODEXPS6 - - - //---------------------------------------------------------------- - // Address Decoder - //---------------------------------------------------------------- -`ifdef USE_CORE_MODEXPS6 - // upper 4 bits specify core being addressed - wire [ 3: 0] addr_core_num = sys_eim_addr[13:10]; - // lower 10 bits specify register offset in core - wire [ 9: 0] addr_core_reg = sys_eim_addr[ 9: 0]; -`endif - - - //---------------------------------------------------------------- - // Core Address Table - //---------------------------------------------------------------- - `ifdef USE_CORE_MODEXPS6 - localparam CORE_ADDR_MODEXPS6 = 4'd0; - `endif - - - //---------------------------------------------------------------- - // ModExpS6 - //---------------------------------------------------------------- - `ifdef USE_CORE_MODEXPS6 - wire [31: 0] read_data_modexps6; - wire enable_modexps6 = sys_ena && (addr_core_num == CORE_ADDR_MODEXPS6); - modexps6_wrapper modexps6_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(enable_modexps6 & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(addr_core_reg), - .write_data(sys_write_data), - .read_data(read_data_modexps6) - ); - `endif - - - //---------------------------------------------------------------- - // Output (Read Data) Multiplexor - //---------------------------------------------------------------- - reg [31: 0] sys_read_data_mux; - assign sys_read_data = sys_read_data_mux; - - always @* - // - `ifdef USE_CORE_MODEXPS6 - if (addr_core_num == CORE_ADDR_MODEXPS6) - begin - sys_read_data_mux = read_data_modexps6; - end - else - `endif - // - begin - sys_read_data_mux = {32{1'b0}}; - end - - -endmodule - -//====================================================================== -// EOF math_selector.v -//====================================================================== diff --git a/core_selector/src/rtl/rng_selector.v b/core_selector/src/rtl/rng_selector.v deleted file mode 100644 index 82f0e9b..0000000 --- a/core_selector/src/rtl/rng_selector.v +++ /dev/null @@ -1,84 +0,0 @@ -//====================================================================== -// -// rng_selector.v -// ----------------- -// Top level wrapper that creates the Cryptech coretest system. -// The wrapper contains instances of external interface, coretest -// and the core to be tested. And if more than one core is -// present the wrapper also includes address and data muxes. -// -// -// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov -// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// - Neither the name of the NORDUnet nor the names of its contributors may -// be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//====================================================================== - -module rng_selector - ( - input wire sys_clk, - input wire sys_rst_n, - input wire sys_ena, - - input wire [13: 0] sys_eim_addr, - input wire sys_eim_wr, - input wire sys_eim_rd, - output wire [31 : 0] sys_read_data, - input wire [31 : 0] sys_write_data, - output wire sys_error, - - input wire noise, - output wire [7 : 0] debug - ); - - - // This is a pass-through to trng.v, which instantiates and muxes the - // entropy sources, mixer, and csprng. - - trng trng_inst - ( - .clk(sys_clk), - .reset_n(sys_rst_n), - - .cs(sys_ena & (sys_eim_rd | sys_eim_wr)), - .we(sys_eim_wr), - - .address(sys_eim_addr[11:0]), - .write_data(sys_write_data), - .read_data(sys_read_data), - .error(sys_error), - - .avalanche_noise(noise), - .debug(debug) - ); - -endmodule - -//====================================================================== -// EOF rng_selector.v -//====================================================================== |