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authorPaul Selkirk <paul@psgd.org>2016-05-17 17:47:03 +0200
committerPaul Selkirk <paul@psgd.org>2016-05-17 17:47:03 +0200
commit2f4a3aaf057b21a830112461d77bd4717ac41737 (patch)
treed03f88f4394f3179f80dc015540b8ffdd2d69fd1 /config
parent8b8b5d3fbe90e9164d9e692e4368e50ce77c2fbb (diff)
add the new mkmif core
Diffstat (limited to 'config')
-rw-r--r--config/config.cfg10
-rwxr-xr-xconfig/config.py59
2 files changed, 66 insertions, 3 deletions
diff --git a/config/config.cfg b/config/config.cfg
index 337ebe5..d3834d6 100644
--- a/config/config.cfg
+++ b/config/config.cfg
@@ -44,6 +44,9 @@ cores = modexps6
[rsa]
cores = sha256 aes trng modexps6
+[mkmif]
+cores = mkmif
+
# include multiple of the same core
[multi-test]
cores = sha256 aes aes chacha aes
@@ -128,3 +131,10 @@ vfiles =
math/modexp/src/rtl/residue.v
math/modexp/src/rtl/shl.v
math/modexp/src/rtl/shr.v
+
+[mkmif]
+error_wire = no
+vfiles =
+ util/mkmif/src/rtl/mkmif.v
+ util/mkmif/src/rtl/mkmif_core.v
+ util/mkmif/src/rtl/mkmif_spi.v
diff --git a/config/config.py b/config/config.py
index acd75a1..5ff3ccc 100755
--- a/config/config.py
+++ b/config/config.py
@@ -103,7 +103,8 @@ def main():
args.verilog.write(createModule_template.format(
addrs = "".join(core.createAddr() for core in cores),
insts = "".join(core.createInstance() for core in cores),
- muxes = "".join(core.createMux() for core in cores)))
+ muxes = "".join(core.createMux() for core in cores),
+ ports = "".join(core.createPort() for core in cores) ))
args.makefile.write(listVfiles_template.format(
vfiles = "".join(core.listVfiles() for core in cores)))
@@ -224,6 +225,9 @@ class Core(object):
def createMux(self):
return createMux_template.format(core = self, core0 = self)
+ def createPort(self):
+ return ""
+
def listVfiles(self):
return "".join(" \\\n\t$(CORE_TREE)/" + vfile for vfile in self.vfiles)
@@ -302,12 +306,29 @@ class ModExpS6Core(Core):
def createMux(self):
return createMux_modexps6_template.format(core = self, core0 = self)
+class MkmifCore(Core):
+ """
+ MKM interface core has extra ports for the SPI signal lines.
+ """
+
+ def createPort(self):
+ return """ \
+
+ output wire mkm_sclk,
+ output wire mkm_cs_n,
+ input wire mkm_do,
+ output wire mkm_di,
+ """
+
+ def createInstance(self):
+ return createInstance_template_MKMIF.format(core = self)
# Hook special classes in as handlers for the cores that require them.
Core.special_class.update(
trng = TRNGCore,
- modexps6 = ModExpS6Core)
+ modexps6 = ModExpS6Core,
+ mkmif = MkmifCore)
# Templates (format strings), here instead of inline in the functions
@@ -409,6 +430,38 @@ createInstance_template_TRNG = """\
"""
+# Template used by Mkmif.createInstance(). This is different
+# enough from the base template that it's easier to make this separate.
+
+createInstance_template_MKMIF = """\
+ //----------------------------------------------------------------
+ // {core.upper_instance_name}
+ //----------------------------------------------------------------
+ wire enable_{core.instance_name} = (addr_core_num == CORE_ADDR_{core.upper_instance_name});
+ wire [31: 0] read_data_{core.instance_name};
+
+ {core.name} {core.instance_name}_inst
+ (
+ .clk(sys_clk),
+ {core.reset_pin},
+
+ .spi_sclk(mkm_sclk),
+ .spi_cs_n(mkm_cs_n),
+ .spi_do(mkm_do),
+ .spi_di(mkm_di),
+
+ .cs(enable_{core.instance_name} & (sys_eim_rd | sys_eim_wr)),
+ .we(sys_eim_wr),
+
+ .address(addr_core_reg),
+ .write_data(sys_write_data),
+ .read_data(read_data_{core.instance_name}){core.error_port}
+ );
+
+{core.one_cycle_delay}
+
+"""
+
# Template for one-cycle delay code.
one_cycle_delay_template = """\
@@ -457,7 +510,7 @@ module core_selector
output wire [31: 0] sys_read_data,
input wire [31: 0] sys_write_data,
output wire sys_error,
-
+{ports}
input wire noise,
output wire [7 : 0] debug
);