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authorRob Austein <sra@hactrn.net>2017-08-09 13:41:22 -0400
committerRob Austein <sra@hactrn.net>2017-08-09 13:41:22 -0400
commitddd80c35c032d1f1dda60e39559965a27255cdf0 (patch)
tree9f1383e0a9ed72fd4a37085fabbe2723256829a6 /config
parente3f8eac7d79352e58bf5ea231c18b9b17ac5bebd (diff)
reset_n vs rst_n, pax guys.
Diffstat (limited to 'config')
-rw-r--r--config/core.cfg4
-rwxr-xr-xconfig/core_config.py15
2 files changed, 13 insertions, 6 deletions
diff --git a/config/core.cfg b/config/core.cfg
index 361774a..5c43502 100644
--- a/config/core.cfg
+++ b/config/core.cfg
@@ -118,6 +118,9 @@ cores = mkmif trng sha1 sha1 sha1 sha256 sha256 sha256 sha512 sha512 sha512 aes
# *not* use block memory. When no cores in the build use block
# memory, the delay isn't necessary and is therefore omitted.
#
+# reset name: what name to use for the reset wire, because we don't
+# seem to be able to agree on whether this is "reset_n" or "rst_n".
+#
# extra ports: Extra port definitions in the core instance.
# Note this is a blob of text, not interpreted, so formatting and commas
# will be copied out verbatim.
@@ -189,6 +192,7 @@ core blocks = 4
block memory = yes
error wire = no
module name = modexpa7_wrapper
+reset name = rst_n
parameter OPERAND_ADDR_WIDTH = 7
parameter SYSTOLIC_ARRAY_POWER = 1
vfiles =
diff --git a/config/core_config.py b/config/core_config.py
index 4de8f16..4033279 100755
--- a/config/core_config.py
+++ b/config/core_config.py
@@ -158,16 +158,16 @@ class RawConfigParser(configparser.RawConfigParser):
for value in self.get(section, option).split():
yield value
- def get(self, section, option):
+ def get(self, section, option, default = ""):
try:
return configparser.RawConfigParser.get(self, section, option)
except configparser.NoSectionError:
if section in ("core board_regs", "core comm_regs"):
- return ""
+ return default
else:
raise
except configparser.NoOptionError:
- return ""
+ return default
class Core(object):
@@ -201,6 +201,9 @@ class Core(object):
self.subcores = []
self.blocks = 1
self.dummy = False
+ self._parameters = dict()
+ self.reset_name = "reset_n"
+
def assign_core_number(self, n):
self.core_number = n
@@ -235,11 +238,11 @@ class Core(object):
self.dummy = cfg.get(self.cfg_section, "dummy")
if self.dummy:
self.dummy = self.dummy.replace("\n", "\n ") + "\n"
- self._parameters = dict()
if cfg.has_section(self.cfg_section):
for option in cfg.options(self.cfg_section):
if option.startswith("parameter "):
self._parameters[option[len("parameter"):].upper().strip()] = cfg.get(self.cfg_section, option)
+ self.reset_name = cfg.get(self.cfg_section, "reset name", self.reset_name)
@property
def instance_name(self):
@@ -340,7 +343,7 @@ createInstance_template_generic = """\
{core.module_name} {core.parameters}{core.instance_name}_inst
(
.clk(sys_clk),
- .reset_n(sys_rst_n),
+ .{core.reset_name}(sys_rst_n),
{core.extra_ports}
.cs(enable_{core.instance_name} & (sys_{core.bus_name}_rd | sys_{core.bus_name}_wr)),
.we(sys_{core.bus_name}_wr),
@@ -368,7 +371,7 @@ createInstance_template_multi_block = """\
{core.module_name} {core.parameters}{core.instance_name}_inst
(
.clk(sys_clk),
- .reset_n(sys_rst_n),
+ .{core.reset_name}(sys_rst_n),
{core.extra_ports}
.cs(enable_{core.instance_name} & (sys_{core.bus_name}_rd | sys_{core.bus_name}_wr)),
.we(sys_{core.bus_name}_wr),