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authorJoachim StroĢˆmbergson <joachim@secworks.se>2015-04-27 13:45:25 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2015-04-27 13:45:25 +0200
commitecfe970a0644192547223eb100e8fa2d2c8243cc (patch)
tree09545f17da7a3961ba99f9e6262e04b42b41a435
parent75491745d24ce1e2f3b0da94edcea228196777d4 (diff)
(1) Added segment for math cores in the core selector. (2) Added specific math core selector module. This module instantiates the modexp core. (3) Minor cleanup of file headers. The core selector is not coretest for example.
-rw-r--r--core_selector/src/rtl/math_selector.v78
1 files changed, 78 insertions, 0 deletions
diff --git a/core_selector/src/rtl/math_selector.v b/core_selector/src/rtl/math_selector.v
new file mode 100644
index 0000000..3c29554
--- /dev/null
+++ b/core_selector/src/rtl/math_selector.v
@@ -0,0 +1,78 @@
+//======================================================================
+//
+// math_selector.v
+// ---------------
+// Selector of math cores. Currently there is only one core in math -
+// the modexp core. That core uses 12 bits and we simply ignore the
+// top two bits of the address. If we add more math cores we will
+// use these bits to select cores here.
+//
+//
+//
+// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov
+// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module math_selector
+ (
+ input wire sys_clk,
+ input wire sys_rst,
+ input wire sys_ena,
+
+ input wire [13: 0] sys_eim_addr,
+ input wire sys_eim_wr,
+ input wire sys_eim_rd,
+ output wire [31 : 0] sys_read_data,
+ input wire [31 : 0] sys_write_data
+ );
+
+
+ //
+ // Output Register
+ //
+ reg [31: 0] tmp_read_data;
+ assign sys_read_data = tmp_read_data;
+
+
+ modexp modexp_inst(
+ .clk(sys_clk),
+ .reset_n(~sys_rst),
+ .cs(sys_ena),
+ .we(sys_eim_wr),
+ .address(sys_eim_addr[11 : 0]),
+ .write_data(sys_write_data),
+ .read_data(sys_read_data)
+ );
+
+endmodule // math_selector
+
+//======================================================================
+// EOF math_selector.v
+//======================================================================