Adding math segment in core selector.

1 files changed, 44 insertions, 12 deletions

diff --git a/core_selector/src/rtl/core_selector.v b/core_selector/src/rtl/core_selector.v
index 275089f..35c87e5 100644
--- a/core_selector/src/rtl/core_selector.v
+++ b/core_selector/src/rtl/core_selector.v
@@ -10,7 +10,7 @@
 //
 // Author: Pavel Shatov
 // Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
@@ -54,19 +54,19 @@ module core_selector
    input wire          noise,
    output wire [7 : 0] debug
    );
-   
-   
+
+
    /* Three upper bits of address [16:14] are used to select memory segment.
     * There can be eight segments. So far segment 0 is used for global
     * registers, segment 1 is used for hashes, segment 2 is reserved for
     * random number generators, segment 3 is reserved for chiphers. Other
     * segments are not used so far.
     */
-   
+
    /* Every segment has its own memory map, take at look at corresponding
     * selectors for more information.
     */
-   
+
    //----------------------------------------------------------------
    // Address Decoder
    //----------------------------------------------------------------
@@ -83,7 +83,8 @@ module core_selector
    `define      USE_SEGMENT_GLOBALS
    `define      USE_SEGMENT_HASHES
    `define      USE_SEGMENT_RNGS
-// `define      USE_SEGMENT_CIPHERS
+//   `define      USE_SEGMENT_CIPHERS
+   `define      USE_SEGMENT_MATH
 
 
    //----------------------------------------------------------------
@@ -93,6 +94,7 @@ module core_selector
    localparam   SEGMENT_ADDR_HASHES     = 3'd1;
    localparam   SEGMENT_ADDR_RNGS       = 3'd2;
    localparam   SEGMENT_ADDR_CIPHERS    = 3'd3;
+   localparam   SEGMENT_ADDR_MATH       = 3'd4;
 
 
    //----------------------------------------------------------------
@@ -111,7 +113,7 @@ module core_selector
 
       .sys_eim_addr(addr_segment_int),
       .sys_eim_wr(sys_eim_wr),
-      .sys_eim_rd(sys_eim_rd),                                          
+      .sys_eim_rd(sys_eim_rd),
       .sys_write_data(sys_write_data),
       .sys_read_data(segment_globals_read_data),
       .sys_error(segment_globals_error)
@@ -135,7 +137,7 @@ module core_selector
 
       .sys_eim_addr(addr_segment_int),
       .sys_eim_wr(sys_eim_wr),
-      .sys_eim_rd(sys_eim_rd),                                          
+      .sys_eim_rd(sys_eim_rd),
       .sys_write_data(sys_write_data),
       .sys_read_data(segment_hashes_read_data),
       .sys_error(segment_hashes_error)
@@ -159,7 +161,7 @@ module core_selector
 
       .sys_eim_addr(addr_segment_int),
       .sys_eim_wr(sys_eim_wr),
-      .sys_eim_rd(sys_eim_rd),                                          
+      .sys_eim_rd(sys_eim_rd),
       .sys_write_data(sys_write_data),
       .sys_read_data(segment_rngs_read_data),
       .sys_error(segment_rngs_error),
@@ -186,7 +188,7 @@ module core_selector
 
       .sys_eim_addr(addr_segment_int),
       .sys_eim_wr(sys_eim_wr),
-      .sys_eim_rd(sys_eim_rd),                                          
+      .sys_eim_rd(sys_eim_rd),
       .sys_write_data(sys_write_data),
       .sys_read_data(segment_ciphers_read_data),
       .sys_error(segment_ciphers_error)
@@ -195,13 +197,37 @@ module core_selector
 
 
    //----------------------------------------------------------------
+   // MATH Segment
+   //----------------------------------------------------------------
+   `ifdef USE_SEGMENT_MATH
+   wire         segment_enable_math = (addr_segment == SEGMENT_ADDR_MATH) ? 1'b1 : 1'b0;
+   wire [31: 0] segment_math_read_data;
+   wire         segment_math_error;
+
+   math_selector math_inst
+     (
+      .sys_clk(sys_clk),
+      .sys_rst(sys_rst),
+      .sys_ena(segment_enable_math),
+
+      .sys_eim_addr(addr_segment_int),
+      .sys_eim_wr(sys_eim_wr),
+      .sys_eim_rd(sys_eim_rd),
+      .sys_write_data(sys_write_data),
+      .sys_read_data(segment_math_read_data),
+      .sys_error(segment_math_error)
+      );
+   `endif
+
+
+   //----------------------------------------------------------------
    // Output (Read Data) Bus
    //----------------------------------------------------------------
    reg [31: 0]  sys_read_data_reg;
    assign       sys_read_data = sys_read_data_reg;
    reg          sys_error_reg;
    assign       sys_error = sys_error_reg;
-   
+
    always @*
      //
      case (addr_segment)
@@ -233,13 +259,19 @@ module core_selector
             sys_error_reg     = segment_ciphers_error;
          end
    `endif
+   `ifdef USE_SEGMENT_CIPHERS
+       SEGMENT_ADDR_MATH:
+         begin
+            sys_read_data_reg = segment_math_read_data;
+            sys_error_reg     = segment_math_error;
+         end
+   `endif
        default:
          begin
             sys_read_data_reg = {32{1'b0}};
             sys_error_reg = 1;
          end
      endcase
-   
 
 endmodule