Rearrange cores.

6 files changed, 882 insertions, 0 deletions

diff --git a/README.md b/README.md
new file mode 100644
index 0000000..0630499
--- /dev/null
+++ b/README.md
@@ -0,0 +1,8 @@
+platform/common
+===============
+
+Support code that is used to build projects, but not tied to a particular platform.
+
+## Introduction ##
+At present, this contains core_selector, a set of muxes to select a core
+by the most significant address bits of a memory-like architecture.
diff --git a/core_selector/src/rtl/cipher_selector.v b/core_selector/src/rtl/cipher_selector.v
new file mode 100644
index 0000000..c7ae812
--- /dev/null
+++ b/core_selector/src/rtl/cipher_selector.v
@@ -0,0 +1,117 @@
+//======================================================================
+//
+// cipher_selector.v
+// -----------------
+// Top level wrapper that creates the Cryptech coretest system.
+// The wrapper contains instances of external interface, coretest
+// and the core to be tested. And if more than one core is
+// present the wrapper also includes address and data muxes.
+//
+//
+// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov
+// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+//   this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module cipher_selector
+  (
+   input wire           sys_clk,
+   input wire           sys_rst,
+   input wire           sys_ena,
+
+   input wire [13: 0]   sys_eim_addr,
+   input wire           sys_eim_wr,
+   input wire           sys_eim_rd,
+   output wire [31 : 0] sys_read_data,
+   input wire [31 : 0]  sys_write_data
+   );
+
+
+   //
+   // Output Register
+   //
+   reg [31: 0]          tmp_read_data;
+   assign sys_read_data = tmp_read_data;
+   
+
+   /* So far we have no CIPHER cores, let's make some dummy 32-bit registers here
+    * to prevent ISE from complaining that we don't use input ports.
+    */
+   
+   reg [31: 0]          reg_dummy_first;
+   reg [31: 0]          reg_dummy_second;
+   reg [31: 0]          reg_dummy_third;
+   
+   always @(posedge sys_clk)
+     //
+     if (sys_rst)
+       begin
+          reg_dummy_first  <= {8{4'hD}};
+          reg_dummy_second <= {8{4'hE}};
+          reg_dummy_third  <= {8{4'hF}};
+       end
+     else if (sys_ena)
+       begin
+          //
+          if (sys_eim_wr)
+            begin
+               //
+               // WRITE handler
+               //
+               case (sys_eim_addr)
+                 14'd0: reg_dummy_first  <= sys_write_data;
+                 14'd1: reg_dummy_second <= sys_write_data;
+                 14'd2: reg_dummy_third  <= sys_write_data;
+               endcase
+               //
+            end
+          //
+          if (sys_eim_rd)
+            begin
+               //
+               // READ handler
+               //
+               case (sys_eim_addr)
+                 14'd0: tmp_read_data   <= reg_dummy_first;
+                 14'd1: tmp_read_data   <= reg_dummy_second;
+                 14'd2: tmp_read_data   <= reg_dummy_third;
+                 //
+                 default: tmp_read_data <= {32{1'b0}};  // read non-existent locations as zeroes
+               endcase
+               //
+            end
+          //
+       end
+   
+
+endmodule
+
+//======================================================================
+// EOF cipher_selector.v
+//======================================================================
diff --git a/core_selector/src/rtl/core_selector.v b/core_selector/src/rtl/core_selector.v
new file mode 100644
index 0000000..1cd1d94
--- /dev/null
+++ b/core_selector/src/rtl/core_selector.v
@@ -0,0 +1,212 @@
+//======================================================================
+//
+// core_selector.v
+// ---------------
+// Top level wrapper that creates the Cryptech coretest system.
+// The wrapper contains instances of external interface, coretest
+// and the core to be tested. And if more than one core is
+// present the wrapper also includes address and data muxes.
+//
+//
+// Author: Pavel Shatov
+// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+//   this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module core_selector
+  (
+   input wire          sys_clk,
+   input wire          sys_rst,
+
+   input wire [16: 0]  sys_eim_addr,
+   input wire          sys_eim_wr,
+   input wire          sys_eim_rd,
+   output wire [31: 0] sys_read_data,
+   input wire [31: 0]  sys_write_data
+   );
+   
+   
+   /* Three upper bits of address [16:14] are used to select memory segment.
+    * There can be eight segments. So far segment 0 is used for global
+    * registers, segment 1 is used for hashes, segment 2 is reserved for
+    * random number generators, segment 3 is reserved for chiphers. Other
+    * segments are not used so far.
+    */
+   
+   /* Every segment has its own memory map, take at look at corresponding
+    * selectors for more information.
+    */
+   
+   //----------------------------------------------------------------
+   // Segment Decoder
+   //----------------------------------------------------------------
+   localparam   SEGMENT_ADDR_GLOBALS    = 3'd0;
+   localparam   SEGMENT_ADDR_HASHES     = 3'd1;
+   localparam   SEGMENT_ADDR_RNGS       = 3'd2;
+   localparam   SEGMENT_ADDR_CIPHERS    = 3'd3;
+
+   wire [ 2: 0] addr_segment            = sys_eim_addr[16:14];  //  3 upper bits are decoded here
+   wire [13: 0] addr_segment_int        = sys_eim_addr[13: 0];  // 14 lower bits are decoded individually
+   // in corresponding segment selectors
+   
+   wire [31: 0] segment_globals_read_data;              // data read from GLOBALS segment
+   wire [31: 0] segment_hashes_read_data;               // data read from HASHES segment
+   wire [31: 0] segment_rngs_read_data;                 // data read from RNGS segment
+   wire [31: 0] segment_ciphers_read_data;              // data read from CIPHERS segment
+   
+   wire         segment_enable_globals  = (addr_segment == SEGMENT_ADDR_GLOBALS) ? 1'b1 : 1'b0; // GLOBALS segment is being addressed
+   wire         segment_enable_hashes   = (addr_segment == SEGMENT_ADDR_HASHES)  ? 1'b1 : 1'b0; // HASHES segment is being addressed
+   wire         segment_enable_rngs     = (addr_segment == SEGMENT_ADDR_RNGS)    ? 1'b1 : 1'b0; // RNGS segment is being addressed
+   wire         segment_enable_ciphers  = (addr_segment == SEGMENT_ADDR_CIPHERS) ? 1'b1 : 1'b0; // CIPHERS segment is being addressed
+   
+   
+   //----------------------------------------------------------------
+   // Output (Read Data) Bus
+   //----------------------------------------------------------------
+   reg [31: 0]  sys_read_data_reg;
+   assign sys_read_data = sys_read_data_reg;
+   
+   always @*
+     //
+     case (addr_segment)
+       SEGMENT_ADDR_GLOBALS:    sys_read_data_reg = segment_globals_read_data;
+       SEGMENT_ADDR_HASHES:     sys_read_data_reg = segment_hashes_read_data;
+       SEGMENT_ADDR_RNGS:       sys_read_data_reg = segment_rngs_read_data;
+       SEGMENT_ADDR_CIPHERS:    sys_read_data_reg = segment_ciphers_read_data;
+       default:                 sys_read_data_reg = {32{1'b0}};
+     endcase
+   
+   
+   
+   //----------------------------------------------------------------
+   // GLOBAL Core Selector
+   //
+   // This selector is used to map core registers into
+   // EIM address space and select which core to send EIM read and
+   // write operations to.
+   //----------------------------------------------------------------
+   global_selector globals
+     (
+      .sys_clk(sys_clk),
+      .sys_rst(sys_rst),
+
+      .sys_ena(segment_enable_globals),         // only enable active selector
+
+      .sys_eim_addr(addr_segment_int),          // we only connect 14 lower bits of address here,
+      // because we have already decoded 3 upper bits earlier,
+      // every segment can have its own address decoder.
+      .sys_eim_wr(sys_eim_wr),
+      .sys_eim_rd(sys_eim_rd),                                          
+
+      .sys_write_data(sys_write_data),
+      .sys_read_data(segment_globals_read_data)  // output from GLOBALS segment
+      );
+   
+   
+   //----------------------------------------------------------------
+   // HASH Core Selector
+   //
+   // This selector is used to map core registers into
+   // EIM address space and select which core to send EIM read and
+   // write operations to.
+   //----------------------------------------------------------------
+   hash_selector hashes
+     (
+      .sys_clk(sys_clk),
+      .sys_rst(sys_rst),
+
+      .sys_ena(segment_enable_hashes),          // only enable active selector
+
+      .sys_eim_addr(addr_segment_int),          // we only connect 14 lower bits of address here,
+      // because we have already decoded 3 upper bits earlier,
+      // every segment can have its own address decoder.
+      .sys_eim_wr(sys_eim_wr),
+      .sys_eim_rd(sys_eim_rd),                                          
+
+      .sys_write_data(sys_write_data),
+      .sys_read_data(segment_hashes_read_data)  // output from HASHES segment
+      );
+   
+   
+   //----------------------------------------------------------------
+   // RNG Selector
+   //
+   // This selector is used to map random number generator registers into
+   // EIM address space and select which RNG to send EIM read and
+   // write operations to. So far there are no RNG cores.
+   //----------------------------------------------------------------
+   rng_selector rngs
+     (
+      .sys_clk(sys_clk),
+      .sys_rst(sys_rst),
+
+      .sys_ena(segment_enable_rngs),            // only enable active selector
+
+      .sys_eim_addr(addr_segment_int),          // we only connect 14 lower bits of address here,
+      // because we have already decoded 3 upper bits earlier,
+      // every segment can have its own address decoder.
+      .sys_eim_wr(sys_eim_wr),
+      .sys_eim_rd(sys_eim_rd),          
+
+      .sys_write_data(sys_write_data),
+      .sys_read_data(segment_rngs_read_data)    // output from RNGS segment
+      );
+   
+   
+   //----------------------------------------------------------------
+   // CIPHER Selector
+   //
+   // This selector is used to map cipher registers into
+   // EIM address space and select which CIPHER to send EIM read and
+   // write operations to. So far there are no CIPHER cores.
+   //----------------------------------------------------------------
+   cipher_selector ciphers
+     (
+      .sys_clk(sys_clk),
+      .sys_rst(sys_rst),
+
+      .sys_ena(segment_enable_ciphers),         // only enable active selector
+
+      .sys_eim_addr(addr_segment_int),          // we only connect 14 lower bits of address here,
+      // because we have already decoded 3 upper bits earlier,
+      // every segment can have its own address decoder.
+      .sys_eim_wr(sys_eim_wr),
+      .sys_eim_rd(sys_eim_rd),          
+
+      .sys_write_data(sys_write_data),
+      .sys_read_data(segment_ciphers_read_data) // output from CIPHERS segment
+      );
+   
+   
+endmodule
+
+
+//======================================================================
+// EOF eim_memory.v
+//======================================================================
diff --git a/core_selector/src/rtl/global_selector.v b/core_selector/src/rtl/global_selector.v
new file mode 100644
index 0000000..993f237
--- /dev/null
+++ b/core_selector/src/rtl/global_selector.v
@@ -0,0 +1,196 @@
+//======================================================================
+//
+// global_selector.v
+// -----------------
+// Top level wrapper that creates the Cryptech coretest system.
+// The wrapper contains instances of external interface, coretest
+// and the core to be tested. And if more than one core is
+// present the wrapper also includes address and data muxes.
+//
+//
+// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov
+// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+//   this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module global_selector
+  (
+   input wire           sys_clk,
+   input wire           sys_rst,
+   input wire           sys_ena,
+
+   input wire [13: 0]   sys_eim_addr,
+   input wire           sys_eim_wr,
+   input wire           sys_eim_rd,
+   output wire [31 : 0] sys_read_data,
+   input wire [31 : 0]  sys_write_data
+   );
+
+   
+   //----------------------------------------------------------------
+   // Address Decoder
+   //----------------------------------------------------------------
+   wire [ 5: 0]         addr_core_num   = sys_eim_addr[13: 8];  // upper 6 bits specify core being addressed
+   wire [ 7: 0]         addr_core_reg   = sys_eim_addr[ 7: 0];  // lower 8 bits specify register offset in core
+
+
+   //----------------------------------------------------------------
+   // Core Address Table
+   //----------------------------------------------------------------
+   localparam   CORE_ADDR_BOARD_REGS    = 6'd0;
+   localparam   CORE_ADDR_COMM_REGS     = 6'd1;
+   
+   
+   //----------------------------------------------------------------
+   // Board-Level Registers
+   //----------------------------------------------------------------
+   wire [31: 0]         read_data_board;
+   wire                 enable_board = sys_ena && (addr_core_num == CORE_ADDR_BOARD_REGS);
+   board_regs board_regs
+     (
+      .clk(sys_clk),
+      .rst(sys_rst),
+
+      .cs(enable_board & (sys_eim_rd | sys_eim_wr)),
+      .we(sys_eim_wr),
+
+      .address(addr_core_reg),
+      .write_data(sys_write_data),
+      .read_data(read_data_board)
+      );
+   
+   
+   //----------------------------------------------------------------
+   // Communication-Channel Registers
+   //----------------------------------------------------------------
+   wire [31: 0]         read_data_comm;
+   wire                 enable_comm = sys_ena && (addr_core_num == CORE_ADDR_COMM_REGS);
+   comm_regs comm_regs
+     (
+      .clk(sys_clk),
+      .rst(sys_rst),
+
+      .cs(enable_comm & (sys_eim_rd | sys_eim_wr)),
+      .we(sys_eim_wr),
+
+      .address(addr_core_reg),
+      .write_data(sys_write_data),
+      .read_data(read_data_comm)
+      );
+   
+   
+   //----------------------------------------------------------------
+   // SHA-1
+   //----------------------------------------------------------------
+   `ifdef USE_CORE_SHA1
+   wire [31: 0]         read_data_sha1;
+   wire                 enable_sha1 = sys_ena && (addr_core_num == CORE_ADDR_SHA1);
+   sha1 sha1_inst
+     (
+      .clk(sys_clk),
+      .reset_n(~sys_rst),
+
+      .cs(enable_sha1 & (sys_eim_rd | sys_eim_wr)),
+      .we(sys_eim_wr),
+
+      .address(addr_core_reg),
+      .write_data(sys_write_data),
+      .read_data(read_data_sha1)
+      );
+   `endif
+   
+   
+   //----------------------------------------------------------------
+   // SHA-256
+   //----------------------------------------------------------------
+   `ifdef USE_CORE_SHA256
+   wire [31: 0]         read_data_sha256;
+   wire                 enable_sha256 = sys_ena && (addr_core_num == CORE_ADDR_SHA256);
+   sha256 sha256_inst
+     (
+      .clk(sys_clk),
+      .reset_n(~sys_rst),
+
+      .cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)),
+      .we(sys_eim_wr),
+
+      .address(addr_core_reg),
+      .write_data(sys_write_data),
+      .read_data(read_data_sha256)
+      );
+   `endif
+   
+   
+   //----------------------------------------------------------------
+   // SHA-512
+   //----------------------------------------------------------------
+   `ifdef USE_CORE_SHA512
+   wire [31: 0]         read_data_sha512;
+   wire                 enable_sha512 = sys_ena && (addr_core_num == CORE_ADDR_SHA512);
+   sha512 sha512_inst
+     (
+      .clk(sys_clk),
+      .reset_n(~sys_rst),
+
+      .cs(enable_sha512 & (sys_eim_rd | sys_eim_wr)),
+      .we(sys_eim_wr),
+
+      .address(addr_core_reg),
+      .write_data(sys_write_data),
+      .read_data(read_data_sha512)
+      );
+   `endif
+   
+   
+   //----------------------------------------------------------------
+   // Output (Read Data) Multiplexor
+   //----------------------------------------------------------------
+   reg [31: 0]          sys_read_data_mux;
+   assign sys_read_data = sys_read_data_mux;
+   
+   always @*
+     //
+     case (addr_core_num)
+       //
+       CORE_ADDR_BOARD_REGS:
+         sys_read_data_mux = read_data_board;
+       CORE_ADDR_COMM_REGS:
+         sys_read_data_mux = read_data_comm;
+       //
+       default:
+         sys_read_data_mux = {32{1'b0}};
+       //
+     endcase
+
+
+endmodule
+
+//======================================================================
+// EOF global_selector.v
+//======================================================================
diff --git a/core_selector/src/rtl/hash_selector.v b/core_selector/src/rtl/hash_selector.v
new file mode 100644
index 0000000..66806b6
--- /dev/null
+++ b/core_selector/src/rtl/hash_selector.v
@@ -0,0 +1,237 @@
+//======================================================================
+//
+// hash_selector.v
+// ---------------
+// Top level wrapper that creates the Cryptech coretest system.
+// The wrapper contains instances of external interface, coretest
+// and the core to be tested. And if more than one core is
+// present the wrapper also includes address and data muxes.
+//
+//
+// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov
+// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+//   this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module hash_selector
+  (
+   input wire           sys_clk,
+   input wire           sys_rst,
+   input wire           sys_ena,
+
+   input wire [13 : 0]  sys_eim_addr,
+   input wire           sys_eim_wr,
+   input wire           sys_eim_rd,
+   output wire [31 : 0] sys_read_data,
+   input wire [31 : 0]  sys_write_data
+   );
+
+   /* In this memory segment (HASHES) we have 14 address bits. Every core has
+    * 8-bit internal address space, so we can have up to 2^(14-8) = 64 cores here.
+    *
+    * So far we have three cores: SHA-1, SHA-256 and SHA-512.
+    */
+   
+   /*********************************************************
+    * To add new HASH core named XXX follow the steps below *
+    *********************************************************
+    *
+    * 1. Add corresponding `define under "List of Available Cores", this will
+    *    allow users to exclude your core from implementation to save some
+    *    slices in case they don't need it.
+    *
+    *    `define    USE_CORE_XXX
+XXX define in wrapper core
+    *
+    *
+    * 2. Choose address of your new core and add corresponding line under
+    *    "Core Address Table". Core addresses can be in the range from 0 to 63
+    *    inclusively.
+    *
+    *    localparam CORE_ADDR_XXX   = 6'dN;
+XXX move to `define in wrapper core??
+    *
+    *
+    * 3. Add instantiation of your new core after all existing cores
+    *    surrounded by conditional synthesis directives.
+    *    You also need a 32-bit output (read data) bus for your core and an
+    *    enable flag. Note that sys_rst in an active-high sync reset signal.
+    *
+    *   `ifdef USE_CORE_XXX
+    *       wire [31: 0]    read_data_xxx;
+    *       wire            enable_xxx = sys_ena && (addr_core_num == CORE_ADDR_XXX);
+    *       xxx xxx_inst
+    *       (
+    *       .clk(sys_clk),
+    *       .reset_n(~sys_rst),
+    *       .cs(enable_xxx & (sys_eim_rd | sys_eim_wr)),
+    *       .we(sys_eim_wr),
+    *       .address(addr_core_reg),
+    *       .write_data(sys_write_data),
+    *       .read_data(read_data_xxx),
+    *       .error()
+    *       );
+    *    `endif
+    *
+    *
+    * 4. Add previously created data bus to "Output (Read Data) Multiplexor"
+    *    in the end of this file.
+    *
+    *   `ifdef USE_CORE_XXX
+    *       CORE_ADDR_XXX:
+    *           sys_read_data_mux = read_data_xxx;
+    *   `endif
+    *
+    */
+
+
+   //----------------------------------------------------------------
+   // Address Decoder
+   //----------------------------------------------------------------
+   wire [ 5: 0]         addr_core_num   = sys_eim_addr[13: 8];  // upper 6 bits specify core being addressed
+   wire [ 7: 0]         addr_core_reg   = sys_eim_addr[ 7: 0];  // lower 8 bits specify register offset in core
+
+
+   /* We can comment following lines to exclude cores from implementation
+    * in case we run out of slices.
+    */
+   
+   //----------------------------------------------------------------
+   // List of Available Cores
+   //----------------------------------------------------------------
+   `define  USE_CORE_SHA1
+   `define  USE_CORE_SHA256
+   `define  USE_CORE_SHA512
+   
+   
+   //----------------------------------------------------------------
+   // Core Address Table
+   //----------------------------------------------------------------
+   localparam   CORE_ADDR_SHA1          = 6'd0;
+   localparam   CORE_ADDR_SHA256        = 6'd1;
+   localparam   CORE_ADDR_SHA512        = 6'd2;
+   
+   
+   //----------------------------------------------------------------
+   // SHA-1
+   //----------------------------------------------------------------
+   `ifdef USE_CORE_SHA1
+   wire [31: 0]         read_data_sha1;
+   wire                 enable_sha1 = sys_ena && (addr_core_num == CORE_ADDR_SHA1);
+   sha1 sha1_inst
+     (
+      .clk(sys_clk),
+      .reset_n(~sys_rst),
+
+      .cs(enable_sha1 & (sys_eim_rd | sys_eim_wr)),
+      .we(sys_eim_wr),
+
+      .address(addr_core_reg),
+      .write_data(sys_write_data),
+      .read_data(read_data_sha1)
+      );
+   `endif
+   
+   
+   //----------------------------------------------------------------
+   // SHA-256
+   //----------------------------------------------------------------
+   `ifdef USE_CORE_SHA256
+   wire [31: 0]         read_data_sha256;
+   wire                 enable_sha256 = sys_ena && (addr_core_num == CORE_ADDR_SHA256);
+   sha256 sha256_inst
+     (
+      .clk(sys_clk),
+      .reset_n(~sys_rst),
+
+      .cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)),
+      .we(sys_eim_wr),
+
+      .address(addr_core_reg),
+      .write_data(sys_write_data),
+      .read_data(read_data_sha256)
+      );
+   `endif
+   
+   
+   //----------------------------------------------------------------
+   // SHA-512
+   //----------------------------------------------------------------
+   `ifdef USE_CORE_SHA512
+   wire [31: 0]         read_data_sha512;
+   wire                 enable_sha512 = sys_ena && (addr_core_num == CORE_ADDR_SHA512);
+   sha512 sha512_inst
+     (
+      .clk(sys_clk),
+      .reset_n(~sys_rst),
+
+      .cs(enable_sha512 & (sys_eim_rd | sys_eim_wr)),
+      .we(sys_eim_wr),
+
+      .address(addr_core_reg),
+      .write_data(sys_write_data),
+      .read_data(read_data_sha512)
+      );
+   `endif
+   
+   
+   //----------------------------------------------------------------
+   // Output (Read Data) Multiplexor
+   //----------------------------------------------------------------
+   reg [31: 0]          sys_read_data_mux;
+   assign sys_read_data = sys_read_data_mux;
+   
+   always @*
+     //
+     case (addr_core_num)
+       //
+   `ifdef USE_CORE_SHA1
+       CORE_ADDR_SHA1:
+         sys_read_data_mux = read_data_sha1;
+   `endif
+   `ifdef USE_CORE_SHA256
+       CORE_ADDR_SHA256:
+         sys_read_data_mux = read_data_sha256;
+   `endif
+   `ifdef USE_CORE_SHA512
+       CORE_ADDR_SHA512:
+         sys_read_data_mux = read_data_sha512;
+   `endif
+       //
+       default:
+         sys_read_data_mux = {32{1'b0}};
+       //
+     endcase
+
+
+endmodule
+
+//======================================================================
+// EOF hash_selector.v
+//======================================================================
diff --git a/core_selector/src/rtl/rng_selector.v b/core_selector/src/rtl/rng_selector.v
new file mode 100644
index 0000000..d88fe82
--- /dev/null
+++ b/core_selector/src/rtl/rng_selector.v
@@ -0,0 +1,112 @@
+//======================================================================
+//
+// rng_selector.v
+// -----------------
+// Top level wrapper that creates the Cryptech coretest system.
+// The wrapper contains instances of external interface, coretest
+// and the core to be tested. And if more than one core is
+// present the wrapper also includes address and data muxes.
+//
+//
+// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov
+// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+//   this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module rng_selector
+  (
+   input wire           sys_clk,
+   input wire           sys_rst,
+   input wire           sys_ena,
+
+   input wire [13: 0]   sys_eim_addr,
+   input wire           sys_eim_wr,
+   input wire           sys_eim_rd,
+   output wire [31 : 0] sys_read_data,
+   input wire [31 : 0]  sys_write_data
+   );
+
+   
+   //
+   // Output Register
+   //
+   reg [31: 0]          tmp_read_data;
+   assign sys_read_data = tmp_read_data;
+   
+
+   /* So far we have no RNG cores, let's make some dummy 32-bit registers here
+    * to prevent ISE from complaining that we don't use input ports.
+    */
+   
+   reg [31: 0]          reg_dummy_first;
+   reg [31: 0]          reg_dummy_second;
+   reg [31: 0]          reg_dummy_third;
+   
+   always @(posedge sys_clk)
+     //
+     if (sys_rst) begin
+        reg_dummy_first  <= {8{4'hA}};
+        reg_dummy_second <= {8{4'hB}};
+        reg_dummy_third  <= {8{4'hC}};
+     end else if (sys_ena) begin
+        //
+        if (sys_eim_wr) begin
+           //
+           // WRITE handler
+           //
+           case (sys_eim_addr)
+             14'd0: reg_dummy_first     <= sys_write_data;
+             14'd1: reg_dummy_second    <= sys_write_data;
+             14'd2: reg_dummy_third     <= sys_write_data;
+           endcase
+           //
+        end
+        //
+        if (sys_eim_rd) begin
+           //
+           // READ handler
+           //
+           case (sys_eim_addr)
+             14'd0: tmp_read_data       <= reg_dummy_first;
+             14'd1: tmp_read_data       <= reg_dummy_second;
+             14'd2: tmp_read_data       <= reg_dummy_third;
+             //
+             default:
+               tmp_read_data    <= {32{1'b0}};  // read non-existent locations as zeroes
+           endcase
+           //
+        end
+        //
+     end
+
+endmodule
+
+//======================================================================
+// EOF rng_selector.v
+//======================================================================